[llvm] 0c390c2 - Revert "[ARM] Fix IT block generation after Thumb2SizeReduce with -Oz"

[David Green via llvm-commits]

Author: David Green
Date: 2020-08-13T22:40:36+01:00
New Revision: 0c390c22a5af485a482de884134097eeee068cfa

URL: https://github.com/llvm/llvm-project/commit/0c390c22a5af485a482de884134097eeee068cfa
DIFF: https://github.com/llvm/llvm-project/commit/0c390c22a5af485a482de884134097eeee068cfa.diff

LOG: Revert "[ARM] Fix IT block generation after Thumb2SizeReduce with -Oz"

This reverts commit 18279a54b5d3382874924d6a3c7775b7e22598dc as it is
causing some chromium android test problems.

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/test/CodeGen/Thumb2/constant-hoisting.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 8be1d10eba03..ab7aaa597b4b 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -587,13 +587,6 @@ bool ARMBaseInstrInfo::DefinesPredicate(
     const MachineOperand &MO = MI.getOperand(i);
     if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
         (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
-
-      // Filter out T1 instructions that have a dead CPSR,
-      // allowing IT blocks to be generated containing T1 instructions
-      const MCInstrDesc &MCID = MI.getDesc();
-      if (MCID.TSFlags & ARMII::ThumbArithFlagSetting && MO.isDead())
-        continue;
-
       Pred.push_back(MO);
       Found = true;
     }

diff  --git a/llvm/test/CodeGen/Thumb2/constant-hoisting.ll b/llvm/test/CodeGen/Thumb2/constant-hoisting.ll
index a106900dc3e9..5c8f934ce61d 100644
--- a/llvm/test/CodeGen/Thumb2/constant-hoisting.ll
+++ b/llvm/test/CodeGen/Thumb2/constant-hoisting.ll
@@ -37,25 +37,26 @@ define i32 @test_values(i32 %a, i32 %b) minsize optsize {
 ; CHECK-V7M:         mov r2, r0
 ; CHECK-V7M-NEXT:    ldr r0, .LCPI0_0
 ; CHECK-V7M-NEXT:    cmp r2, #50
-; CHECK-V7M-NEXT:    beq .LBB0_3
+; CHECK-V7M-NEXT:    beq .LBB0_5
 ; CHECK-V7M-NEXT:    cmp r2, #1
-; CHECK-V7M-NEXT:    ittt eq
-; CHECK-V7M-NEXT:    addeq r0, r1
-; CHECK-V7M-NEXT:    addeq r0, #1
-; CHECK-V7M-NEXT:    bxeq lr
+; CHECK-V7M-NEXT:    beq .LBB0_7
 ; CHECK-V7M-NEXT:    cmp r2, #30
-; CHECK-V7M-NEXT:    ittt eq
-; CHECK-V7M-NEXT:    addeq r0, r1
-; CHECK-V7M-NEXT:    addeq r0, #2
-; CHECK-V7M-NEXT:    bxeq lr
-; CHECK-V7M-NEXT:    cbnz r2, .LBB0_4
-; CHECK-V7M-NEXT:  .LBB0_2:
+; CHECK-V7M-NEXT:    beq .LBB0_8
+; CHECK-V7M-NEXT:    cbnz r2, .LBB0_6
 ; CHECK-V7M-NEXT:    add r0, r1
 ; CHECK-V7M-NEXT:    bx lr
-; CHECK-V7M-NEXT:  .LBB0_3:
+; CHECK-V7M-NEXT:  .LBB0_5:
 ; CHECK-V7M-NEXT:    add r0, r1
 ; CHECK-V7M-NEXT:    adds r0, #4
-; CHECK-V7M-NEXT:  .LBB0_4:
+; CHECK-V7M-NEXT:  .LBB0_6:
+; CHECK-V7M-NEXT:    bx lr
+; CHECK-V7M-NEXT:  .LBB0_7:
+; CHECK-V7M-NEXT:    add r0, r1
+; CHECK-V7M-NEXT:    adds r0, #1
+; CHECK-V7M-NEXT:    bx lr
+; CHECK-V7M-NEXT:  .LBB0_8:
+; CHECK-V7M-NEXT:    add r0, r1
+; CHECK-V7M-NEXT:    adds r0, #2
 ; CHECK-V7M-NEXT:    bx lr
 ; CHECK-V7M-NEXT:    .p2align 2
 ; CHECK-V7M-NEXT:  .LCPI0_0: