[PATCH] D85931: AMDGPU: Remove SIFixupVectorISel pass

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, kerbowa, b-sumner, ronlieb.
Herald added subscribers: jfb, hiraditya, t-tye, tpr, dstuttard, yaxunl, mgorny, nhaehnle, jvesely, kzhuravl.
Herald added a project: LLVM.
arsenm requested review of this revision.
Herald added a subscriber: wdng.

This was only used for matching the saddr addressing mode of global
instructions, but this was not implemented correctly. The instruction
definitions aren't even correct, and are defined as using a 64-bit
VGPR component. Eliminate this pass to enable correcting the
instruction definitions. A new matching implementation can work in
GlobalISel or relying on DAG divergence information for the base
address.


https://reviews.llvm.org/D85931

Files:
  llvm/lib/Target/AMDGPU/AMDGPU.h
  llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  llvm/lib/Target/AMDGPU/CMakeLists.txt
  llvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp
  llvm/test/CodeGen/AMDGPU/disable_form_clauses.ll
  llvm/test/CodeGen/AMDGPU/ds_write2.ll
  llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
  llvm/test/CodeGen/AMDGPU/global-load-store-atomics.mir
  llvm/test/CodeGen/AMDGPU/global-saddr.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll
  llvm/test/CodeGen/AMDGPU/madak.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-store.ll
  llvm/test/CodeGen/AMDGPU/memory_clause.ll
  llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D85931.285485.patch
Type: text/x-patch
Size: 56515 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200813/1051cf76/attachment.bin>