[PATCH] D85165: [X86][MC][Target] Initial backend support a tune CPU to support -mtune

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D85165#2211246 <https://reviews.llvm.org/D85165#2211246>, @RKSimon wrote:

> In D85165#2192126 <https://reviews.llvm.org/D85165#2192126>, @efriedma wrote:
>
>> Do the x86 scheduling models do something sane with "impossible" instructions, like if you use AVX512 instructions with Atom tuning?
>
> AFAICT it should still use the model from the base cpu, and just apply the fast/slow feature flags from the tune cpu - so it shouldn't permit any mismatches - is that right?

This patch changes the scheduler model selection to the tune CPU. See the change to MCSubtargetInfo::InitMCProcessorInfo

> In D85165#2193969 <https://reviews.llvm.org/D85165#2193969>, @craig.topper wrote:
>
>> @andreadb @RKSimon or @efriedma do any of you have suggestions for simple scheduler tests for this? I was hoping I could use -print-schedule like we used to but that no longer exists.
>
> Since I've been working on HADD/SUB recently :-)  Using -mtune=btver2 on a 'slow' base cpu should fold single shuffle HADD patterns. Tests based on other simple feature bits like SlowSHLD should be simple as well. More complex cases like LEA/NOPs etc. might work but could be trickier.

Those are all based on feature flags right? I was looking for some easy test to prove the scheduler is following the tune CPU.


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