[PATCH] D84416: [RISCV] add the assemble and disassemble support of Zvlsseg instructions

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCV.td:152
+    : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
+                       "'Zvlsseg' (Vector segment load/store instructions)">;
+def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">,
----------------
```
def FeatureStdExtZvlsseg
    : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
                       "'Zvlsseg' (Vector segment load/store instructions)",
                       [FeatureStdExtV]>;
```


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:131
+                             RISCVWidth width, string opcodestr>
+    : RVInstVLU<nf, width.Value{3}, lumop, width.Value{2-0},
+                (outs VRegOp:$vd),
----------------
RVInstVLU<nf, width.Value{3}, MOPLDUnitStride, lumop, width.Value{2-0}


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:137
+class VStridedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
+    : RVInstVLS<nf, width.Value{3}, width.Value{2-0},
+                (outs VRegOp:$vd),
----------------
RVInstVLS<nf, width.Value{3}, MOPLDStrided, width.Value{2-0}


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:145
+class VIndexedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
+    : RVInstVLX<nf, width.Value{3}, width.Value{2-0},
+                (outs VRegOp:$vd),
----------------
RVInstVLX<nf, width.Value{3}, MOPLDIndexed, width.Value{2-0}


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:181
+// segment store vd, vs3, (rs1), vm
+class VUnitStrideSegmentStore<bits<3> nf, RISCVLSUMOP sumop, 
+                              RISCVWidth width, string opcodestr>
----------------
Remove sumop.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:183
+                              RISCVWidth width, string opcodestr>
+    : RVInstVSU<nf, width.Value{3}, sumop, width.Value{2-0},
+                (outs), (ins VRegOp:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr,
----------------
RVInstVSU<nf, width.Value{3}, MOPSTUnitStride, SUMOPUnitStride, width.Value{2-0},


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:189
+class VStridedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
+    : RVInstVSS<nf, width.Value{3}, width.Value{2-0}, (outs),
+                (ins VRegOp:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm),
----------------
RVInstVSS<nf, width.Value{3}, MOPSTStrided, width.Value{2-0}, (outs),


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:194
+// segment store vd, vs3, (rs1), vs2, vm
+class VIndexedSegmentStore<bits<3> nf, RISCVMOP mop, RISCVWidth width, string opcodestr>
+    : RVInstVSX<nf, width.Value{3}, mop, width.Value{2-0}, (outs),
----------------
Remove mop


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:195
+class VIndexedSegmentStore<bits<3> nf, RISCVMOP mop, RISCVWidth width, string opcodestr>
+    : RVInstVSX<nf, width.Value{3}, mop, width.Value{2-0}, (outs),
+                (ins VRegOp:$vs3, GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm),
----------------
RVInstVSX<nf, width.Value{3}, MOPSTIndexedOrder, width.Value{2-0}, (outs),


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:958
+
+let Predicates = [HasStdExtV, HasStdExtZvlsseg] in {
+  foreach nf=2-8 in {
----------------
HasStdExtZvlsseg is enough.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:978
+
+    def VSSEG#nf#E8_V : VUnitStrideSegmentStore<!add(nf, -1), SUMOPUnitStride, LSWidth8, "vsseg"#nf#"e8.v">;
+    def VSSEG#nf#E16_V : VUnitStrideSegmentStore<!add(nf, -1), SUMOPUnitStride, LSWidth16, "vsseg"#nf#"e16.v">;
----------------
Remove SUMOPUnitStride.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1016
+
+    def VSXSEG#nf#EI8_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth8, "vsxseg"#nf#"ei8.v">;
+    def VSXSEG#nf#EI16_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth16, "vsxseg"#nf#"ei16.v">;
----------------
Remove MOPSTIndexedOrder.


================
Comment at: llvm/test/MC/RISCV/rvv/zvlsseg.s:1
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v,experimental-zvlsseg %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
----------------
+experimental-zvlsseg is enough.


================
Comment at: llvm/test/MC/RISCV/rvv/zvlsseg.s:14
+# CHECK-ENCODING: [0x07,0x04,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 22 <unknown>
----------------
CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)


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  https://reviews.llvm.org/D84416/new/

https://reviews.llvm.org/D84416