[PATCH] D85720: [AArch64][GlobalISel] Handle rtcGPR64RegClassID in AArch64RegisterBankInfo::getRegBankFromRegClass()

[Raul Tambre via Phabricator via llvm-commits]

tambre updated this revision to Diff 285153.
tambre added a comment.

Re-generate test checks


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85720/new/

https://reviews.llvm.org/D85720

Files:
  llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir


Index: llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
@@ -75,6 +75,8 @@
 
   define void @test_gphi_ptr() { ret void }
 
+  define void @test_restricted_tail_call() { ret void }
+
 ...
 
 ---
@@ -888,3 +890,20 @@
     RET_ReallyLR implicit $x0
 
 ...
+
+---
+name:            test_restricted_tail_call
+legalized:       true
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x16, $x17
+    ; CHECK-LABEL: name: test_restricted_tail_call
+    ; CHECK: liveins: $x16, $x17
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x16
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr(s64) = COPY $x17
+    ; CHECK: RET_ReallyLR
+    %0:_(s64) = COPY $x16
+    %1:_(s64) = COPY $x17
+    RET_ReallyLR
+...
Index: llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -261,6 +261,7 @@
   case AArch64::GPR64common_and_GPR64noipRegClassID:
   case AArch64::GPR64noip_and_tcGPR64RegClassID:
   case AArch64::tcGPR64RegClassID:
+  case AArch64::rtcGPR64RegClassID:
   case AArch64::WSeqPairsClassRegClassID:
   case AArch64::XSeqPairsClassRegClassID:
     return getRegBank(AArch64::GPRRegBankID);


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