[llvm] 5d54921 - [VE] Change to promote i32 AND/OR/XOR operations
Kazushi Marukawa via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 12 00:24:01 PDT 2020
Author: Kazushi (Jam) Marukawa
Date: 2020-08-12T16:23:50+09:00
New Revision: 5d549219df1c5c9a619e33d7dca662cd2c44fcda
URL: https://github.com/llvm/llvm-project/commit/5d549219df1c5c9a619e33d7dca662cd2c44fcda
DIFF: https://github.com/llvm/llvm-project/commit/5d549219df1c5c9a619e33d7dca662cd2c44fcda.diff
LOG: [VE] Change to promote i32 AND/OR/XOR operations
VE has only 64 bits AND/OR/XOR instructions. We pretended that VE has 32 bits
instructions also, but doing it increase the number of generated instructions.
Therefore, we decide to promote 32 bits operations and use only 64 bits
instructions in back end. We also avoid pretending that VE has 32 bits LEA
instruction. Update regression tests also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D85726
Added:
Modified:
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/lib/Target/VE/VEInstrInfo.td
llvm/test/CodeGen/VE/cttz.ll
llvm/test/CodeGen/VE/nnd.ll
llvm/test/CodeGen/VE/or.ll
llvm/test/CodeGen/VE/selectccf32c.ll
llvm/test/CodeGen/VE/selectccf64c.ll
llvm/test/CodeGen/VE/selectcci32c.ll
llvm/test/CodeGen/VE/selectcci64c.ll
llvm/test/CodeGen/VE/xor.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index 510dc0f7ab34..a4211d9af4ba 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -696,6 +696,12 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
setOperationAction(ISD::CTLZ, IntVT, Act);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, IntVT, Act);
setOperationAction(ISD::CTPOP, IntVT, Act);
+
+ // VE has only 64 bits instructions which work as i64 AND/OR/XOR operations.
+ // Use isel patterns for i64, promote for i32.
+ setOperationAction(ISD::AND, IntVT, Act);
+ setOperationAction(ISD::OR, IntVT, Act);
+ setOperationAction(ISD::XOR, IntVT, Act);
}
/// } Int Ops
diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td
index 2555b16138b2..b07938cb99a3 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -917,16 +917,11 @@ let cx = 0, DecoderMethod = "DecodeLoadI64" in
defm LEA : RMm<"lea", 0x06, I64>;
let cx = 1, DecoderMethod = "DecodeLoadI64" in
defm LEASL : RMm<"lea.sl", 0x06, I64>;
-let cx = 0, DecoderMethod = "DecodeLoadI32", isCodeGenOnly = 1 in
-defm LEA32 : RMm<"lea", 0x06, I32>;
def : Pat<(iPTR ADDRrri:$addr), (LEArri MEMrri:$addr)>;
def : Pat<(iPTR ADDRrii:$addr), (LEArii MEMrii:$addr)>;
def : Pat<(add I64:$base, simm32:$disp), (LEArii $base, 0, (LO32 $disp))>;
def : Pat<(add I64:$base, lozero:$disp), (LEASLrii $base, 0, (HI32 $disp))>;
-def : Pat<(add I32:$base, simm32:$disp),
- (LEA32rii (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $base, sub_i32), 0,
- (LO32 $disp))>;
def lea_add : PatFrags<(ops node:$base, node:$idx, node:$disp),
[(add (add node:$base, node:$idx), node:$disp),
@@ -1181,15 +1176,12 @@ let cw = 1 in defm MINSL : RRm<"mins.l", 0x68, I64, i64>;
// Section 8.5.1 - AND (AND)
defm AND : RRm<"and", 0x44, I64, i64, and>;
-let isCodeGenOnly = 1 in defm AND32 : RRm<"and", 0x44, I32, i32, and>;
// Section 8.5.2 - OR (OR)
defm OR : RRm<"or", 0x45, I64, i64, or>;
-let isCodeGenOnly = 1 in defm OR32 : RRm<"or", 0x45, I32, i32, or>;
// Section 8.5.3 - XOR (Exclusive OR)
defm XOR : RRm<"xor", 0x46, I64, i64, xor>;
-let isCodeGenOnly = 1 in defm XOR32 : RRm<"xor", 0x46, I32, i32, xor>;
// Section 8.5.4 - EQV (Equivalence)
defm EQV : RRm<"eqv", 0x47, I64, i64>;
@@ -1495,10 +1487,11 @@ defm SHMB : SHMm<"shm.b", 0x31, I64>;
//===----------------------------------------------------------------------===//
// Small immediates.
-def : Pat<(i32 simm7:$val), (OR32im (LO7 $val), 0)>;
+def : Pat<(i32 simm7:$val), (EXTRACT_SUBREG (ORim (LO7 $val), 0), sub_i32)>;
def : Pat<(i64 simm7:$val), (ORim (LO7 $val), 0)>;
// Medium immediates.
-def : Pat<(i32 simm32:$val), (LEA32zii 0, 0, (LO32 $val))>;
+def : Pat<(i32 simm32:$val),
+ (EXTRACT_SUBREG (LEAzii 0, 0, (LO32 $val)), sub_i32)>;
def : Pat<(i64 simm32:$val), (LEAzii 0, 0, (LO32 $val))>;
def : Pat<(i64 uimm32:$val), (ANDrm (LEAzii 0, 0, (LO32 $val)), !add(32, 64))>;
// Arbitrary immediates.
@@ -1539,8 +1532,8 @@ def : Pat<(sext_inreg I64:$src, i8),
(SRALri (SLLri $src, 56), 56)>;
def : Pat<(sext_inreg (i32 (trunc i64:$src)), i8),
(EXTRACT_SUBREG (SRALri (SLLri $src, 56), 56), sub_i32)>;
-def : Pat<(and (trunc i64:$src), 0xff),
- (AND32rm (EXTRACT_SUBREG $src, sub_i32), !add(56, 64))>;
+def : Pat<(i32 (and (trunc i64:$src), 0xff)),
+ (EXTRACT_SUBREG (ANDrm $src, !add(56, 64)), sub_i32)>;
// Cast to i16
def : Pat<(sext_inreg I32:$src, i16),
@@ -1549,8 +1542,8 @@ def : Pat<(sext_inreg I64:$src, i16),
(SRALri (SLLri $src, 48), 48)>;
def : Pat<(sext_inreg (i32 (trunc i64:$src)), i16),
(EXTRACT_SUBREG (SRALri (SLLri $src, 48), 48), sub_i32)>;
-def : Pat<(and (trunc i64:$src), 0xffff),
- (AND32rm (EXTRACT_SUBREG $src, sub_i32), !add(48, 64))>;
+def : Pat<(i32 (and (trunc i64:$src), 0xffff)),
+ (EXTRACT_SUBREG (ANDrm $src, !add(48, 64)), sub_i32)>;
// Cast to i32
def : Pat<(i32 (trunc i64:$src)),
@@ -1995,11 +1988,20 @@ def : Pat<(f32 (bitconvert i32:$op)),
(EXTRACT_SUBREG (SLLri (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
$op, sub_i32), 32), sub_f32)>;
-// Several special pattern matches to optimize code
+// Optimize code A generated by `(unsigned char)c << 5` to B.
+// A) sla.w.sx %s0, %s0, 5
+// lea %s1, 224 ; 0xE0
+// and %s0, %s0, %s1
+// B) sla.w.sx %s0, %s0, 5
+// and %s0, %s0, (56)0
-def : Pat<(i32 (and i32:$lhs, 0xff)),
- (AND32rm $lhs, !add(56, 64))>;
-def : Pat<(i32 (and i32:$lhs, 0xffff)),
- (AND32rm $lhs, !add(48, 64))>;
-def : Pat<(i32 (and i32:$lhs, 0xffffffff)),
- (AND32rm $lhs, !add(32, 64))>;
+def : Pat<(i32 (and i32:$val, 0xff)),
+ (EXTRACT_SUBREG
+ (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $val, sub_i32),
+ !add(56, 64)), sub_i32)>;
+def : Pat<(i32 (and i32:$val, 0xffff)),
+ (EXTRACT_SUBREG
+ (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $val, sub_i32),
+ !add(48, 64)), sub_i32)>;
+def : Pat<(i64 (and i64:$val, 0xffffffff)),
+ (ANDrm $val, !add(32, 64))>;
diff --git a/llvm/test/CodeGen/VE/cttz.ll b/llvm/test/CodeGen/VE/cttz.ll
index 9d4f94c742f5..f99bc3f76bb8 100644
--- a/llvm/test/CodeGen/VE/cttz.ll
+++ b/llvm/test/CodeGen/VE/cttz.ll
@@ -39,11 +39,9 @@ define i64 @func64(i64 %p) {
define signext i32 @func32s(i32 signext %p) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s0, %s1
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, %s1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true)
@@ -53,11 +51,9 @@ define signext i32 @func32s(i32 signext %p) {
define zeroext i32 @func32z(i32 zeroext %p) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s0, %s1
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, %s1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true)
@@ -67,11 +63,9 @@ define zeroext i32 @func32z(i32 zeroext %p) {
define signext i16 @func16s(i16 signext %p) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s0, %s1
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, %s1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true)
@@ -81,11 +75,9 @@ define signext i16 @func16s(i16 signext %p) {
define zeroext i16 @func16z(i16 zeroext %p) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s0, %s1
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, %s1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true)
@@ -95,11 +87,9 @@ define zeroext i16 @func16z(i16 zeroext %p) {
define signext i8 @func8s(i8 signext %p) {
; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s0, %s1
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, %s1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true)
@@ -109,11 +99,9 @@ define signext i8 @func8s(i8 signext %p) {
define zeroext i8 @func8z(i8 zeroext %p) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: adds.w.sx %s1, -1, %s0
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s0, %s1
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, %s1
+; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: pcnt %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true)
diff --git a/llvm/test/CodeGen/VE/nnd.ll b/llvm/test/CodeGen/VE/nnd.ll
index aedb85050f30..fd24032166b1 100644
--- a/llvm/test/CodeGen/VE/nnd.ll
+++ b/llvm/test/CodeGen/VE/nnd.ll
@@ -3,11 +3,7 @@
define signext i8 @func8s(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: func8s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s0, %s1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i8 %a, -1
%res = and i8 %not, %b
@@ -17,11 +13,7 @@ define signext i8 @func8s(i8 signext %a, i8 signext %b) {
define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: func8z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s1, %s0
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i8 %a, -1
%res = and i8 %b, %not
@@ -31,10 +23,8 @@ define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, 5, %s0
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: or %s1, 5, (0)1
+; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i8 %a, -1
%res = and i8 %not, 5
@@ -44,10 +34,8 @@ define signext i8 @funci8s(i8 signext %a) {
define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: xor %s0, -1, %s0
; CHECK-NEXT: lea %s1, 251
-; CHECK-NEXT: and %s0, %s0, %s1
+; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i8 %a, -1
%res = and i8 -5, %not
@@ -57,11 +45,7 @@ define zeroext i8 @funci8z(i8 zeroext %a) {
define signext i16 @func16s(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: func16s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s0, %s1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i16 %a, -1
%res = and i16 %not, %b
@@ -71,11 +55,7 @@ define signext i16 @func16s(i16 signext %a, i16 signext %b) {
define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: func16z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s1, %s0
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i16 %a, -1
%res = and i16 %b, %not
@@ -85,9 +65,7 @@ define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i16 %a, -1
%res = and i16 %not, 65535
@@ -97,10 +75,7 @@ define signext i16 @funci16s(i16 signext %a) {
define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s0, (52)0
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, (52)0
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i16 %a, -1
%res = and i16 4095, %not
@@ -110,11 +85,7 @@ define zeroext i16 @funci16z(i16 zeroext %a) {
define signext i32 @func32s(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: func32s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s0, %s1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i32 %a, -1
%res = and i32 %not, %b
@@ -124,11 +95,7 @@ define signext i32 @func32s(i32 signext %a, i32 signext %b) {
define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: func32z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s0, %s1
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i32 %a, -1
%res = and i32 %not, %b
@@ -138,10 +105,7 @@ define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s0, (36)0
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i32 %a, -1
%res = and i32 %not, 268435455
@@ -151,10 +115,7 @@ define signext i32 @funci32s(i32 signext %a) {
define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: and %s0, %s0, (36)0
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
+; CHECK-NEXT: nnd %s0, %s0, (36)0
; CHECK-NEXT: or %s11, 0, %s9
%not = xor i32 %a, -1
%res = and i32 %not, 268435455
diff --git a/llvm/test/CodeGen/VE/or.ll b/llvm/test/CodeGen/VE/or.ll
index 8ddb1b5fbf80..1f8c35012f81 100644
--- a/llvm/test/CodeGen/VE/or.ll
+++ b/llvm/test/CodeGen/VE/or.ll
@@ -21,9 +21,7 @@ define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s0, 5, %s0
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = or i8 %a, 5
ret i8 %res
@@ -32,10 +30,8 @@ define signext i8 @funci8s(i8 signext %a) {
define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: lea %s1, 251
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = or i8 -5, %a
ret i8 %res
@@ -71,9 +67,7 @@ define signext i16 @funci16s(i16 signext %a) {
define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s0, %s0, (52)0
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = or i16 4095, %a
ret i16 %res
@@ -100,9 +94,7 @@ define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s0, %s0, (36)0
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = or i32 %a, 268435455
ret i32 %res
@@ -111,9 +103,7 @@ define signext i32 @funci32s(i32 signext %a) {
define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s0, %s0, (36)0
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = or i32 %a, 268435455
ret i32 %res
diff --git a/llvm/test/CodeGen/VE/selectccf32c.ll b/llvm/test/CodeGen/VE/selectccf32c.ll
index aed2cad78a5b..c30eba96bf5f 100644
--- a/llvm/test/CodeGen/VE/selectccf32c.ll
+++ b/llvm/test/CodeGen/VE/selectccf32c.ll
@@ -64,10 +64,10 @@ define float @selectccsgti128(i128, i128, float, float) {
; CHECK-NEXT: or %s3, 0, %s6
; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2
-; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s0
-; CHECK-NEXT: cmov.l.eq %s3, %s6, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s3, %s0
+; CHECK-NEXT: or %s2, 0, %s6
+; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
+; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
+; CHECK-NEXT: cmps.w.sx %s0, %s3, %s6
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9
diff --git a/llvm/test/CodeGen/VE/selectccf64c.ll b/llvm/test/CodeGen/VE/selectccf64c.ll
index cef221ef87a7..4f113edbed5f 100644
--- a/llvm/test/CodeGen/VE/selectccf64c.ll
+++ b/llvm/test/CodeGen/VE/selectccf64c.ll
@@ -64,10 +64,10 @@ define double @selectccsgti128(i128, i128, double, double) {
; CHECK-NEXT: or %s3, 0, %s6
; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2
-; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s0
-; CHECK-NEXT: cmov.l.eq %s3, %s6, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s3, %s0
+; CHECK-NEXT: or %s2, 0, %s6
+; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
+; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
+; CHECK-NEXT: cmps.w.sx %s0, %s3, %s6
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9
diff --git a/llvm/test/CodeGen/VE/selectcci32c.ll b/llvm/test/CodeGen/VE/selectcci32c.ll
index 67878352dec6..982259c2bc89 100644
--- a/llvm/test/CodeGen/VE/selectcci32c.ll
+++ b/llvm/test/CodeGen/VE/selectcci32c.ll
@@ -64,10 +64,10 @@ define i32 @selectccsgti128(i128, i128, i32, i32) {
; CHECK-NEXT: or %s3, 0, %s6
; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2
-; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s0
-; CHECK-NEXT: cmov.l.eq %s3, %s6, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s3, %s0
+; CHECK-NEXT: or %s2, 0, %s6
+; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
+; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
+; CHECK-NEXT: cmps.w.sx %s0, %s3, %s6
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9
diff --git a/llvm/test/CodeGen/VE/selectcci64c.ll b/llvm/test/CodeGen/VE/selectcci64c.ll
index 75c54f6ad97c..7a91bfe10f88 100644
--- a/llvm/test/CodeGen/VE/selectcci64c.ll
+++ b/llvm/test/CodeGen/VE/selectcci64c.ll
@@ -64,10 +64,10 @@ define i64 @selectccsgti128(i128, i128, i64, i64) {
; CHECK-NEXT: or %s3, 0, %s6
; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2
-; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s0
-; CHECK-NEXT: cmov.l.eq %s3, %s6, %s1
-; CHECK-NEXT: or %s0, 0, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s3, %s0
+; CHECK-NEXT: or %s2, 0, %s6
+; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
+; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
+; CHECK-NEXT: cmps.w.sx %s0, %s3, %s6
; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: or %s11, 0, %s9
diff --git a/llvm/test/CodeGen/VE/xor.ll b/llvm/test/CodeGen/VE/xor.ll
index b3336bb72ff5..b84ab11593f6 100644
--- a/llvm/test/CodeGen/VE/xor.ll
+++ b/llvm/test/CodeGen/VE/xor.ll
@@ -21,9 +21,7 @@ define zeroext i8 @func8z(i8 zeroext %a, i8 zeroext %b) {
define signext i8 @funci8s(i8 signext %a) {
; CHECK-LABEL: funci8s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, 5, %s0
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = xor i8 %a, 5
ret i8 %res
@@ -32,10 +30,8 @@ define signext i8 @funci8s(i8 signext %a) {
define zeroext i8 @funci8z(i8 zeroext %a) {
; CHECK-LABEL: funci8z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: lea %s1, 251
; CHECK-NEXT: xor %s0, %s0, %s1
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = xor i8 -5, %a
ret i8 %res
@@ -62,9 +58,7 @@ define zeroext i16 @func16z(i16 zeroext %a, i16 zeroext %b) {
define signext i16 @funci16s(i16 signext %a) {
; CHECK-LABEL: funci16s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, -1, %s0
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = xor i16 %a, 65535
ret i16 %res
@@ -73,9 +67,7 @@ define signext i16 @funci16s(i16 signext %a) {
define zeroext i16 @funci16z(i16 zeroext %a) {
; CHECK-LABEL: funci16z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, %s0, (52)0
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = xor i16 4095, %a
ret i16 %res
@@ -102,9 +94,7 @@ define zeroext i32 @func32z(i32 zeroext %a, i32 zeroext %b) {
define signext i32 @funci32s(i32 signext %a) {
; CHECK-LABEL: funci32s:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, %s0, (36)0
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = xor i32 %a, 268435455
ret i32 %res
@@ -113,9 +103,7 @@ define signext i32 @funci32s(i32 signext %a) {
define zeroext i32 @funci32z(i32 zeroext %a) {
; CHECK-LABEL: funci32z:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: xor %s0, %s0, (36)0
-; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%res = xor i32 %a, 268435455
ret i32 %res
@@ -124,8 +112,9 @@ define zeroext i32 @funci32z(i32 zeroext %a) {
define i32 @funci32_another(i32 %0) {
; CHECK-LABEL: funci32_another:
; CHECK: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT: xor %s0, %s0, (33)1
+; CHECK-NEXT: lea %s1, -2147483648
+; CHECK-NEXT: and %s1, %s1, (32)0
+; CHECK-NEXT: xor %s0, %s0, %s1
; CHECK-NEXT: or %s11, 0, %s9
%2 = xor i32 %0, -2147483648
ret i32 %2
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