[PATCH] D85726: [VE] Change to promote i32 AND/OR/XOR operations

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 added a comment.

Thank you for reviewing.



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Comment at: llvm/test/CodeGen/VE/xor.ll:115-118
+; CHECK-NEXT:    lea %s1, -2147483648
+; CHECK-NEXT:    and %s1, %s1, (32)0
+; CHECK-NEXT:    xor %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
----------------
simoll wrote:
> Are you planning to address this regression? (non-blocker given the significant improvements everywhere else)
No since I think these additional instructions are required to handle 32 bits correctly.  VE instructions sign-extend all immediate values in instructions.  So, (33)1 is 0xFFFFFFFF80000000.  However, llvm expects 0x0000000080000000 here, I think.


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  https://reviews.llvm.org/D85726/new/

https://reviews.llvm.org/D85726