[PATCH] D81766: [VectorCombine] try to create vector loads from scalar loads

[Steven Johnson via Phabricator via llvm-commits]

srj added a comment.

> Can we just add another condition (!VectorSize) to this bailout?
> if (!ScalarSize || VectorSize % ScalarSize != 0)

Changing it to `if (!ScalarSize || !VectorSize || VectorSize % ScalarSize != 0)` does indeed seem to make our failure go away, so that would be fine as a quick fix.

(I'm still surprised that `getMinVectorRegisterBitWidth()` should ever return 0, but I can take that up with Qualcomm folks separately; it is entirely possible I don't understand the full semantics of that method.)


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  https://reviews.llvm.org/D81766/new/

https://reviews.llvm.org/D81766