[PATCH] D85366: [RISCV] Disparage CSR instructions

[Evandro Menezes via Phabricator via llvm-commits]

evandro added a comment.

`hasSideEffects` may imply `isNotDuplicable`, especially when rematerializing, but the latter prevents duplication more extensively in the middle end (e.g., tail end duplication).

Architecting reading the cycle counter to be like a GPR is not a given, since it's usually a side band register away from the register file.  Therefore, such instructions follow unusual paths in the architecture, when methinks that `hasNoSchedulingInfo` makes sense.

Moreover, though the CSR instructions may be used as RO, they are defined as RMW instructions.  But this probably just backs up `hasSideEffects`.

And not all code piped through the LLVM IR comes from `CodeGen`.  Thus, it's important to describe the instructions as faithfully as possible to the ISA, regardless of how they are used in the compiler.


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  rL LLVM

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  https://reviews.llvm.org/D85366/new/

https://reviews.llvm.org/D85366