[llvm] e9ac149 - [AIX][XCOFF] change the operand of branch instruction from symbol name to qualified symbol name for function declarations
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 11 12:26:44 PDT 2020
Author: diggerlin
Date: 2020-08-11T15:26:19-04:00
New Revision: e9ac1495e2082ebacfe14df2ffd124a58860449d
URL: https://github.com/llvm/llvm-project/commit/e9ac1495e2082ebacfe14df2ffd124a58860449d
DIFF: https://github.com/llvm/llvm-project/commit/e9ac1495e2082ebacfe14df2ffd124a58860449d.diff
LOG: [AIX][XCOFF] change the operand of branch instruction from symbol name to qualified symbol name for function declarations
SUMMARY:
1. in the patch , remove setting storageclass in function .getXCOFFSection and construct function of class MCSectionXCOFF
there are
XCOFF::StorageMappingClass MappingClass;
XCOFF::SymbolType Type;
XCOFF::StorageClass StorageClass;
in the MCSectionXCOFF class,
these attribute only used in the XCOFFObjectWriter, (asm path do not need the StorageClass)
we need get the value of StorageClass, Type,MappingClass before we invoke the getXCOFFSection every time.
actually , we can get the StorageClass of the MCSectionXCOFF from it's delegated symbol.
2. we also change the oprand of branch instruction from symbol name to qualify symbol name.
for example change
bl .foo
extern .foo
to
bl .foo[PR]
extern .foo[PR]
3. and if there is reference indirect call a function bar.
we also add
extern .bar[PR]
Reviewers: Jason liu, Xiangling Liao
Differential Revision: https://reviews.llvm.org/D84765
Added:
Modified:
llvm/include/llvm/MC/MCContext.h
llvm/include/llvm/MC/MCSectionXCOFF.h
llvm/include/llvm/MC/MCSymbolXCOFF.h
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
llvm/lib/MC/MCContext.cpp
llvm/lib/MC/MCObjectFileInfo.cpp
llvm/lib/MC/MCSymbolXCOFF.cpp
llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
llvm/test/CodeGen/PowerPC/aix-external-sym-sdnode-lowering.ll
llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
llvm/test/CodeGen/PowerPC/aix-sret-param.ll
llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll
llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
llvm/test/CodeGen/PowerPC/aix-xcoff-visibility.ll
llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
llvm/test/CodeGen/PowerPC/test_call_aix.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/MC/MCContext.h b/llvm/include/llvm/MC/MCContext.h
index d041b06c5568..eeb1fb241007 100644
--- a/llvm/include/llvm/MC/MCContext.h
+++ b/llvm/include/llvm/MC/MCContext.h
@@ -565,7 +565,6 @@ namespace llvm {
MCSectionXCOFF *getXCOFFSection(StringRef Section,
XCOFF::StorageMappingClass MappingClass,
XCOFF::SymbolType CSectType,
- XCOFF::StorageClass StorageClass,
SectionKind K,
const char *BeginSymName = nullptr);
diff --git a/llvm/include/llvm/MC/MCSectionXCOFF.h b/llvm/include/llvm/MC/MCSectionXCOFF.h
index eed6b9c2609c..4ad9aa76a210 100644
--- a/llvm/include/llvm/MC/MCSectionXCOFF.h
+++ b/llvm/include/llvm/MC/MCSectionXCOFF.h
@@ -34,22 +34,20 @@ class MCSectionXCOFF final : public MCSection {
XCOFF::StorageMappingClass MappingClass;
XCOFF::SymbolType Type;
- XCOFF::StorageClass StorageClass;
MCSymbolXCOFF *const QualName;
StringRef SymbolTableName;
static constexpr unsigned DefaultAlignVal = 4;
MCSectionXCOFF(StringRef Name, XCOFF::StorageMappingClass SMC,
- XCOFF::SymbolType ST, XCOFF::StorageClass SC, SectionKind K,
- MCSymbolXCOFF *QualName, MCSymbol *Begin,
- StringRef SymbolTableName)
+ XCOFF::SymbolType ST, SectionKind K, MCSymbolXCOFF *QualName,
+ MCSymbol *Begin, StringRef SymbolTableName)
: MCSection(SV_XCOFF, Name, K, Begin), MappingClass(SMC), Type(ST),
- StorageClass(SC), QualName(QualName), SymbolTableName(SymbolTableName) {
+ QualName(QualName), SymbolTableName(SymbolTableName) {
assert((ST == XCOFF::XTY_SD || ST == XCOFF::XTY_CM || ST == XCOFF::XTY_ER) &&
"Invalid or unhandled type for csect.");
assert(QualName != nullptr && "QualName is needed.");
- QualName->setStorageClass(SC);
QualName->setRepresentedCsect(this);
+ QualName->setStorageClass(XCOFF::C_HIDEXT);
// A csect is 4 byte aligned by default, except for undefined symbol csects.
if (Type != XCOFF::XTY_ER)
setAlignment(Align(DefaultAlignVal));
@@ -65,7 +63,9 @@ class MCSectionXCOFF final : public MCSection {
}
XCOFF::StorageMappingClass getMappingClass() const { return MappingClass; }
- XCOFF::StorageClass getStorageClass() const { return StorageClass; }
+ XCOFF::StorageClass getStorageClass() const {
+ return QualName->getStorageClass();
+ }
XCOFF::SymbolType getCSectType() const { return Type; }
MCSymbolXCOFF *getQualNameSymbol() const { return QualName; }
diff --git a/llvm/include/llvm/MC/MCSymbolXCOFF.h b/llvm/include/llvm/MC/MCSymbolXCOFF.h
index d0379ec08b7d..752e1e7bba0f 100644
--- a/llvm/include/llvm/MC/MCSymbolXCOFF.h
+++ b/llvm/include/llvm/MC/MCSymbolXCOFF.h
@@ -35,8 +35,6 @@ class MCSymbolXCOFF : public MCSymbol {
}
void setStorageClass(XCOFF::StorageClass SC) {
- assert((!StorageClass.hasValue() || StorageClass.getValue() == SC) &&
- "Redefining StorageClass of XCOFF MCSymbol.");
StorageClass = SC;
};
@@ -48,8 +46,6 @@ class MCSymbolXCOFF : public MCSymbol {
StringRef getUnqualifiedName() const { return getUnqualifiedName(getName()); }
- bool hasRepresentedCsectSet() const { return RepresentedCsect != nullptr; }
-
MCSectionXCOFF *getRepresentedCsect() const;
void setRepresentedCsect(MCSectionXCOFF *C);
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index a5d83ab11d2b..cdacedc72321 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -1528,9 +1528,8 @@ bool AsmPrinter::doFinalization(Module &M) {
// Variable `Name` is the function descriptor symbol (see above). Get the
// function entry point symbol.
MCSymbol *FnEntryPointSym = TLOF.getFunctionEntryPointSymbol(&F, TM);
- if (cast<MCSymbolXCOFF>(FnEntryPointSym)->hasRepresentedCsectSet())
- // Emit linkage for the function entry point.
- emitLinkage(&F, FnEntryPointSym);
+ // Emit linkage for the function entry point.
+ emitLinkage(&F, FnEntryPointSym);
// Emit linkage for the function descriptor.
emitLinkage(&F, Name);
diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
index 8a0aacc4cee2..4c3e6cce7836 100644
--- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
@@ -2016,13 +2016,11 @@ MCSection *TargetLoweringObjectFileXCOFF::getSectionForExternalReference(
SmallString<128> Name;
getNameWithPrefix(Name, GO, TM);
- XCOFF::StorageClass SC =
- TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(GO);
// Externals go into a csect of type ER.
return getContext().getXCOFFSection(
Name, isa<Function>(GO) ? XCOFF::XMC_DS : XCOFF::XMC_UA, XCOFF::XTY_ER,
- SC, SectionKind::getMetadata());
+ SectionKind::getMetadata());
}
MCSection *TargetLoweringObjectFileXCOFF::SelectSectionForGlobal(
@@ -2035,11 +2033,9 @@ MCSection *TargetLoweringObjectFileXCOFF::SelectSectionForGlobal(
if (Kind.isBSSLocal() || Kind.isCommon()) {
SmallString<128> Name;
getNameWithPrefix(Name, GO, TM);
- XCOFF::StorageClass SC =
- TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(GO);
return getContext().getXCOFFSection(
Name, Kind.isBSSLocal() ? XCOFF::XMC_BS : XCOFF::XMC_RW, XCOFF::XTY_CM,
- SC, Kind, /* BeginSymbolName */ nullptr);
+ Kind, /* BeginSymbolName */ nullptr);
}
if (Kind.isMergeableCString()) {
@@ -2051,10 +2047,8 @@ MCSection *TargetLoweringObjectFileXCOFF::SelectSectionForGlobal(
SmallString<128> Name;
Name = SizeSpec + utostr(Alignment.value());
- return getContext().getXCOFFSection(
- Name, XCOFF::XMC_RO, XCOFF::XTY_SD,
- TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(GO),
- Kind, /* BeginSymbolName */ nullptr);
+ return getContext().getXCOFFSection(Name, XCOFF::XMC_RO, XCOFF::XTY_SD,
+ Kind, /*BeginSymbolName*/ nullptr);
}
if (Kind.isText()) {
@@ -2095,7 +2089,6 @@ MCSection *TargetLoweringObjectFileXCOFF::getSectionForJumpTable(
SmallString<128> NameStr(".rodata.jmp..");
getNameWithPrefix(NameStr, &F, TM);
return getContext().getXCOFFSection(NameStr, XCOFF::XMC_RO, XCOFF::XTY_SD,
- XCOFF::C_HIDEXT,
SectionKind::getReadOnly());
}
@@ -2176,16 +2169,15 @@ MCSymbol *TargetLoweringObjectFileXCOFF::getFunctionEntryPointSymbol(
// When -function-sections is enabled, it's not necessary to emit
// function entry point label any more. We will use function entry
- // point csect instead. For function delcarations, it's okay to continue
- // using label semantic because undefined symbols gets treated as csect with
- // XTY_ER property anyway.
- if (TM.getFunctionSections() && !Func->isDeclaration() &&
+ // point csect instead. And for function delcarations, the undefined symbols
+ // gets treated as csect with XTY_ER property.
+ if ((TM.getFunctionSections() || Func->isDeclaration()) &&
isa<Function>(Func)) {
- XCOFF::StorageClass SC =
- TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(Func);
- return cast<MCSectionXCOFF>(getContext().getXCOFFSection(
- NameStr, XCOFF::XMC_PR, XCOFF::XTY_SD, SC,
- SectionKind::getText()))
+ return cast<MCSectionXCOFF>(
+ getContext().getXCOFFSection(
+ NameStr, XCOFF::XMC_PR,
+ Func->isDeclaration() ? XCOFF::XTY_ER : XCOFF::XTY_SD,
+ SectionKind::getText()))
->getQualNameSymbol();
}
@@ -2197,7 +2189,6 @@ MCSection *TargetLoweringObjectFileXCOFF::getSectionForFunctionDescriptor(
SmallString<128> NameStr;
getNameWithPrefix(NameStr, F, TM);
return getContext().getXCOFFSection(NameStr, XCOFF::XMC_DS, XCOFF::XTY_SD,
- getStorageClassForGlobal(F),
SectionKind::getData());
}
@@ -2208,5 +2199,5 @@ MCSection *TargetLoweringObjectFileXCOFF::getSectionForTOCEntry(
return getContext().getXCOFFSection(
cast<MCSymbolXCOFF>(Sym)->getSymbolTableName(),
TM.getCodeModel() == CodeModel::Large ? XCOFF::XMC_TE : XCOFF::XMC_TC,
- XCOFF::XTY_SD, XCOFF::C_HIDEXT, SectionKind::getData());
+ XCOFF::XTY_SD, SectionKind::getData());
}
diff --git a/llvm/lib/MC/MCContext.cpp b/llvm/lib/MC/MCContext.cpp
index 5b0078974318..650fddde82eb 100644
--- a/llvm/lib/MC/MCContext.cpp
+++ b/llvm/lib/MC/MCContext.cpp
@@ -662,7 +662,6 @@ MCSectionWasm *MCContext::getWasmSection(const Twine &Section, SectionKind Kind,
MCSectionXCOFF *MCContext::getXCOFFSection(StringRef Section,
XCOFF::StorageMappingClass SMC,
XCOFF::SymbolType Type,
- XCOFF::StorageClass SC,
SectionKind Kind,
const char *BeginSymName) {
// Do the lookup. If we have a hit, return it.
@@ -684,8 +683,8 @@ MCSectionXCOFF *MCContext::getXCOFFSection(StringRef Section,
// QualName->getUnqualifiedName() and CachedName are the same except when
// CachedName contains invalid character(s) such as '$' for an XCOFF symbol.
MCSectionXCOFF *Result = new (XCOFFAllocator.Allocate())
- MCSectionXCOFF(QualName->getUnqualifiedName(), SMC, Type, SC, Kind,
- QualName, Begin, CachedName);
+ MCSectionXCOFF(QualName->getUnqualifiedName(), SMC, Type, Kind, QualName,
+ Begin, CachedName);
Entry.second = Result;
auto *F = new MCDataFragment();
diff --git a/llvm/lib/MC/MCObjectFileInfo.cpp b/llvm/lib/MC/MCObjectFileInfo.cpp
index a400cc9de75c..927294fcd7e1 100644
--- a/llvm/lib/MC/MCObjectFileInfo.cpp
+++ b/llvm/lib/MC/MCObjectFileInfo.cpp
@@ -822,21 +822,21 @@ void MCObjectFileInfo::initXCOFFMCObjectFileInfo(const Triple &T) {
// get placed into this csect. The choice of csect name is not a property of
// the ABI or object file format. For example, the XL compiler uses an unnamed
// csect for program code.
- TextSection = Ctx->getXCOFFSection(
- ".text", XCOFF::StorageMappingClass::XMC_PR, XCOFF::XTY_SD,
- XCOFF::C_HIDEXT, SectionKind::getText());
+ TextSection =
+ Ctx->getXCOFFSection(".text", XCOFF::StorageMappingClass::XMC_PR,
+ XCOFF::XTY_SD, SectionKind::getText());
- DataSection = Ctx->getXCOFFSection(
- ".data", XCOFF::StorageMappingClass::XMC_RW, XCOFF::XTY_SD,
- XCOFF::C_HIDEXT, SectionKind::getData());
+ DataSection =
+ Ctx->getXCOFFSection(".data", XCOFF::StorageMappingClass::XMC_RW,
+ XCOFF::XTY_SD, SectionKind::getData());
- ReadOnlySection = Ctx->getXCOFFSection(
- ".rodata", XCOFF::StorageMappingClass::XMC_RO, XCOFF::XTY_SD,
- XCOFF::C_HIDEXT, SectionKind::getReadOnly());
+ ReadOnlySection =
+ Ctx->getXCOFFSection(".rodata", XCOFF::StorageMappingClass::XMC_RO,
+ XCOFF::XTY_SD, SectionKind::getReadOnly());
- TOCBaseSection = Ctx->getXCOFFSection(
- "TOC", XCOFF::StorageMappingClass::XMC_TC0, XCOFF::XTY_SD,
- XCOFF::C_HIDEXT, SectionKind::getData());
+ TOCBaseSection =
+ Ctx->getXCOFFSection("TOC", XCOFF::StorageMappingClass::XMC_TC0,
+ XCOFF::XTY_SD, SectionKind::getData());
// The TOC-base always has 0 size, but 4 byte alignment.
TOCBaseSection->setAlignment(Align(4));
diff --git a/llvm/lib/MC/MCSymbolXCOFF.cpp b/llvm/lib/MC/MCSymbolXCOFF.cpp
index 536153e5518b..b9dd2908b40b 100644
--- a/llvm/lib/MC/MCSymbolXCOFF.cpp
+++ b/llvm/lib/MC/MCSymbolXCOFF.cpp
@@ -13,8 +13,7 @@ using namespace llvm;
MCSectionXCOFF *MCSymbolXCOFF::getRepresentedCsect() const {
assert(RepresentedCsect &&
"Trying to get csect representation of this symbol but none was set.");
- assert((!getName().equals(getUnqualifiedName()) ||
- RepresentedCsect->getCSectType() == XCOFF::XTY_ER) &&
+ assert(!getName().equals(getUnqualifiedName()) &&
"Symbol does not represent a csect; MCSectionXCOFF that represents "
"the symbol should not be (but is) set.");
assert(getSymbolTableName().equals(RepresentedCsect->getSymbolTableName()) &&
@@ -26,10 +25,9 @@ MCSectionXCOFF *MCSymbolXCOFF::getRepresentedCsect() const {
void MCSymbolXCOFF::setRepresentedCsect(MCSectionXCOFF *C) {
assert(C && "Assigned csect should not be null.");
assert((!RepresentedCsect || RepresentedCsect == C) &&
- "Trying to set a csect that doesn't match the one that"
- "this symbol is already mapped to.");
- assert((!getName().equals(getUnqualifiedName()) ||
- C->getCSectType() == XCOFF::XTY_ER) &&
+ "Trying to set a csect that doesn't match the one that this symbol is "
+ "already mapped to.");
+ assert(!getName().equals(getUnqualifiedName()) &&
"Symbol does not represent a csect; can only set a MCSectionXCOFF "
"representation for a csect.");
assert(getSymbolTableName().equals(C->getSymbolTableName()) &&
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 5358a8a36b33..8540e89284fe 100644
--- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1709,10 +1709,7 @@ void PPCAIXAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
"Unhandled intrinsic global variable.");
ValidateGV(GV);
- // Create the symbol, set its storage class.
MCSymbolXCOFF *GVSym = cast<MCSymbolXCOFF>(getSymbol(GV));
- GVSym->setStorageClass(
- TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(GV));
if (GV->isDeclarationForLinker()) {
emitLinkage(GV, GVSym);
@@ -1736,6 +1733,8 @@ void PPCAIXAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
if (GVKind.isCommon() || GVKind.isBSSLocal()) {
Align Alignment = GV->getAlign().getValueOr(DL.getPreferredAlign(GV));
uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());
+ GVSym->setStorageClass(
+ TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(GV));
if (GVKind.isBSSLocal())
OutStreamer->emitXCOFFLocalCommonSymbol(
@@ -1907,15 +1906,6 @@ void PPCAIXAsmPrinter::emitInstruction(const MachineInstr *MI) {
if (MO.isSymbol()) {
MCSymbolXCOFF *S =
cast<MCSymbolXCOFF>(OutContext.getOrCreateSymbol(MO.getSymbolName()));
- if (!S->hasRepresentedCsectSet()) {
- // On AIX, an undefined symbol needs to be associated with a
- // MCSectionXCOFF to get the correct storage mapping class.
- // In this case, XCOFF::XMC_PR.
- MCSectionXCOFF *Sec = OutContext.getXCOFFSection(
- S->getName(), XCOFF::XMC_PR, XCOFF::XTY_ER, XCOFF::C_EXT,
- SectionKind::getMetadata());
- S->setRepresentedCsect(Sec);
- }
ExtSymSDNodeSymbols.insert(S);
}
} break;
@@ -1938,10 +1928,9 @@ void PPCAIXAsmPrinter::emitInstruction(const MachineInstr *MI) {
}
bool PPCAIXAsmPrinter::doFinalization(Module &M) {
- bool Ret = PPCAsmPrinter::doFinalization(M);
for (MCSymbol *Sym : ExtSymSDNodeSymbols)
OutStreamer->emitSymbolAttribute(Sym, MCSA_Extern);
- return Ret;
+ return PPCAsmPrinter::doFinalization(M);
}
void PPCAIXAsmPrinter::emitXXStructorList(const DataLayout &DL,
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 8495ad37a3d6..296d0922d16d 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -5159,19 +5159,6 @@ static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG,
MCSymbolXCOFF *S =
cast<MCSymbolXCOFF>(TLOF->getFunctionEntryPointSymbol(GV, TM));
- if (GV->isDeclaration() && !S->hasRepresentedCsectSet()) {
- // On AIX, an undefined symbol needs to be associated with a
- // MCSectionXCOFF to get the correct storage mapping class.
- // In this case, XCOFF::XMC_PR.
- const XCOFF::StorageClass SC =
- TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(GV);
- auto &Context = DAG.getMachineFunction().getMMI().getContext();
- MCSectionXCOFF *Sec = Context.getXCOFFSection(
- S->getSymbolTableName(), XCOFF::XMC_PR, XCOFF::XTY_ER, SC,
- SectionKind::getMetadata());
- S->setRepresentedCsect(Sec);
- }
-
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
return DAG.getMCSymbol(S, PtrVT);
};
@@ -5199,14 +5186,17 @@ static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG,
// On AIX, direct function calls reference the symbol for the function's
// entry point, which is named by prepending a "." before the function's
- // C-linkage name.
- const auto getFunctionEntryPointSymbol = [&](StringRef SymName) {
+ // C-linkage name. A Qualname is returned here because an external
+ // function entry point is a csect with XTY_ER property.
+ const auto getExternalFunctionEntryPointSymbol = [&](StringRef SymName) {
auto &Context = DAG.getMachineFunction().getMMI().getContext();
- return cast<MCSymbolXCOFF>(
- Context.getOrCreateSymbol(Twine(".") + Twine(SymName)));
+ MCSectionXCOFF *Sec = Context.getXCOFFSection(
+ (Twine(".") + Twine(SymName)).str(), XCOFF::XMC_PR, XCOFF::XTY_ER,
+ SectionKind::getMetadata());
+ return Sec->getQualNameSymbol();
};
- SymName = getFunctionEntryPointSymbol(SymName)->getName().data();
+ SymName = getExternalFunctionEntryPointSymbol(SymName)->getName().data();
}
return DAG.getTargetExternalSymbol(SymName, Callee.getValueType(),
UsePlt ? PPCII::MO_PLT : 0);
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
index 52070aa9063d..3105f5ba5829 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
@@ -381,7 +381,7 @@ declare i32 @call_test_bool(i1 zeroext)
; 32BIT-NEXT: bb.0.entry:
; 32BIT: liveins: $r3
; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: BL_NOP <mcsymbol .call_test_bool>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1, implicit-def $r3
+; 32BIT: BL_NOP <mcsymbol .call_test_bool[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1, implicit-def $r3
; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 64BIT: liveins:
@@ -390,7 +390,7 @@ declare i32 @call_test_bool(i1 zeroext)
; 64BIT-NEXT: bb.0.entry:
; 64BIT-NEXT: liveins: $x3
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: BL8_NOP <mcsymbol .call_test_bool>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def $x3
+; 64BIT: BL8_NOP <mcsymbol .call_test_bool[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def $x3
; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
@f1 = global float 0.000000e+00, align 4
@@ -712,7 +712,7 @@ declare void @test_vararg(i32, ...)
; 32BIT-NEXT: renamable $r7 = LWZ 4, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]] + 4)
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: $r3 = LI 42
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit $f2, implicit $r6, implicit $r7, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit $f2, implicit $r6, implicit $r7, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_vararg:
@@ -729,7 +729,7 @@ declare void @test_vararg(i32, ...)
; ASM32PWR4-DAG: lwz 5, 68(1)
; ASM32PWR4-DAG: lwz 6, 72(1)
; ASM32PWR4-DAG: lwz 7, 76(1)
-; ASM32PWR4-NEXT: bl .test_vararg
+; ASM32PWR4-NEXT: bl .test_vararg[PR]
; ASM32PWR4-NEXT: nop
; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
@@ -742,7 +742,7 @@ declare void @test_vararg(i32, ...)
; 64BIT-NEXT: renamable $x5 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]])
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 42
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64PWR4: stdu 1, -128(1)
@@ -755,7 +755,7 @@ declare void @test_vararg(i32, ...)
; ASM64PWR4-NEXT: stfd 2, 120(1)
; ASM64PWR4-NEXT: ld 4, 112(1)
; ASM64PWR4-NEXT: ld 5, 120(1)
-; ASM64PWR4-NEXT: bl .test_vararg
+; ASM64PWR4-NEXT: bl .test_vararg[PR]
; ASM64PWR4-NEXT: nop
define void @call_test_vararg2() {
@@ -782,7 +782,7 @@ entry:
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: $r3 = LI 42
; 32BIT-NEXT: $r6 = LI 42
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit $f2, implicit $r7, implicit $r8, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit $f2, implicit $r7, implicit $r8, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; ASM32PWR4: stwu 1, -80(1)
@@ -798,7 +798,7 @@ entry:
; ASM32PWR4-DAG: lwz 5, 68(1)
; ASM32PWR4-DAG: lwz 7, 72(1)
; ASM32PWR4-DAG: lwz 8, 76(1)
-; ASM32PWR4-NEXT: bl .test_vararg
+; ASM32PWR4-NEXT: bl .test_vararg[PR]
; ASM32PWR4-NEXT: nop
; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
@@ -812,7 +812,7 @@ entry:
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 42
; 64BIT-NEXT: $x5 = LI8 42
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64PWR4: stdu 1, -128(1)
@@ -826,7 +826,7 @@ entry:
; ASM64PWR4-NEXT: stfd 2, 120(1)
; ASM64PWR4-NEXT: ld 4, 112(1)
; ASM64PWR4-NEXT: ld 6, 120(1)
-; ASM64PWR4-NEXT: bl .test_vararg
+; ASM64PWR4-NEXT: bl .test_vararg[PR]
; ASM64PWR4-NEXT: nop
define void @call_test_vararg3() {
@@ -854,7 +854,7 @@ entry:
; 32BIT-NEXT: $r3 = LI 42
; 32BIT-NEXT: $r6 = LI 0
; 32BIT-NEXT: $r7 = LI 42
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit killed $r7, implicit $f2, implicit $r8, implicit $r9, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit killed $r7, implicit $f2, implicit $r8, implicit $r9, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; ASM32PWR4: stwu 1, -80(1)
@@ -871,7 +871,7 @@ entry:
; ASM32PWR4-DAG: lwz 5, 68(1)
; ASM32PWR4-DAG: lwz 8, 72(1)
; ASM32PWR4-DAG: lwz 9, 76(1)
-; ASM32PWR4-NEXT: bl .test_vararg
+; ASM32PWR4-NEXT: bl .test_vararg[PR]
; ASM32PWR4-NEXT: nop
; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
@@ -885,7 +885,7 @@ entry:
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 42
; 64BIT-NEXT: $x5 = LI8 42
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64PWR4: stdu 1, -128(1)
@@ -899,7 +899,7 @@ entry:
; ASM64PWR4-NEXT: stfd 2, 120(1)
; ASM64PWR4-DAG: ld 4, 112(1)
; ASM64PWR4-DAG: ld 6, 120(1)
-; ASM64PWR4-NEXT: bl .test_vararg
+; ASM64PWR4-NEXT: bl .test_vararg[PR]
; ASM64PWR4-NEXT: nop
define void @call_test_vararg4() {
@@ -917,7 +917,7 @@ entry:
; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT]] :: (load 4 from %stack.[[SLOT]])
; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: $r3 = LI 42
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; ASM32PWR4: stwu 1, -64(1)
@@ -926,7 +926,7 @@ entry:
; ASM32PWR4-NEXT: li 3, 42
; ASM32PWR4-NEXT: stfs 1, 60(1)
; ASM32PWR4-NEXT: lwz 4, 60(1)
-; ASM32PWR4-NEXT: bl .test_vararg
+; ASM32PWR4-NEXT: bl .test_vararg[PR]
; ASM32PWR4-NEXT: nop
; 64BIT: renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
@@ -935,7 +935,7 @@ entry:
; 64BIT-NEXT: renamable $x4 = LWZ8 0, %stack.[[SLOT]] :: (load 4 from %stack.[[SLOT]])
; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: $x3 = LI8 42
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64PWR4: stdu 1, -128(1)
@@ -944,7 +944,7 @@ entry:
; ASM64PWR4-NEXT: li 3, 42
; ASM64PWR4-NEXT: stfs 1, 124(1)
; ASM64PWR4-NEXT: lwz 4, 124(1)
-; ASM64PWR4-NEXT: bl .test_vararg
+; ASM64PWR4-NEXT: bl .test_vararg[PR]
; ASM64PWR4-NEXT: nop
@c = common global i8 0, align 1
@@ -995,7 +995,7 @@ declare void @test_stackarg_int(i32, i32, i32, i32, i32, i32, i32, i32, i8 zeroe
; 32BIT-DAG: renamable $r[[REGLLI2:[0-9]+]] = LWZ 4, killed renamable $r[[REGLLIADDR]] :: (dereferenceable load 4 from @lli + 4, align 8)
; 32BIT-DAG: STW killed renamable $r[[REGLLI2]], 72, $r1 :: (store 4)
; 32BIT-DAG: STW renamable $r[[REGI]], 76, $r1 :: (store 4)
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_int>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_int[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 80, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_stackarg_int:
@@ -1025,7 +1025,7 @@ declare void @test_stackarg_int(i32, i32, i32, i32, i32, i32, i32, i32, i8 zeroe
; ASM32PWR4-DAG: lwz [[REGLLI2:[0-9]+]], 4([[REGLLIADDR]])
; ASM32PWR4-DAG: stw [[REGLLI2]], 72(1)
; ASM32PWR4-DAG: stw [[REGI]], 76(1)
-; ASM32PWR4-NEXT: bl .test_stackarg_int
+; ASM32PWR4-NEXT: bl .test_stackarg_int[PR]
; ASM32PWR4-NEXT: nop
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
@@ -1051,7 +1051,7 @@ declare void @test_stackarg_int(i32, i32, i32, i32, i32, i32, i32, i32, i8 zeroe
; 64BIT-DAG: renamable $x[[REGLLI:[0-9]+]] = LD 0, killed renamable $x[[REGLLIADDR]] :: (dereferenceable load 8 from @lli)
; 64BIT-DAG: STD killed renamable $x[[REGLLI]], 136, $x1 :: (store 8)
; 64BIT-DAG: STD renamable $x[[REGI]], 144, $x1 :: (store 8)
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_int>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_int[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
@@ -1077,7 +1077,7 @@ declare void @test_stackarg_int(i32, i32, i32, i32, i32, i32, i32, i32, i8 zeroe
; ASM64PWR4-DAG: ld [[REGLLI:[0-9]+]], 0([[REGLLIADDR]])
; ASM64PWR4-DAG: std [[REGLLI]], 136(1)
; ASM64PWR4-DAG: std [[REGI]], 144(1)
-; ASM64PWR4-NEXT: bl .test_stackarg_int
+; ASM64PWR4-NEXT: bl .test_stackarg_int[PR]
; ASM64PWR4-NEXT: nop
; Basic saving of floating point type arguments to the parameter save area.
@@ -1110,7 +1110,7 @@ declare void @test_stackarg_float(i32, i32, i32, i32, i32, i32, i32, i32, float,
; 32BIT-DAG: renamable $f2 = LFD 0, killed renamable $r[[REGD]] :: (dereferenceable load 8 from @d)
; 32BIT-DAG: STFS renamable $f1, 56, $r1 :: (store 4)
; 32BIT-DAG: STFD renamable $f2, 60, $r1 :: (store 8)
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $f1, implicit $f2, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $f1, implicit $f2, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 68, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_stackarg_float:
@@ -1131,7 +1131,7 @@ declare void @test_stackarg_float(i32, i32, i32, i32, i32, i32, i32, i32, float,
; ASM32PWR4-DAG: lfd 2, 0([[REGD:[0-9]+]])
; ASM32PWR4-DAG: stfs 1, 56(1)
; ASM32PWR4-DAG: stfd 2, 60(1)
-; ASM32PWR4-NEXT: bl .test_stackarg_float
+; ASM32PWR4-NEXT: bl .test_stackarg_float[PR]
; ASM32PWR4-NEXT: nop
; ASM32PWR4-NEXT: addi 1, 1, 80
@@ -1151,7 +1151,7 @@ declare void @test_stackarg_float(i32, i32, i32, i32, i32, i32, i32, i32, float,
; 64BIT-DAG: renamable $f2 = LFD 0, killed renamable $x[[REGD]] :: (dereferenceable load 8 from @d)
; 64BIT-DAG: STFS renamable $f1, 112, $x1 :: (store 4)
; 64BIT-DAG: STFD renamable $f2, 120, $x1 :: (store 8)
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
@@ -1170,7 +1170,7 @@ declare void @test_stackarg_float(i32, i32, i32, i32, i32, i32, i32, i32, float,
; ASM64PWR4-DAG: lfd 2, 0([[REGD]])
; ASM64PWR4-DAG: stfs 1, 112(1)
; ASM64PWR4-DAG: stfd 2, 120(1)
-; ASM64PWR4-NEXT: bl .test_stackarg_float
+; ASM64PWR4-NEXT: bl .test_stackarg_float[PR]
; ASM64PWR4-NEXT: nop
; ASM64PWR4-NEXT: addi 1, 1, 128
@@ -1198,7 +1198,7 @@ declare void @test_stackarg_float2(i32, i32, i32, i32, i32, i32, ...)
; 32BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0)
; 32BIT-DAG: renamable $r9 = LWZ 0, %stack.0 :: (load 4 from %stack.0, align 8)
; 32BIT-DAG: renamable $r10 = LWZ 4, %stack.0 :: (load 4 from %stack.0 + 4)
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float2>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit $f1, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float2[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit $f1, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_stackarg_float2:
@@ -1216,7 +1216,7 @@ declare void @test_stackarg_float2(i32, i32, i32, i32, i32, i32, ...)
; ASM32PWR4-DAG: stfd 1, 56(1)
; ASM32PWR4-DAG: lwz 9, 56(1)
; ASM32PWR4-DAG: lwz 10, 60(1)
-; ASM32PWR4-NEXT: bl .test_stackarg_float2
+; ASM32PWR4-NEXT: bl .test_stackarg_float2[PR]
; ASM32PWR4-NEXT: nop
; ASM32PWR4-NEXT: addi 1, 1, 64
@@ -1232,7 +1232,7 @@ declare void @test_stackarg_float2(i32, i32, i32, i32, i32, i32, ...)
; 64BIT-DAG: renamable $f1 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d)
; 64BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0)
; 64BIT-DAG: renamable $x9 = LD 0, %stack.0 :: (load 8 from %stack.0)
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float2>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float2[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
@@ -1247,7 +1247,7 @@ declare void @test_stackarg_float2(i32, i32, i32, i32, i32, i32, ...)
; ASM64PWR4-DAG: lfd 1, 0([[REG]])
; ASM64PWR4-DAG: stfd 1, 120(1)
; ASM64PWR4-DAG: ld 9, 120(1)
-; ASM64PWR4-NEXT: bl .test_stackarg_float2
+; ASM64PWR4-NEXT: bl .test_stackarg_float2[PR]
; ASM64PWR4-NEXT: nop
; ASM64PWR4-NEXT: addi 1, 1, 128
@@ -1282,7 +1282,7 @@ declare void @test_stackarg_float3(i32, i32, i32, i32, i32, i32, i32, ...)
; 32BIT-DAG: STFS renamable $f2, 60, $r1 :: (store 4)
; 32BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0)
; 32BIT-DAG: renamable $r10 = LWZ 0, %stack.0 :: (load 4 from %stack.0, align 8)
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float3>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $f1, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_stackarg_float3[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit $f1, implicit $r10, implicit $f2, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 64, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_stackarg_float3:
@@ -1304,7 +1304,7 @@ declare void @test_stackarg_float3(i32, i32, i32, i32, i32, i32, i32, ...)
; ASM32PWR4-DAG: stfs 2, 60(1)
; ASM32PWR4-DAG: stfd 1, 72(1)
; ASM32PWR4-DAG: lwz 10, 72(1)
-; ASM32PWR4-NEXT: bl .test_stackarg_float3
+; ASM32PWR4-NEXT: bl .test_stackarg_float3[PR]
; ASM32PWR4-NEXT: nop
; ASM32PWR4-NEXT: addi 1, 1, 80
@@ -1325,7 +1325,7 @@ declare void @test_stackarg_float3(i32, i32, i32, i32, i32, i32, i32, ...)
; 64BIT-DAG: STFS renamable $f2, 112, $x1 :: (store 4)
; 64BIT-DAG: STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0)
; 64BIT-DAG: renamable $x10 = LD 0, %stack.0 :: (load 8 from %stack.0)
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float3>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_stackarg_float3[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1
@@ -1345,7 +1345,7 @@ declare void @test_stackarg_float3(i32, i32, i32, i32, i32, i32, i32, ...)
; ASM64PWR4-DAG: stfs 2, 112(1)
; ASM64PWR4-DAG: stfd 1, 120(1)
; ASM64PWR4-DAG: ld 10, 120(1)
-; ASM64PWR4-NEXT: bl .test_stackarg_float3
+; ASM64PWR4-NEXT: bl .test_stackarg_float3[PR]
; ASM64PWR4-NEXT: nop
; ASM64PWR4-NEXT: addi 1, 1, 128
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
index 82927fdda86a..3f30bfd0e837 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll
@@ -88,7 +88,7 @@ entry:
; 32BIT-DAG: $r3 = COPY %0
; 32BIT-DAG: $r4 = COPY %1
; 32BIT-DAG: $r5 = COPY %2
-; 32BIT-NEXT: BL_NOP &.memcpy, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
+; 32BIT-NEXT: BL_NOP &".memcpy[PR]", csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT: ADJCALLSTACKDOWN 312, 0, implicit-def dead $r1, implicit $r1
; 32BIT-DAG: $r3 = COPY %{{[0-9]+}}
@@ -108,7 +108,7 @@ entry:
; ASM32BIT-DAG: addi 3, 1, 56
; ASM32BIT-DAG: lwz 4, L..C{{[0-9]+}}(2)
; ASM32BIT-DAG: li 5, 256
-; ASM32BIT-NEXT: bl .memcpy
+; ASM32BIT-NEXT: bl .memcpy[PR]
; ASM32BIT: bl .test_byval_mem2
; ASM32BIT: addi 1, 1, 320
@@ -120,7 +120,7 @@ entry:
; 64BIT-DAG: $x3 = COPY %0
; 64BIT-DAG: $x4 = COPY %1
; 64BIT-DAG: $x5 = COPY %2
-; 64BIT-NEXT: BL8_NOP &.memcpy, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1, implicit-def $x3
+; 64BIT-NEXT: BL8_NOP &".memcpy[PR]", csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1, implicit-def $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT: ADJCALLSTACKDOWN 368, 0, implicit-def dead $r1, implicit $r1
; 64BIT-DAG: $x3 = COPY %{{[0-9]+}}
@@ -138,7 +138,7 @@ entry:
; ASM64BIT-DAG: addi 3, 1, 112
; ASM64BIT-DAG: ld 4, L..C{{[0-9]+}}(2)
; ASM64BIT-DAG: li 5, 256
-; ASM64BIT-NEXT: bl .memcpy
+; ASM64BIT-NEXT: bl .memcpy[PR]
; ASM64BIT: bl .test_byval_mem2
; ASM64BIT: addi 1, 1, 368
@@ -187,7 +187,7 @@ entry:
; 32BIT-DAG: $r3 = COPY %2
; 32BIT-DAG: $r4 = COPY %1
; 32BIT-DAG: $r5 = COPY %3
-; 32BIT-NEXT: BL_NOP &.memcpy, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
+; 32BIT-NEXT: BL_NOP &".memcpy[PR]", csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT: ADJCALLSTACKDOWN 92, 0, implicit-def dead $r1, implicit $r1
; 32BIT-DAG: $r3 = COPY %{{[0-9]+}}
@@ -208,7 +208,7 @@ entry:
; ASM32BIT-DAG: addi 3, 1, 56
; ASM32BIT-DAG: addi 4, [[REG]], 24
; ASM32BIT-DAG: li 5, 33
-; ASM32BIT-NEXT: bl .memcpy
+; ASM32BIT-NEXT: bl .memcpy[PR]
; ASM32BIT-DAG: lwz 5, 0([[REG]])
; ASM32BIT-DAG: lwz 6, 4([[REG]])
; ASM32BIT-DAG: lwz 7, 8([[REG]])
@@ -305,7 +305,7 @@ entry:
; 32BIT-DAG: $r3 = COPY %3
; 32BIT-DAG: $r4 = COPY %4
; 32BIT-DAG: $r5 = COPY %5
-; 32BIT-NEXT: BL_NOP &.memcpy, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
+; 32BIT-NEXT: BL_NOP &".memcpy[PR]", csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 32BIT: ADJCALLSTACKDOWN 316, 0, implicit-def dead $r1, implicit $r1
; 32BIT-DAG: $r3 = COPY %{{[0-9]+}}
@@ -329,7 +329,7 @@ entry:
; ASM32BIT-DAG: addi 3, 1, 60
; ASM32BIT-DAG: lwz 4, L..C{{[0-9]+}}(2)
; ASM32BIT-DAG: li 5, 256
-; ASM32BIT-NEXT: bl .memcpy
+; ASM32BIT-NEXT: bl .memcpy[PR]
; ASM32BIT-DAG: lwz 4, 0([[REG1]])
; ASM32BIT-DAG: lwz 5, 4([[REG1]])
; ASM32BIT-DAG: lwz 6, 8([[REG1]])
@@ -349,7 +349,7 @@ entry:
; 64BIT-DAG: $x3 = COPY %2
; 64BIT-DAG: $x4 = COPY %1
; 64BIT-DAG: $x5 = COPY %3
-; 64BIT-NEXT: BL8_NOP &.memcpy, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1, implicit-def $x3
+; 64BIT-NEXT: BL8_NOP &".memcpy[PR]", csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1, implicit-def $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT: ADJCALLSTACKDOWN 344, 0, implicit-def dead $r1, implicit $r1
; 64BIT-DAG: $x3 = COPY %{{[0-9]+}}
@@ -368,7 +368,7 @@ entry:
; ASM64BIT-DAG: addi 3, 1, 112
; ASM64BIT-DAG: addi 4, [[REG1]], 24
; ASM64BIT-DAG: li 5, 232
-; ASM64BIT-NEXT: bl .memcpy
+; ASM64BIT-NEXT: bl .memcpy[PR]
; ASM64BIT-DAG: ld [[REG2:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM64BIT-DAG: ld 4, 0([[REG2]])
; ASM64BIT-DAG: ld 5, 8([[REG2]])
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll b/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
index bccb28ef2290..e495bb04dba8 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-byval.ll
@@ -479,7 +479,7 @@ declare zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1)
; 32BIT-DAG: renamable $r[[REG1:[0-9]+]] = LBZ 4, renamable $r[[REGADDR]] :: (load 1)
; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
; 32BIT-DAG: renamable $r4 = RLWINM killed renamable $r[[REG1]], 24, 0, 7
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_5Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_5Byte[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_byval_5Byte:
@@ -490,7 +490,7 @@ declare zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1)
; ASM32-DAG: lbz [[REG1:[0-9]+]], 4([[REGADDR]])
; ASM32-DAG: lwz 3, 0([[REGADDR]])
; ASM32-DAG: slwi 4, [[REG1]], 24
-; ASM32-NEXT: bl .test_byval_5Byte
+; ASM32-NEXT: bl .test_byval_5Byte[PR]
; ASM32-NEXT: nop
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
@@ -500,7 +500,7 @@ declare zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1)
; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1)
; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7
; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_5Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_5Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
@@ -510,7 +510,7 @@ declare zeroext i8 @test_byval_5Byte(%struct.S5* byval(%struct.S5) align 1)
; ASM64-DAG: lbz [[REG2:[0-9]+]], 4([[REGADDR]])
; ASM64-DAG: rlwinm 3, [[REG2]], 24, 0, 7
; ASM64-DAG: rldimi 3, [[REG1]], 32, 0
-; ASM64-NEXT: bl .test_byval_5Byte
+; ASM64-NEXT: bl .test_byval_5Byte[PR]
; ASM64-NEXT: nop
@@ -534,7 +534,7 @@ declare zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1)
; 32BIT-DAG: renamable $r[[REG1:[0-9]+]] = LHZ 4, renamable $r[[REGADDR]] :: (load 2)
; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
; 32BIT-DAG: renamable $r4 = RLWINM killed renamable $r[[REG1]], 16, 0, 15
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_6Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_6Byte[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_byval_6Byte:
@@ -545,7 +545,7 @@ declare zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1)
; ASM32-DAG: lhz [[REG1:[0-9]+]], 4([[REGADDR]])
; ASM32-DAG: lwz 3, 0([[REGADDR]])
; ASM32-DAG: slwi 4, [[REG1]], 16
-; ASM32-NEXT: bl .test_byval_6Byte
+; ASM32-NEXT: bl .test_byval_6Byte[PR]
; ASM32-NEXT: nop
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
@@ -555,7 +555,7 @@ declare zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1)
; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15
; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_6Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_6Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
@@ -565,7 +565,7 @@ declare zeroext i8 @test_byval_6Byte(%struct.S6* byval(%struct.S6) align 1)
; ASM64-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
; ASM64-DAG: rlwinm 3, [[REG2]], 16, 0, 15
; ASM64-DAG: rldimi 3, [[REG1]], 32, 0
-; ASM64-NEXT: bl .test_byval_6Byte
+; ASM64-NEXT: bl .test_byval_6Byte[PR]
; ASM64-NEXT: nop
@@ -591,7 +591,7 @@ declare zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1)
; 32BIT-DAG: renamable $r[[REG2:[0-9]+]] = LBZ 6, renamable $r[[REGADDR]] :: (load 1)
; 32BIT-DAG: renamable $r4 = RLWINM killed renamable $r[[REG2]], 8, 16, 23
; 32BIT-DAG: renamable $r4 = RLWIMI killed renamable $r4, killed renamable $r[[REG1]], 16, 0, 15
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_7Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_7Byte[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_byval_7Byte:
@@ -604,7 +604,7 @@ declare zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1)
; ASM32-DAG: lbz [[REG2:[0-9]+]], 6([[REGADDR]])
; ASM32-DAG: rlwinm 4, [[REG2]], 8, 16, 23
; ASM32-DAG: rlwimi 4, [[REG1]], 16, 0, 15
-; ASM32-NEXT: bl .test_byval_7Byte
+; ASM32-NEXT: bl .test_byval_7Byte[PR]
; ASM32-NEXT: nop
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
@@ -616,7 +616,7 @@ declare zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1)
; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
; 64BIT-DAG: renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15
; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_7Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_7Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
@@ -628,7 +628,7 @@ declare zeroext i8 @test_byval_7Byte(%struct.S7* byval(%struct.S7) align 1)
; ASM64-DAG: rlwinm 3, [[REG3]], 8, 16, 23
; ASM64-DAG: rlwimi 3, [[REG2]], 16, 0, 15
; ASM64-DAG: rldimi 3, [[REG1]], 32, 0
-; ASM64-NEXT: bl .test_byval_7Byte
+; ASM64-NEXT: bl .test_byval_7Byte[PR]
; ASM64-NEXT: nop
@@ -651,7 +651,7 @@ declare zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1)
; 32BIT-NEXT: renamable $r[[REGADDR:[0-9]+]] = LWZtoc @gS8, $r2 :: (load 4 from got)
; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGADDR]] :: (load 4)
; 32BIT-DAG: renamable $r4 = LWZ 4, renamable $r[[REGADDR]] :: (load 4)
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_8Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_8Byte[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_byval_8Byte:
@@ -661,19 +661,19 @@ declare zeroext i8 @test_byval_8Byte(%struct.S8* byval(%struct.S8) align 1)
; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM32-DAG: lwz 3, 0([[REGADDR]])
; ASM32-DAG: lwz 4, 4([[REGADDR]])
-; ASM32-NEXT: bl .test_byval_8Byte
+; ASM32-NEXT: bl .test_byval_8Byte[PR]
; ASM32-NEXT: nop
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got)
; 64BIT-NEXT: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_8Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_8Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; ASM64: stdu 1, -112(1)
; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM64-NEXT: ld 3, 0([[REGADDR]])
-; ASM64-NEXT: bl .test_byval_8Byte
+; ASM64-NEXT: bl .test_byval_8Byte[PR]
; ASM64-NEXT: nop
@@ -960,7 +960,7 @@ declare i32 @test_byval_homogeneous_float_struct(%struct.F* byval(%struct.F) ali
; 32BIT-DAG: renamable $r3 = LWZ 0, %stack.0.s :: (load 4 from %stack.0.s, align 8)
; 32BIT-DAG: renamable $r4 = LWZ 4, %stack.0.s :: (load 4 from %stack.0.s + 4)
; 32BIT-DAG: renamable $r5 = LWZ 8, %stack.0.s :: (load 4 from %stack.0.s + 8, align 8)
-; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_homogeneous_float_struct>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_byval_homogeneous_float_struct[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r2, implicit-def $r1, implicit-def $r3
; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .call_test_byval_homogeneous_float_struct:
@@ -969,7 +969,7 @@ declare i32 @test_byval_homogeneous_float_struct(%struct.F* byval(%struct.F) ali
; ASM32-DAG: lwz 3, 64(1)
; ASM32-DAG: lwz 4, 68(1)
; ASM32-DAG: lwz 5, 72(1)
-; ASM32-NEXT: bl .test_byval_homogeneous_float_struct
+; ASM32-NEXT: bl .test_byval_homogeneous_float_struct[PR]
; ASM32-NEXT: nop
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
@@ -977,7 +977,7 @@ declare i32 @test_byval_homogeneous_float_struct(%struct.F* byval(%struct.F) ali
; 64BIT-DAG: renamable $x3 = LD 0, %stack.0.s :: (load 8 from %stack.0.s)
; 64BIT-DAG: renamable $x4 = LWZ8 8, %stack.0.s :: (load 4 from %stack.0.s + 8, align 8)
; 64BIT-DAG: renamable $x4 = RLDICR killed renamable $x4, 32, 31
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_homogeneous_float_struct>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1, implicit-def $x3
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_homogeneous_float_struct[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x2, implicit-def $r1, implicit-def $x3
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
@@ -985,5 +985,5 @@ declare i32 @test_byval_homogeneous_float_struct(%struct.F* byval(%struct.F) ali
; ASM64-DAG: ld 3, 112(1)
; ASM64-DAG: lwz 4, 120(1)
; ASM64-DAG: sldi 4, 4, 32
-; ASM64-NEXT: bl .test_byval_homogeneous_float_struct
+; ASM64-NEXT: bl .test_byval_homogeneous_float_struct[PR]
; ASM64-NEXT: nop
diff --git a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
index 313857986c64..0b38ba8b23b0 100644
--- a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
@@ -4,9 +4,6 @@
; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \
; RUN: -mattr=-altivec < %s | FileCheck --check-prefixes=COMMON,BIT64 %s
-; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
-; RUN: -mattr=-altivec < %s | FileCheck %s
-
; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s
; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefix=CHECKSYM %s
@@ -53,8 +50,9 @@ declare extern_weak void @foo_ext_weak(i32*)
; BIT32-NEXT: .vbyte 4, foo_ext_weak_ref[DS]
; BIT64-NEXT: .vbyte 8, foo_ext_weak_ref[DS]
; COMMON-NEXT: .weak b_w[UA]
+; COMMON-NEXT: .weak .foo_ext_weak_ref[PR]
; COMMON-NEXT: .weak foo_ext_weak_ref[DS]
-; COMMON-NEXT: .weak .foo_ext_weak
+; COMMON-NEXT: .weak .foo_ext_weak[PR]
; COMMON-NEXT: .weak foo_ext_weak[DS]
; COMMON-NEXT: .toc
; COMMON-NEXT: L..C0:
@@ -62,8 +60,6 @@ declare extern_weak void @foo_ext_weak(i32*)
; COMMON-NEXT: L..C1:
; COMMON-NEXT: .tc b_w[TC],b_w[UA]
-; CHECK-NOT: .weak .foo_ext_weak_ref
-
; CHECKSYM: Symbols [
; CHECKSYM-NEXT: Symbol {
; CHECKSYM-NEXT: Index: [[#Index:]]
@@ -127,7 +123,7 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: Symbol {
; CHECKSYM-NEXT: Index: [[#Index+6]]
-; CHECKSYM-NEXT: Name: foo_ext_weak
+; CHECKSYM-NEXT: Name: .foo_ext_weak_ref
; CHECKSYM-NEXT: Value (RelocatableAddress): 0x0
; CHECKSYM-NEXT: Section: N_UNDEF
; CHECKSYM-NEXT: Type: 0x0
@@ -140,13 +136,33 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: TypeChkSectNum: 0x0
; CHECKSYM-NEXT: SymbolAlignmentLog2: 0
; CHECKSYM-NEXT: SymbolType: XTY_ER (0x0)
-; CHECKSYM-NEXT: StorageMappingClass: XMC_DS (0xA)
+; CHECKSYM-NEXT: StorageMappingClass: XMC_PR (0x0)
; CHECKSYM-NEXT: StabInfoIndex: 0x0
; CHECKSYM-NEXT: StabSectNum: 0x0
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: Symbol {
; CHECKSYM-NEXT: Index: [[#Index+8]]
+; CHECKSYM-NEXT: Name: foo_ext_weak
+; CHECKSYM-NEXT: Value (RelocatableAddress): 0x0
+; CHECKSYM-NEXT: Section: N_UNDEF
+; CHECKSYM-NEXT: Type: 0x0
+; CHECKSYM-NEXT: StorageClass: C_WEAKEXT (0x6F)
+; CHECKSYM-NEXT: NumberOfAuxEntries: 1
+; CHECKSYM-NEXT: CSECT Auxiliary Entry {
+; CHECKSYM-NEXT: Index: [[#Index+9]]
+; CHECKSYM-NEXT: SectionLen: 0
+; CHECKSYM-NEXT: ParameterHashIndex: 0x0
+; CHECKSYM-NEXT: TypeChkSectNum: 0x0
+; CHECKSYM-NEXT: SymbolAlignmentLog2: 0
+; CHECKSYM-NEXT: SymbolType: XTY_ER (0x0)
+; CHECKSYM-NEXT: StorageMappingClass: XMC_DS (0xA)
+; CHECKSYM-NEXT: StabInfoIndex: 0x0
+; CHECKSYM-NEXT: StabSectNum: 0x0
+; CHECKSYM-NEXT: }
+; CHECKSYM-NEXT: }
+; CHECKSYM-NEXT: Symbol {
+; CHECKSYM-NEXT: Index: [[#Index+10]]
; CHECKSYM-NEXT: Name: .text
; CHECKSYM-NEXT: Value (RelocatableAddress): 0x0
; CHECKSYM-NEXT: Section: .text
@@ -154,7 +170,7 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: StorageClass: C_HIDEXT (0x6B)
; CHECKSYM-NEXT: NumberOfAuxEntries: 1
; CHECKSYM-NEXT: CSECT Auxiliary Entry {
-; CHECKSYM-NEXT: Index: [[#Index+9]]
+; CHECKSYM-NEXT: Index: [[#Index+11]]
; CHECKSYM-NEXT: SectionLen: 80
; CHECKSYM-NEXT: ParameterHashIndex: 0x0
; CHECKSYM-NEXT: TypeChkSectNum: 0x0
@@ -166,7 +182,7 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: Symbol {
-; CHECKSYM-NEXT: Index: [[#Index+10]]
+; CHECKSYM-NEXT: Index: [[#Index+12]]
; CHECKSYM-NEXT: Name: .main
; CHECKSYM-NEXT: Value (RelocatableAddress): 0x0
; CHECKSYM-NEXT: Section: .text
@@ -174,8 +190,8 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: StorageClass: C_EXT (0x2)
; CHECKSYM-NEXT: NumberOfAuxEntries: 1
; CHECKSYM-NEXT: CSECT Auxiliary Entry {
-; CHECKSYM-NEXT: Index: [[#Index+11]]
-; CHECKSYM-NEXT: ContainingCsectSymbolIndex: [[#Index+8]]
+; CHECKSYM-NEXT: Index: [[#Index+13]]
+; CHECKSYM-NEXT: ContainingCsectSymbolIndex: [[#Index+10]]
; CHECKSYM-NEXT: ParameterHashIndex: 0x0
; CHECKSYM-NEXT: TypeChkSectNum: 0x0
; CHECKSYM-NEXT: SymbolAlignmentLog2: 0
@@ -186,7 +202,7 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: Symbol {
-; CHECKSYM-NEXT: Index: [[#Index+12]]
+; CHECKSYM-NEXT: Index: [[#Index+14]]
; CHECKSYM-NEXT: Name: .data
; CHECKSYM-NEXT: Value (RelocatableAddress): 0x50
; CHECKSYM-NEXT: Section: .data
@@ -194,7 +210,7 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: StorageClass: C_HIDEXT (0x6B)
; CHECKSYM-NEXT: NumberOfAuxEntries: 1
; CHECKSYM-NEXT: CSECT Auxiliary Entry {
-; CHECKSYM-NEXT: Index: [[#Index+13]]
+; CHECKSYM-NEXT: Index: [[#Index+15]]
; CHECKSYM-NEXT: SectionLen: 4
; CHECKSYM-NEXT: ParameterHashIndex: 0x0
; CHECKSYM-NEXT: TypeChkSectNum: 0x0
@@ -206,7 +222,7 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: Symbol {
-; CHECKSYM-NEXT: Index: [[#Index+14]]
+; CHECKSYM-NEXT: Index: [[#Index+16]]
; CHECKSYM-NEXT: Name: foo_ext_weak_p
; CHECKSYM-NEXT: Value (RelocatableAddress): 0x50
; CHECKSYM-NEXT: Section: .data
@@ -214,8 +230,8 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: StorageClass: C_EXT (0x2)
; CHECKSYM-NEXT: NumberOfAuxEntries: 1
; CHECKSYM-NEXT: CSECT Auxiliary Entry {
-; CHECKSYM-NEXT: Index: [[#Index+15]]
-; CHECKSYM-NEXT: ContainingCsectSymbolIndex: [[#Index+12]]
+; CHECKSYM-NEXT: Index: [[#Index+17]]
+; CHECKSYM-NEXT: ContainingCsectSymbolIndex: [[#Index+14]]
; CHECKSYM-NEXT: ParameterHashIndex: 0x0
; CHECKSYM-NEXT: TypeChkSectNum: 0x0
; CHECKSYM-NEXT: SymbolAlignmentLog2: 0
@@ -226,7 +242,7 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: Symbol {
-; CHECKSYM-NEXT: Index: [[#Index+16]]
+; CHECKSYM-NEXT: Index: [[#Index+18]]
; CHECKSYM-NEXT: Name: main
; CHECKSYM-NEXT: Value (RelocatableAddress): 0x54
; CHECKSYM-NEXT: Section: .data
@@ -234,7 +250,7 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: StorageClass: C_EXT (0x2)
; CHECKSYM-NEXT: NumberOfAuxEntries: 1
; CHECKSYM-NEXT: CSECT Auxiliary Entry {
-; CHECKSYM-NEXT: Index: [[#Index+17]]
+; CHECKSYM-NEXT: Index: [[#Index+19]]
; CHECKSYM-NEXT: SectionLen: 12
; CHECKSYM-NEXT: ParameterHashIndex: 0x0
; CHECKSYM-NEXT: TypeChkSectNum: 0x0
@@ -246,7 +262,7 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: Symbol {
-; CHECKSYM-NEXT: Index: [[#Index+18]]
+; CHECKSYM-NEXT: Index: [[#Index+20]]
; CHECKSYM-NEXT: Name: TOC
; CHECKSYM-NEXT: Value (RelocatableAddress): 0x60
; CHECKSYM-NEXT: Section: .data
@@ -254,7 +270,7 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: StorageClass: C_HIDEXT (0x6B)
; CHECKSYM-NEXT: NumberOfAuxEntries: 1
; CHECKSYM-NEXT: CSECT Auxiliary Entry {
-; CHECKSYM-NEXT: Index: [[#Index+19]]
+; CHECKSYM-NEXT: Index: [[#Index+21]]
; CHECKSYM-NEXT: SectionLen: 0
; CHECKSYM-NEXT: ParameterHashIndex: 0x0
; CHECKSYM-NEXT: TypeChkSectNum: 0x0
@@ -266,7 +282,7 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: Symbol {
-; CHECKSYM-NEXT: Index: [[#Index+20]]
+; CHECKSYM-NEXT: Index: [[#Index+22]]
; CHECKSYM-NEXT: Name: foo_ext_weak_p
; CHECKSYM-NEXT: Value (RelocatableAddress): 0x60
; CHECKSYM-NEXT: Section: .data
@@ -274,7 +290,7 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: StorageClass: C_HIDEXT (0x6B)
; CHECKSYM-NEXT: NumberOfAuxEntries: 1
; CHECKSYM-NEXT: CSECT Auxiliary Entry {
-; CHECKSYM-NEXT: Index: [[#Index+21]]
+; CHECKSYM-NEXT: Index: [[#Index+23]]
; CHECKSYM-NEXT: SectionLen: 4
; CHECKSYM-NEXT: ParameterHashIndex: 0x0
; CHECKSYM-NEXT: TypeChkSectNum: 0x0
@@ -286,7 +302,7 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: }
; CHECKSYM-NEXT: Symbol {
-; CHECKSYM-NEXT: Index: [[#Index+22]]
+; CHECKSYM-NEXT: Index: [[#Index+24]]
; CHECKSYM-NEXT: Name: b_w
; CHECKSYM-NEXT: Value (RelocatableAddress): 0x64
; CHECKSYM-NEXT: Section: .data
@@ -294,7 +310,7 @@ declare extern_weak void @foo_ext_weak(i32*)
; CHECKSYM-NEXT: StorageClass: C_HIDEXT (0x6B)
; CHECKSYM-NEXT: NumberOfAuxEntries: 1
; CHECKSYM-NEXT: CSECT Auxiliary Entry {
-; CHECKSYM-NEXT: Index: [[#Index+23]]
+; CHECKSYM-NEXT: Index: [[#Index+25]]
; CHECKSYM-NEXT: SectionLen: 4
; CHECKSYM-NEXT: ParameterHashIndex: 0x0
; CHECKSYM-NEXT: TypeChkSectNum: 0x0
diff --git a/llvm/test/CodeGen/PowerPC/aix-external-sym-sdnode-lowering.ll b/llvm/test/CodeGen/PowerPC/aix-external-sym-sdnode-lowering.ll
index 690ff99d0530..154fcfecd342 100644
--- a/llvm/test/CodeGen/PowerPC/aix-external-sym-sdnode-lowering.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-external-sym-sdnode-lowering.ll
@@ -14,5 +14,5 @@ entry:
declare double @llvm.ceil.f64(double)
-; 32BIT: BL_NOP &.ceil
-; 64BIT: BL8_NOP &.ceil
+; 32BIT: BL_NOP &".ceil[PR]"
+; 64BIT: BL8_NOP &".ceil[PR]"
diff --git a/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll b/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
index 9b078a1f0f8a..50c08fc0b6a7 100644
--- a/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll
@@ -20,6 +20,7 @@ entry:
;CHECK-NEXT: .align 2
;CHECK-NEXT: bar_ptr1:
;CHECK-NEXT: .vbyte 4, bar[DS]
+;CHECK-NEXT: .extern .foo[PR]
;CHECK-NEXT: .extern foo[DS]
;CHECK64: .csect .data[RW],3
@@ -31,4 +32,5 @@ entry:
;CHECK64-NEXT: .align 3
;CHECK64-NEXT: bar_ptr1:
;CHECK64-NEXT: .vbyte 8, bar[DS]
+;CHECK64-NEXT: .extern .foo[PR]
;CHECK64-NEXT: .extern foo[DS]
diff --git a/llvm/test/CodeGen/PowerPC/aix-sret-param.ll b/llvm/test/CodeGen/PowerPC/aix-sret-param.ll
index 8486e471d905..98f3dccc6bb4 100644
--- a/llvm/test/CodeGen/PowerPC/aix-sret-param.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-sret-param.ll
@@ -39,13 +39,13 @@ declare void @bar(%struct.T* sret)
; MIR32: bb.0.entry:
; MIR32-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; MIR32-NEXT: renamable $r3 = ADDI %stack.0.s, 0
-; MIR32-NEXT: BL_NOP <mcsymbol .foo>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
+; MIR32-NEXT: BL_NOP <mcsymbol .foo[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
; MIR32-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; MIR64: bb.0.entry:
; MIR64-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; MIR64-NEXT: renamable $x3 = ADDI8 %stack.0.s, 0
-; MIR64-NEXT: BL8_NOP <mcsymbol .foo>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; MIR64-NEXT: BL8_NOP <mcsymbol .foo[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
@@ -53,13 +53,13 @@ declare void @bar(%struct.T* sret)
; ASM32: stwu 1, -64(1)
; ASM32-NEXT: addi 3, 1, 56
-; ASM32-NEXT: bl .foo
+; ASM32-NEXT: bl .foo[PR]
; ASM32-NEXT: nop
; ASM32-NEXT: addi 1, 1, 64
; ASM64: stdu 1, -128(1)
; ASM64-NEXT: addi 3, 1, 120
-; ASM64-NEXT: bl .foo
+; ASM64-NEXT: bl .foo[PR]
; ASM64-NEXT: nop
; ASM64-NEXT: addi 1, 1, 128
@@ -72,13 +72,13 @@ declare void @bar(%struct.T* sret)
; MIR32: bb.0.entry:
; MIR32-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
; MIR32-NEXT: renamable $r3 = ADDI %stack.0.t, 0
-; MIR32-NEXT: BL_NOP <mcsymbol .bar>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
+; MIR32-NEXT: BL_NOP <mcsymbol .bar[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
; MIR32-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; MIR64: bb.0.entry:
; MIR64-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; MIR64-NEXT: renamable $x3 = ADDI8 %stack.0.t, 0
-; MIR64-NEXT: BL8_NOP <mcsymbol .bar>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; MIR64-NEXT: BL8_NOP <mcsymbol .bar[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
@@ -86,13 +86,13 @@ declare void @bar(%struct.T* sret)
; ASM32: stwu 1, -80(1)
; ASM32-NEXT: addi 3, 1, 56
-; ASM32-NEXT: bl .bar
+; ASM32-NEXT: bl .bar[PR]
; ASM32-NEXT: nop
; ASM32-NEXT: addi 1, 1, 80
; ASM64: stdu 1, -144(1)
; ASM64-NEXT: addi 3, 1, 120
-; ASM64-NEXT: bl .bar
+; ASM64-NEXT: bl .bar[PR]
; ASM64-NEXT: nop
; ASM64-NEXT: addi 1, 1, 144
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll
index 27dac1b9a30b..72502f925d29 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll
@@ -51,7 +51,7 @@ declare i32 @"f\40o"(...)
; ASM-NEXT: .vbyte 4, 0
; ASM-NEXT: .csect .text[PR],2
; ASM-NEXT: ._Renamed..24f_o:
-; ASM: bl ._Renamed..40f_o
+; ASM: bl ._Renamed..40f_o[PR]
; ASM-NEXT: nop
; ASM: .globl _Renamed..26f_o[DS] # -- Begin function f&o
; ASM-NEXT: .rename _Renamed..26f_o[DS],"f&o"
@@ -84,8 +84,8 @@ declare i32 @"f\40o"(...)
; ASM-NEXT: .vbyte 4, 10 # 0xa
; ASM-NEXT: .comm _Renamed..2222f_o_[RW],4,2
; ASM-NEXT: .rename _Renamed..2222f_o_[RW],"f""o"""
-; ASM-NEXT: .extern ._Renamed..40f_o
-; ASM-NEXT: .rename ._Renamed..40f_o,".f at o"
+; ASM-NEXT: .extern ._Renamed..40f_o[PR]
+; ASM-NEXT: .rename ._Renamed..40f_o[PR],".f at o"
; ASM-NEXT: .extern _Renamed..40f_o[DS]
; ASM-NEXT: .rename _Renamed..40f_o[DS],"f at o"
; ASM-NEXT: .toc
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
index a637d2ae8cb1..5fa60f4eda08 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll
@@ -137,7 +137,7 @@ define void @foobar() {
; SYM-NEXT: }
; SYM-NEXT: Symbol {
; SYM-NEXT: Index: [[#UNDEF_INDX+6]]
-; SYM-NEXT: Name: foo
+; SYM-NEXT: Name: .foo
; SYM-NEXT: Value (RelocatableAddress): 0x0
; SYM-NEXT: Section: N_UNDEF
; SYM-NEXT: Type: 0x0
@@ -150,6 +150,26 @@ define void @foobar() {
; SYM-NEXT: TypeChkSectNum: 0x0
; SYM-NEXT: SymbolAlignmentLog2: 0
; SYM-NEXT: SymbolType: XTY_ER (0x0)
+; SYM-NEXT: StorageMappingClass: XMC_PR (0x0)
+; SYM-NEXT: StabInfoIndex: 0x0
+; SYM-NEXT: StabSectNum: 0x0
+; SYM-NEXT: }
+; SYM-NEXT: }
+; SYM-NEXT: Symbol {
+; SYM-NEXT: Index: [[#UNDEF_INDX+8]]
+; SYM-NEXT: Name: foo
+; SYM-NEXT: Value (RelocatableAddress): 0x0
+; SYM-NEXT: Section: N_UNDEF
+; SYM-NEXT: Type: 0x0
+; SYM-NEXT: StorageClass: C_EXT (0x2)
+; SYM-NEXT: NumberOfAuxEntries: 1
+; SYM-NEXT: CSECT Auxiliary Entry {
+; SYM-NEXT: Index: [[#UNDEF_INDX+9]]
+; SYM-NEXT: SectionLen: 0
+; SYM-NEXT: ParameterHashIndex: 0x0
+; SYM-NEXT: TypeChkSectNum: 0x0
+; SYM-NEXT: SymbolAlignmentLog2: 0
+; SYM-NEXT: SymbolType: XTY_ER (0x0)
; SYM-NEXT: StorageMappingClass: XMC_DS (0xA)
; SYM-NEXT: StabInfoIndex: 0x0
; SYM-NEXT: StabSectNum: 0x0
diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-visibility.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-visibility.ll
index a4c0b93a13a4..04c2e0cfe22b 100644
--- a/llvm/test/CodeGen/PowerPC/aix-xcoff-visibility.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-visibility.ll
@@ -52,6 +52,7 @@ declare hidden i32 @bar_h(i32*)
; CHECK: .globl b{{[[:space:]]*([#].*)?$}}
; CHECK: .globl b_h,hidden
+; CHECK: .weak .zoo_weak_extern_h[PR],hidden
; CHECK: .weak zoo_weak_extern_h[DS],hidden
-; CHECK: .extern .bar_h,hidden
+; CHECK: .extern .bar_h[PR],hidden
; CHECK: .extern bar_h[DS],hidden
diff --git a/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll b/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
index 7700c988b6c5..97c1490e7ebb 100644
--- a/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
+++ b/llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll
@@ -134,7 +134,7 @@ declare void @test_byval_64Byte(%struct.S64* byval(%struct.S64) align 1)
; CHECK-DAG: renamable $x8 = LD 40, renamable $x[[REGADDR]] :: (load 8)
; CHECK-DAG: renamable $x9 = LD 48, renamable $x[[REGADDR]] :: (load 8)
; CHECK-DAG: renamable $x10 = LD 56, renamable $x[[REGADDR]] :: (load 8)
-; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_64Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
+; CHECK-NEXT: BL8_NOP <mcsymbol .test_byval_64Byte[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
; CHECK-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; CHECKASM-LABEL: .test_byval_64Byte:
diff --git a/llvm/test/CodeGen/PowerPC/test_call_aix.ll b/llvm/test/CodeGen/PowerPC/test_call_aix.ll
index cb2ebaba5e0f..4065fc860307 100644
--- a/llvm/test/CodeGen/PowerPC/test_call_aix.ll
+++ b/llvm/test/CodeGen/PowerPC/test_call_aix.ll
@@ -12,11 +12,11 @@ declare void @foo(...)
define void @test_call() {
entry:
; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: BL_NOP <mcsymbol .foo>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r2, implicit-def $r1
+; 32BIT: BL_NOP <mcsymbol .foo[PR]>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r2, implicit-def $r1
; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: BL8_NOP <mcsymbol .foo>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x2, implicit-def $r1
+; 64BIT: BL8_NOP <mcsymbol .foo[PR]>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x2, implicit-def $r1
; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; CHECK-LABEL: test_call
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