[PATCH] D85233: [GlobalISel] Implement bit-test switch table optimization

[Amara Emerson via Phabricator via llvm-commits]

aemerson added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll:132
+  ret void
+}
----------------
arsenm wrote:
> Can you add a few degenerate cases with 1 and 2 switch cases (and 0 if that's even accepted).
> 
> I also don't think any of these hit the omit-branch-to-next block case
I'll add a test to check for a single BT cluster, but 1 or 2 switch cases by themselves won't trigger this optimization, it'll just use a simple equality check.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D85233/new/

https://reviews.llvm.org/D85233