[PATCH] D85726: [VE] Change to promote i32 AND/OR/XOR operations

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 created this revision.
kaz7 added reviewers: simoll, k-ishizaka.
kaz7 added projects: LLVM, VE.
Herald added subscribers: llvm-commits, hiraditya.
kaz7 requested review of this revision.

VE has only 64 bits AND/OR/XOR instructions.  We pretended that VE has 32 bits
instructions also, but doing it increase the number of generated instructions.
Therefore, we decide to promote 32 bits operations and use only 64 bits
instructions in back end.  We also avoid pretending that VE has 32 bits LEA
instruction.  Update regression tests also.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D85726

Files:
  llvm/lib/Target/VE/VEISelLowering.cpp
  llvm/lib/Target/VE/VEInstrInfo.td
  llvm/test/CodeGen/VE/cttz.ll
  llvm/test/CodeGen/VE/nnd.ll
  llvm/test/CodeGen/VE/or.ll
  llvm/test/CodeGen/VE/selectccf32c.ll
  llvm/test/CodeGen/VE/selectccf64c.ll
  llvm/test/CodeGen/VE/selectcci32c.ll
  llvm/test/CodeGen/VE/selectcci64c.ll
  llvm/test/CodeGen/VE/xor.ll

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