[llvm] ab6a517 - Fix "CHECK-LABEL: @" typos in llvm/test/CodeGen/AArch64/sve-fixed-length-*.ll
Paul Walker via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 10 12:15:53 PDT 2020
Author: Paul Walker
Date: 2020-08-10T20:07:45+01:00
New Revision: ab6a517ea41e1cb63856cce6f7fa4a196ffca368
URL: https://github.com/llvm/llvm-project/commit/ab6a517ea41e1cb63856cce6f7fa4a196ffca368
DIFF: https://github.com/llvm/llvm-project/commit/ab6a517ea41e1cb63856cce6f7fa4a196ffca368.diff
LOG: Fix "CHECK-LABEL: @" typos in llvm/test/CodeGen/AArch64/sve-fixed-length-*.ll
Added:
Modified:
llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
index 242fabe44f79..f8a37e7d81fe 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-arith.ll
@@ -31,7 +31,7 @@ target triple = "aarch64-unknown-linux-gnu"
; Don't use SVE for 64-bit vectors.
define <4 x half> @fadd_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
-; CHECK-LABEL: @fadd_v4f16
+; CHECK-LABEL: fadd_v4f16:
; CHECK: fadd v0.4h, v0.4h, v1.4h
; CHECK: ret
%res = fadd <4 x half> %op1, %op2
@@ -40,7 +40,7 @@ define <4 x half> @fadd_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <8 x half> @fadd_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
-; CHECK-LABEL: @fadd_v8f16
+; CHECK-LABEL: fadd_v8f16:
; CHECK: fadd v0.8h, v0.8h, v1.8h
; CHECK: ret
%res = fadd <8 x half> %op1, %op2
@@ -48,7 +48,7 @@ define <8 x half> @fadd_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
}
define void @fadd_v16f16(<16 x half>* %a, <16 x half>* %b) #0 {
-; CHECK-LABEL: @fadd_v16f16
+; CHECK-LABEL: fadd_v16f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),16)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -63,7 +63,7 @@ define void @fadd_v16f16(<16 x half>* %a, <16 x half>* %b) #0 {
}
define void @fadd_v32f16(<32 x half>* %a, <32 x half>* %b) #0 {
-; CHECK-LABEL: @fadd_v32f16
+; CHECK-LABEL: fadd_v32f16:
; CHECK-DAG: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),32)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -84,7 +84,7 @@ define void @fadd_v32f16(<32 x half>* %a, <32 x half>* %b) #0 {
}
define void @fadd_v64f16(<64 x half>* %a, <64 x half>* %b) #0 {
-; CHECK-LABEL: @fadd_v64f16
+; CHECK-LABEL: fadd_v64f16:
; CHECK-DAG: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),64)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -119,7 +119,7 @@ define void @fadd_v64f16(<64 x half>* %a, <64 x half>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the fadd_v#f16 tests
; already cover the general legalisation cases.
define void @fadd_v128f16(<128 x half>* %a, <128 x half>* %b) #0 {
-; CHECK-LABEL: @fadd_v128f16
+; CHECK-LABEL: fadd_v128f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),128)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -135,7 +135,7 @@ define void @fadd_v128f16(<128 x half>* %a, <128 x half>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <2 x float> @fadd_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
-; CHECK-LABEL: @fadd_v2f32
+; CHECK-LABEL: fadd_v2f32:
; CHECK: fadd v0.2s, v0.2s, v1.2s
; CHECK: ret
%res = fadd <2 x float> %op1, %op2
@@ -144,7 +144,7 @@ define <2 x float> @fadd_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <4 x float> @fadd_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
-; CHECK-LABEL: @fadd_v4f32
+; CHECK-LABEL: fadd_v4f32:
; CHECK: fadd v0.4s, v0.4s, v1.4s
; CHECK: ret
%res = fadd <4 x float> %op1, %op2
@@ -152,7 +152,7 @@ define <4 x float> @fadd_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
}
define void @fadd_v8f32(<8 x float>* %a, <8 x float>* %b) #0 {
-; CHECK-LABEL: @fadd_v8f32
+; CHECK-LABEL: fadd_v8f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -169,7 +169,7 @@ define void @fadd_v8f32(<8 x float>* %a, <8 x float>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the fadd_v#f16 tests
; already cover the general legalisation cases.
define void @fadd_v16f32(<16 x float>* %a, <16 x float>* %b) #0 {
-; CHECK-LABEL: @fadd_v16f32
+; CHECK-LABEL: fadd_v16f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -186,7 +186,7 @@ define void @fadd_v16f32(<16 x float>* %a, <16 x float>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the fadd_v#f16 tests
; already cover the general legalisation cases.
define void @fadd_v32f32(<32 x float>* %a, <32 x float>* %b) #0 {
-; CHECK-LABEL: @fadd_v32f32
+; CHECK-LABEL: fadd_v32f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -203,7 +203,7 @@ define void @fadd_v32f32(<32 x float>* %a, <32 x float>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the fadd_v#f16 tests
; already cover the general legalisation cases.
define void @fadd_v64f32(<64 x float>* %a, <64 x float>* %b) #0 {
-; CHECK-LABEL: @fadd_v64f32
+; CHECK-LABEL: fadd_v64f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -219,7 +219,7 @@ define void @fadd_v64f32(<64 x float>* %a, <64 x float>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <1 x double> @fadd_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
-; CHECK-LABEL: @fadd_v1f64
+; CHECK-LABEL: fadd_v1f64:
; CHECK: fadd d0, d0, d1
; CHECK: ret
%res = fadd <1 x double> %op1, %op2
@@ -228,7 +228,7 @@ define <1 x double> @fadd_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <2 x double> @fadd_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
-; CHECK-LABEL: @fadd_v2f64
+; CHECK-LABEL: fadd_v2f64:
; CHECK: fadd v0.2d, v0.2d, v1.2d
; CHECK: ret
%res = fadd <2 x double> %op1, %op2
@@ -236,7 +236,7 @@ define <2 x double> @fadd_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
}
define void @fadd_v4f64(<4 x double>* %a, <4 x double>* %b) #0 {
-; CHECK-LABEL: @fadd_v4f64
+; CHECK-LABEL: fadd_v4f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -253,7 +253,7 @@ define void @fadd_v4f64(<4 x double>* %a, <4 x double>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the fadd_v#f16 tests
; already cover the general legalisation cases.
define void @fadd_v8f64(<8 x double>* %a, <8 x double>* %b) #0 {
-; CHECK-LABEL: @fadd_v8f64
+; CHECK-LABEL: fadd_v8f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -270,7 +270,7 @@ define void @fadd_v8f64(<8 x double>* %a, <8 x double>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the fadd_v#f16 tests
; already cover the general legalisation cases.
define void @fadd_v16f64(<16 x double>* %a, <16 x double>* %b) #0 {
-; CHECK-LABEL: @fadd_v16f64
+; CHECK-LABEL: fadd_v16f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -287,7 +287,7 @@ define void @fadd_v16f64(<16 x double>* %a, <16 x double>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the fadd_v#f16 tests
; already cover the general legalisation cases.
define void @fadd_v32f64(<32 x double>* %a, <32 x double>* %b) #0 {
-; CHECK-LABEL: @fadd_v32f64
+; CHECK-LABEL: fadd_v32f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -312,7 +312,7 @@ define void @fadd_v32f64(<32 x double>* %a, <32 x double>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <4 x half> @fdiv_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
-; CHECK-LABEL: @fdiv_v4f16
+; CHECK-LABEL: fdiv_v4f16:
; CHECK: fdiv v0.4h, v0.4h, v1.4h
; CHECK: ret
%res = fdiv <4 x half> %op1, %op2
@@ -321,7 +321,7 @@ define <4 x half> @fdiv_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <8 x half> @fdiv_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
-; CHECK-LABEL: @fdiv_v8f16
+; CHECK-LABEL: fdiv_v8f16:
; CHECK: fdiv v0.8h, v0.8h, v1.8h
; CHECK: ret
%res = fdiv <8 x half> %op1, %op2
@@ -329,7 +329,7 @@ define <8 x half> @fdiv_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
}
define void @fdiv_v16f16(<16 x half>* %a, <16 x half>* %b) #0 {
-; CHECK-LABEL: @fdiv_v16f16
+; CHECK-LABEL: fdiv_v16f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),16)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -344,7 +344,7 @@ define void @fdiv_v16f16(<16 x half>* %a, <16 x half>* %b) #0 {
}
define void @fdiv_v32f16(<32 x half>* %a, <32 x half>* %b) #0 {
-; CHECK-LABEL: @fdiv_v32f16
+; CHECK-LABEL: fdiv_v32f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),32)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -359,7 +359,7 @@ define void @fdiv_v32f16(<32 x half>* %a, <32 x half>* %b) #0 {
}
define void @fdiv_v64f16(<64 x half>* %a, <64 x half>* %b) #0 {
-; CHECK-LABEL: @fdiv_v64f16
+; CHECK-LABEL: fdiv_v64f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),64)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -374,7 +374,7 @@ define void @fdiv_v64f16(<64 x half>* %a, <64 x half>* %b) #0 {
}
define void @fdiv_v128f16(<128 x half>* %a, <128 x half>* %b) #0 {
-; CHECK-LABEL: @fdiv_v128f16
+; CHECK-LABEL: fdiv_v128f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),128)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -390,7 +390,7 @@ define void @fdiv_v128f16(<128 x half>* %a, <128 x half>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <2 x float> @fdiv_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
-; CHECK-LABEL: @fdiv_v2f32
+; CHECK-LABEL: fdiv_v2f32:
; CHECK: fdiv v0.2s, v0.2s, v1.2s
; CHECK: ret
%res = fdiv <2 x float> %op1, %op2
@@ -399,7 +399,7 @@ define <2 x float> @fdiv_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <4 x float> @fdiv_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
-; CHECK-LABEL: @fdiv_v4f32
+; CHECK-LABEL: fdiv_v4f32:
; CHECK: fdiv v0.4s, v0.4s, v1.4s
; CHECK: ret
%res = fdiv <4 x float> %op1, %op2
@@ -407,7 +407,7 @@ define <4 x float> @fdiv_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
}
define void @fdiv_v8f32(<8 x float>* %a, <8 x float>* %b) #0 {
-; CHECK-LABEL: @fdiv_v8f32
+; CHECK-LABEL: fdiv_v8f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -422,7 +422,7 @@ define void @fdiv_v8f32(<8 x float>* %a, <8 x float>* %b) #0 {
}
define void @fdiv_v16f32(<16 x float>* %a, <16 x float>* %b) #0 {
-; CHECK-LABEL: @fdiv_v16f32
+; CHECK-LABEL: fdiv_v16f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -437,7 +437,7 @@ define void @fdiv_v16f32(<16 x float>* %a, <16 x float>* %b) #0 {
}
define void @fdiv_v32f32(<32 x float>* %a, <32 x float>* %b) #0 {
-; CHECK-LABEL: @fdiv_v32f32
+; CHECK-LABEL: fdiv_v32f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -452,7 +452,7 @@ define void @fdiv_v32f32(<32 x float>* %a, <32 x float>* %b) #0 {
}
define void @fdiv_v64f32(<64 x float>* %a, <64 x float>* %b) #0 {
-; CHECK-LABEL: @fdiv_v64f32
+; CHECK-LABEL: fdiv_v64f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -468,7 +468,7 @@ define void @fdiv_v64f32(<64 x float>* %a, <64 x float>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <1 x double> @fdiv_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
-; CHECK-LABEL: @fdiv_v1f64
+; CHECK-LABEL: fdiv_v1f64:
; CHECK: fdiv d0, d0, d1
; CHECK: ret
%res = fdiv <1 x double> %op1, %op2
@@ -477,7 +477,7 @@ define <1 x double> @fdiv_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <2 x double> @fdiv_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
-; CHECK-LABEL: @fdiv_v2f64
+; CHECK-LABEL: fdiv_v2f64:
; CHECK: fdiv v0.2d, v0.2d, v1.2d
; CHECK: ret
%res = fdiv <2 x double> %op1, %op2
@@ -485,7 +485,7 @@ define <2 x double> @fdiv_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
}
define void @fdiv_v4f64(<4 x double>* %a, <4 x double>* %b) #0 {
-; CHECK-LABEL: @fdiv_v4f64
+; CHECK-LABEL: fdiv_v4f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -500,7 +500,7 @@ define void @fdiv_v4f64(<4 x double>* %a, <4 x double>* %b) #0 {
}
define void @fdiv_v8f64(<8 x double>* %a, <8 x double>* %b) #0 {
-; CHECK-LABEL: @fdiv_v8f64
+; CHECK-LABEL: fdiv_v8f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -515,7 +515,7 @@ define void @fdiv_v8f64(<8 x double>* %a, <8 x double>* %b) #0 {
}
define void @fdiv_v16f64(<16 x double>* %a, <16 x double>* %b) #0 {
-; CHECK-LABEL: @fdiv_v16f64
+; CHECK-LABEL: fdiv_v16f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -530,7 +530,7 @@ define void @fdiv_v16f64(<16 x double>* %a, <16 x double>* %b) #0 {
}
define void @fdiv_v32f64(<32 x double>* %a, <32 x double>* %b) #0 {
-; CHECK-LABEL: @fdiv_v32f64
+; CHECK-LABEL: fdiv_v32f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -550,7 +550,7 @@ define void @fdiv_v32f64(<32 x double>* %a, <32 x double>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <4 x half> @fma_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3) #0 {
-; CHECK-LABEL: @fma_v4f16
+; CHECK-LABEL: fma_v4f16:
; CHECK: fmla v2.4h, v1.4h, v0.4h
; CHECK: ret
%res = call <4 x half> @llvm.fma.v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3)
@@ -559,7 +559,7 @@ define <4 x half> @fma_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x half> %op3)
; Don't use SVE for 128-bit vectors.
define <8 x half> @fma_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3) #0 {
-; CHECK-LABEL: @fma_v8f16
+; CHECK-LABEL: fma_v8f16:
; CHECK: fmla v2.8h, v1.8h, v0.8h
; CHECK: ret
%res = call <8 x half> @llvm.fma.v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3)
@@ -567,7 +567,7 @@ define <8 x half> @fma_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x half> %op3)
}
define void @fma_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x half>* %c) #0 {
-; CHECK-LABEL: @fma_v16f16
+; CHECK-LABEL: fma_v16f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),16)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -584,7 +584,7 @@ define void @fma_v16f16(<16 x half>* %a, <16 x half>* %b, <16 x half>* %c) #0 {
}
define void @fma_v32f16(<32 x half>* %a, <32 x half>* %b, <32 x half>* %c) #0 {
-; CHECK-LABEL: @fma_v32f16
+; CHECK-LABEL: fma_v32f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),32)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -601,7 +601,7 @@ define void @fma_v32f16(<32 x half>* %a, <32 x half>* %b, <32 x half>* %c) #0 {
}
define void @fma_v64f16(<64 x half>* %a, <64 x half>* %b, <64 x half>* %c) #0 {
-; CHECK-LABEL: @fma_v64f16
+; CHECK-LABEL: fma_v64f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),64)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -618,7 +618,7 @@ define void @fma_v64f16(<64 x half>* %a, <64 x half>* %b, <64 x half>* %c) #0 {
}
define void @fma_v128f16(<128 x half>* %a, <128 x half>* %b, <128 x half>* %c) #0 {
-; CHECK-LABEL: @fma_v128f16
+; CHECK-LABEL: fma_v128f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),128)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -636,7 +636,7 @@ define void @fma_v128f16(<128 x half>* %a, <128 x half>* %b, <128 x half>* %c) #
; Don't use SVE for 64-bit vectors.
define <2 x float> @fma_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %op3) #0 {
-; CHECK-LABEL: @fma_v2f32
+; CHECK-LABEL: fma_v2f32:
; CHECK: fmla v2.2s, v1.2s, v0.2s
; CHECK: ret
%res = call <2 x float> @llvm.fma.v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %op3)
@@ -645,7 +645,7 @@ define <2 x float> @fma_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x float> %o
; Don't use SVE for 128-bit vectors.
define <4 x float> @fma_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %op3) #0 {
-; CHECK-LABEL: @fma_v4f32
+; CHECK-LABEL: fma_v4f32:
; CHECK: fmla v2.4s, v1.4s, v0.4s
; CHECK: ret
%res = call <4 x float> @llvm.fma.v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %op3)
@@ -653,7 +653,7 @@ define <4 x float> @fma_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x float> %o
}
define void @fma_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) #0 {
-; CHECK-LABEL: @fma_v8f32
+; CHECK-LABEL: fma_v8f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -670,7 +670,7 @@ define void @fma_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) #0 {
}
define void @fma_v16f32(<16 x float>* %a, <16 x float>* %b, <16 x float>* %c) #0 {
-; CHECK-LABEL: @fma_v16f32
+; CHECK-LABEL: fma_v16f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -687,7 +687,7 @@ define void @fma_v16f32(<16 x float>* %a, <16 x float>* %b, <16 x float>* %c) #0
}
define void @fma_v32f32(<32 x float>* %a, <32 x float>* %b, <32 x float>* %c) #0 {
-; CHECK-LABEL: @fma_v32f32
+; CHECK-LABEL: fma_v32f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -704,7 +704,7 @@ define void @fma_v32f32(<32 x float>* %a, <32 x float>* %b, <32 x float>* %c) #0
}
define void @fma_v64f32(<64 x float>* %a, <64 x float>* %b, <64 x float>* %c) #0 {
-; CHECK-LABEL: @fma_v64f32
+; CHECK-LABEL: fma_v64f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -722,7 +722,7 @@ define void @fma_v64f32(<64 x float>* %a, <64 x float>* %b, <64 x float>* %c) #0
; Don't use SVE for 64-bit vectors.
define <1 x double> @fma_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x double> %op3) #0 {
-; CHECK-LABEL: @fma_v1f64
+; CHECK-LABEL: fma_v1f64:
; CHECK: fmadd d0, d0, d1, d2
; CHECK: ret
%res = call <1 x double> @llvm.fma.v1f64(<1 x double> %op1, <1 x double> %op2, <1 x double> %op3)
@@ -731,7 +731,7 @@ define <1 x double> @fma_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x double
; Don't use SVE for 128-bit vectors.
define <2 x double> @fma_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double> %op3) #0 {
-; CHECK-LABEL: @fma_v2f64
+; CHECK-LABEL: fma_v2f64:
; CHECK: fmla v2.2d, v1.2d, v0.2d
; CHECK: ret
%res = call <2 x double> @llvm.fma.v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double> %op3)
@@ -739,7 +739,7 @@ define <2 x double> @fma_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x double
}
define void @fma_v4f64(<4 x double>* %a, <4 x double>* %b, <4 x double>* %c) #0 {
-; CHECK-LABEL: @fma_v4f64
+; CHECK-LABEL: fma_v4f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -756,7 +756,7 @@ define void @fma_v4f64(<4 x double>* %a, <4 x double>* %b, <4 x double>* %c) #0
}
define void @fma_v8f64(<8 x double>* %a, <8 x double>* %b, <8 x double>* %c) #0 {
-; CHECK-LABEL: @fma_v8f64
+; CHECK-LABEL: fma_v8f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -773,7 +773,7 @@ define void @fma_v8f64(<8 x double>* %a, <8 x double>* %b, <8 x double>* %c) #0
}
define void @fma_v16f64(<16 x double>* %a, <16 x double>* %b, <16 x double>* %c) #0 {
-; CHECK-LABEL: @fma_v16f64
+; CHECK-LABEL: fma_v16f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -790,7 +790,7 @@ define void @fma_v16f64(<16 x double>* %a, <16 x double>* %b, <16 x double>* %c)
}
define void @fma_v32f64(<32 x double>* %a, <32 x double>* %b, <32 x double>* %c) #0 {
-; CHECK-LABEL: @fma_v32f64
+; CHECK-LABEL: fma_v32f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -812,7 +812,7 @@ define void @fma_v32f64(<32 x double>* %a, <32 x double>* %b, <32 x double>* %c)
; Don't use SVE for 64-bit vectors.
define <4 x half> @fmul_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
-; CHECK-LABEL: @fmul_v4f16
+; CHECK-LABEL: fmul_v4f16:
; CHECK: fmul v0.4h, v0.4h, v1.4h
; CHECK: ret
%res = fmul <4 x half> %op1, %op2
@@ -821,7 +821,7 @@ define <4 x half> @fmul_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <8 x half> @fmul_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
-; CHECK-LABEL: @fmul_v8f16
+; CHECK-LABEL: fmul_v8f16:
; CHECK: fmul v0.8h, v0.8h, v1.8h
; CHECK: ret
%res = fmul <8 x half> %op1, %op2
@@ -829,7 +829,7 @@ define <8 x half> @fmul_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
}
define void @fmul_v16f16(<16 x half>* %a, <16 x half>* %b) #0 {
-; CHECK-LABEL: @fmul_v16f16
+; CHECK-LABEL: fmul_v16f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),16)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -844,7 +844,7 @@ define void @fmul_v16f16(<16 x half>* %a, <16 x half>* %b) #0 {
}
define void @fmul_v32f16(<32 x half>* %a, <32 x half>* %b) #0 {
-; CHECK-LABEL: @fmul_v32f16
+; CHECK-LABEL: fmul_v32f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),32)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -859,7 +859,7 @@ define void @fmul_v32f16(<32 x half>* %a, <32 x half>* %b) #0 {
}
define void @fmul_v64f16(<64 x half>* %a, <64 x half>* %b) #0 {
-; CHECK-LABEL: @fmul_v64f16
+; CHECK-LABEL: fmul_v64f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),64)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -874,7 +874,7 @@ define void @fmul_v64f16(<64 x half>* %a, <64 x half>* %b) #0 {
}
define void @fmul_v128f16(<128 x half>* %a, <128 x half>* %b) #0 {
-; CHECK-LABEL: @fmul_v128f16
+; CHECK-LABEL: fmul_v128f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),128)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -890,7 +890,7 @@ define void @fmul_v128f16(<128 x half>* %a, <128 x half>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <2 x float> @fmul_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
-; CHECK-LABEL: @fmul_v2f32
+; CHECK-LABEL: fmul_v2f32:
; CHECK: fmul v0.2s, v0.2s, v1.2s
; CHECK: ret
%res = fmul <2 x float> %op1, %op2
@@ -899,7 +899,7 @@ define <2 x float> @fmul_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <4 x float> @fmul_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
-; CHECK-LABEL: @fmul_v4f32
+; CHECK-LABEL: fmul_v4f32:
; CHECK: fmul v0.4s, v0.4s, v1.4s
; CHECK: ret
%res = fmul <4 x float> %op1, %op2
@@ -907,7 +907,7 @@ define <4 x float> @fmul_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
}
define void @fmul_v8f32(<8 x float>* %a, <8 x float>* %b) #0 {
-; CHECK-LABEL: @fmul_v8f32
+; CHECK-LABEL: fmul_v8f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -922,7 +922,7 @@ define void @fmul_v8f32(<8 x float>* %a, <8 x float>* %b) #0 {
}
define void @fmul_v16f32(<16 x float>* %a, <16 x float>* %b) #0 {
-; CHECK-LABEL: @fmul_v16f32
+; CHECK-LABEL: fmul_v16f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -937,7 +937,7 @@ define void @fmul_v16f32(<16 x float>* %a, <16 x float>* %b) #0 {
}
define void @fmul_v32f32(<32 x float>* %a, <32 x float>* %b) #0 {
-; CHECK-LABEL: @fmul_v32f32
+; CHECK-LABEL: fmul_v32f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -952,7 +952,7 @@ define void @fmul_v32f32(<32 x float>* %a, <32 x float>* %b) #0 {
}
define void @fmul_v64f32(<64 x float>* %a, <64 x float>* %b) #0 {
-; CHECK-LABEL: @fmul_v64f32
+; CHECK-LABEL: fmul_v64f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -968,7 +968,7 @@ define void @fmul_v64f32(<64 x float>* %a, <64 x float>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <1 x double> @fmul_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
-; CHECK-LABEL: @fmul_v1f64
+; CHECK-LABEL: fmul_v1f64:
; CHECK: fmul d0, d0, d1
; CHECK: ret
%res = fmul <1 x double> %op1, %op2
@@ -977,7 +977,7 @@ define <1 x double> @fmul_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <2 x double> @fmul_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
-; CHECK-LABEL: @fmul_v2f64
+; CHECK-LABEL: fmul_v2f64:
; CHECK: fmul v0.2d, v0.2d, v1.2d
; CHECK: ret
%res = fmul <2 x double> %op1, %op2
@@ -985,7 +985,7 @@ define <2 x double> @fmul_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
}
define void @fmul_v4f64(<4 x double>* %a, <4 x double>* %b) #0 {
-; CHECK-LABEL: @fmul_v4f64
+; CHECK-LABEL: fmul_v4f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -1000,7 +1000,7 @@ define void @fmul_v4f64(<4 x double>* %a, <4 x double>* %b) #0 {
}
define void @fmul_v8f64(<8 x double>* %a, <8 x double>* %b) #0 {
-; CHECK-LABEL: @fmul_v8f64
+; CHECK-LABEL: fmul_v8f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -1015,7 +1015,7 @@ define void @fmul_v8f64(<8 x double>* %a, <8 x double>* %b) #0 {
}
define void @fmul_v16f64(<16 x double>* %a, <16 x double>* %b) #0 {
-; CHECK-LABEL: @fmul_v16f64
+; CHECK-LABEL: fmul_v16f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -1030,7 +1030,7 @@ define void @fmul_v16f64(<16 x double>* %a, <16 x double>* %b) #0 {
}
define void @fmul_v32f64(<32 x double>* %a, <32 x double>* %b) #0 {
-; CHECK-LABEL: @fmul_v32f64
+; CHECK-LABEL: fmul_v32f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -1050,7 +1050,7 @@ define void @fmul_v32f64(<32 x double>* %a, <32 x double>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <4 x half> @fsub_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
-; CHECK-LABEL: @fsub_v4f16
+; CHECK-LABEL: fsub_v4f16:
; CHECK: fsub v0.4h, v0.4h, v1.4h
; CHECK: ret
%res = fsub <4 x half> %op1, %op2
@@ -1059,7 +1059,7 @@ define <4 x half> @fsub_v4f16(<4 x half> %op1, <4 x half> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <8 x half> @fsub_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
-; CHECK-LABEL: @fsub_v8f16
+; CHECK-LABEL: fsub_v8f16:
; CHECK: fsub v0.8h, v0.8h, v1.8h
; CHECK: ret
%res = fsub <8 x half> %op1, %op2
@@ -1067,7 +1067,7 @@ define <8 x half> @fsub_v8f16(<8 x half> %op1, <8 x half> %op2) #0 {
}
define void @fsub_v16f16(<16 x half>* %a, <16 x half>* %b) #0 {
-; CHECK-LABEL: @fsub_v16f16
+; CHECK-LABEL: fsub_v16f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),16)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -1082,7 +1082,7 @@ define void @fsub_v16f16(<16 x half>* %a, <16 x half>* %b) #0 {
}
define void @fsub_v32f16(<32 x half>* %a, <32 x half>* %b) #0 {
-; CHECK-LABEL: @fsub_v32f16
+; CHECK-LABEL: fsub_v32f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),32)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -1097,7 +1097,7 @@ define void @fsub_v32f16(<32 x half>* %a, <32 x half>* %b) #0 {
}
define void @fsub_v64f16(<64 x half>* %a, <64 x half>* %b) #0 {
-; CHECK-LABEL: @fsub_v64f16
+; CHECK-LABEL: fsub_v64f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),64)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -1112,7 +1112,7 @@ define void @fsub_v64f16(<64 x half>* %a, <64 x half>* %b) #0 {
}
define void @fsub_v128f16(<128 x half>* %a, <128 x half>* %b) #0 {
-; CHECK-LABEL: @fsub_v128f16
+; CHECK-LABEL: fsub_v128f16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),128)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -1128,7 +1128,7 @@ define void @fsub_v128f16(<128 x half>* %a, <128 x half>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <2 x float> @fsub_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
-; CHECK-LABEL: @fsub_v2f32
+; CHECK-LABEL: fsub_v2f32:
; CHECK: fsub v0.2s, v0.2s, v1.2s
; CHECK: ret
%res = fsub <2 x float> %op1, %op2
@@ -1137,7 +1137,7 @@ define <2 x float> @fsub_v2f32(<2 x float> %op1, <2 x float> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <4 x float> @fsub_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
-; CHECK-LABEL: @fsub_v4f32
+; CHECK-LABEL: fsub_v4f32:
; CHECK: fsub v0.4s, v0.4s, v1.4s
; CHECK: ret
%res = fsub <4 x float> %op1, %op2
@@ -1145,7 +1145,7 @@ define <4 x float> @fsub_v4f32(<4 x float> %op1, <4 x float> %op2) #0 {
}
define void @fsub_v8f32(<8 x float>* %a, <8 x float>* %b) #0 {
-; CHECK-LABEL: @fsub_v8f32
+; CHECK-LABEL: fsub_v8f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -1160,7 +1160,7 @@ define void @fsub_v8f32(<8 x float>* %a, <8 x float>* %b) #0 {
}
define void @fsub_v16f32(<16 x float>* %a, <16 x float>* %b) #0 {
-; CHECK-LABEL: @fsub_v16f32
+; CHECK-LABEL: fsub_v16f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -1175,7 +1175,7 @@ define void @fsub_v16f32(<16 x float>* %a, <16 x float>* %b) #0 {
}
define void @fsub_v32f32(<32 x float>* %a, <32 x float>* %b) #0 {
-; CHECK-LABEL: @fsub_v32f32
+; CHECK-LABEL: fsub_v32f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -1190,7 +1190,7 @@ define void @fsub_v32f32(<32 x float>* %a, <32 x float>* %b) #0 {
}
define void @fsub_v64f32(<64 x float>* %a, <64 x float>* %b) #0 {
-; CHECK-LABEL: @fsub_v64f32
+; CHECK-LABEL: fsub_v64f32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -1206,7 +1206,7 @@ define void @fsub_v64f32(<64 x float>* %a, <64 x float>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <1 x double> @fsub_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
-; CHECK-LABEL: @fsub_v1f64
+; CHECK-LABEL: fsub_v1f64:
; CHECK: fsub d0, d0, d1
; CHECK: ret
%res = fsub <1 x double> %op1, %op2
@@ -1215,7 +1215,7 @@ define <1 x double> @fsub_v1f64(<1 x double> %op1, <1 x double> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <2 x double> @fsub_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
-; CHECK-LABEL: @fsub_v2f64
+; CHECK-LABEL: fsub_v2f64:
; CHECK: fsub v0.2d, v0.2d, v1.2d
; CHECK: ret
%res = fsub <2 x double> %op1, %op2
@@ -1223,7 +1223,7 @@ define <2 x double> @fsub_v2f64(<2 x double> %op1, <2 x double> %op2) #0 {
}
define void @fsub_v4f64(<4 x double>* %a, <4 x double>* %b) #0 {
-; CHECK-LABEL: @fsub_v4f64
+; CHECK-LABEL: fsub_v4f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -1238,7 +1238,7 @@ define void @fsub_v4f64(<4 x double>* %a, <4 x double>* %b) #0 {
}
define void @fsub_v8f64(<8 x double>* %a, <8 x double>* %b) #0 {
-; CHECK-LABEL: @fsub_v8f64
+; CHECK-LABEL: fsub_v8f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -1253,7 +1253,7 @@ define void @fsub_v8f64(<8 x double>* %a, <8 x double>* %b) #0 {
}
define void @fsub_v16f64(<16 x double>* %a, <16 x double>* %b) #0 {
-; CHECK-LABEL: @fsub_v16f64
+; CHECK-LABEL: fsub_v16f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -1268,7 +1268,7 @@ define void @fsub_v16f64(<16 x double>* %a, <16 x double>* %b) #0 {
}
define void @fsub_v32f64(<32 x double>* %a, <32 x double>* %b) #0 {
-; CHECK-LABEL: @fsub_v32f64
+; CHECK-LABEL: fsub_v32f64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
index 9f172e51d85d..2ee77fe41bf0 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
@@ -25,9 +25,13 @@ target triple = "aarch64-unknown-linux-gnu"
; Don't use SVE when its registers are no bigger than NEON.
; NO_SVE-NOT: ptrue
+;
+; ADD
+;
+
; Don't use SVE for 64-bit vectors.
define <8 x i8> @add_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
-; CHECK-LABEL: @add_v8i8
+; CHECK-LABEL: add_v8i8:
; CHECK: add v0.8b, v0.8b, v1.8b
; CHECK: ret
%res = add <8 x i8> %op1, %op2
@@ -36,7 +40,7 @@ define <8 x i8> @add_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <16 x i8> @add_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
-; CHECK-LABEL: @add_v16i8
+; CHECK-LABEL: add_v16i8:
; CHECK: add v0.16b, v0.16b, v1.16b
; CHECK: ret
%res = add <16 x i8> %op1, %op2
@@ -44,7 +48,7 @@ define <16 x i8> @add_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
}
define void @add_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
-; CHECK-LABEL: @add_v32i8
+; CHECK-LABEL: add_v32i8:
; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,32)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -59,7 +63,7 @@ define void @add_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
}
define void @add_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
-; CHECK-LABEL: @add_v64i8
+; CHECK-LABEL: add_v64i8:
; CHECK-DAG: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,64)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -79,7 +83,7 @@ define void @add_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
}
define void @add_v128i8(<128 x i8>* %a, <128 x i8>* %b) #0 {
-; CHECK-LABEL: @add_v128i8
+; CHECK-LABEL: add_v128i8:
; CHECK-DAG: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,128)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -109,7 +113,7 @@ define void @add_v128i8(<128 x i8>* %a, <128 x i8>* %b) #0 {
}
define void @add_v256i8(<256 x i8>* %a, <256 x i8>* %b) #0 {
-; CHECK-LABEL: @add_v256i8
+; CHECK-LABEL: add_v256i8:
; CHECK-DAG: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,256)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -160,7 +164,7 @@ define void @add_v256i8(<256 x i8>* %a, <256 x i8>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <4 x i16> @add_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
-; CHECK-LABEL: @add_v4i16
+; CHECK-LABEL: add_v4i16:
; CHECK: add v0.4h, v0.4h, v1.4h
; CHECK: ret
%res = add <4 x i16> %op1, %op2
@@ -169,7 +173,7 @@ define <4 x i16> @add_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <8 x i16> @add_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
-; CHECK-LABEL: @add_v8i16
+; CHECK-LABEL: add_v8i16:
; CHECK: add v0.8h, v0.8h, v1.8h
; CHECK: ret
%res = add <8 x i16> %op1, %op2
@@ -177,7 +181,7 @@ define <8 x i16> @add_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
}
define void @add_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
-; CHECK-LABEL: @add_v16i16
+; CHECK-LABEL: add_v16i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),16)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -194,7 +198,7 @@ define void @add_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the add_v#i8 tests
; already cover the general legalisation cases.
define void @add_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 {
-; CHECK-LABEL: @add_v32i16
+; CHECK-LABEL: add_v32i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),32)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -211,7 +215,7 @@ define void @add_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the add_v#i8 tests
; already cover the general legalisation cases.
define void @add_v64i16(<64 x i16>* %a, <64 x i16>* %b) #0 {
-; CHECK-LABEL: @add_v64i16
+; CHECK-LABEL: add_v64i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),64)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -228,7 +232,7 @@ define void @add_v64i16(<64 x i16>* %a, <64 x i16>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the add_v#i8 tests
; already cover the general legalisation cases.
define void @add_v128i16(<128 x i16>* %a, <128 x i16>* %b) #0 {
-; CHECK-LABEL: @add_v128i16
+; CHECK-LABEL: add_v128i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),128)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -244,7 +248,7 @@ define void @add_v128i16(<128 x i16>* %a, <128 x i16>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <2 x i32> @add_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
-; CHECK-LABEL: @add_v2i32
+; CHECK-LABEL: add_v2i32:
; CHECK: add v0.2s, v0.2s, v1.2s
; CHECK: ret
%res = add <2 x i32> %op1, %op2
@@ -253,7 +257,7 @@ define <2 x i32> @add_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <4 x i32> @add_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
-; CHECK-LABEL: @add_v4i32
+; CHECK-LABEL: add_v4i32:
; CHECK: add v0.4s, v0.4s, v1.4s
; CHECK: ret
%res = add <4 x i32> %op1, %op2
@@ -261,7 +265,7 @@ define <4 x i32> @add_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
}
define void @add_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
-; CHECK-LABEL: @add_v8i32
+; CHECK-LABEL: add_v8i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -278,7 +282,7 @@ define void @add_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the add_v#i8 tests
; already cover the general legalisation cases.
define void @add_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
-; CHECK-LABEL: @add_v16i32
+; CHECK-LABEL: add_v16i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -295,7 +299,7 @@ define void @add_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the add_v#i8 tests
; already cover the general legalisation cases.
define void @add_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
-; CHECK-LABEL: @add_v32i32
+; CHECK-LABEL: add_v32i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -312,7 +316,7 @@ define void @add_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the add_v#i8 tests
; already cover the general legalisation cases.
define void @add_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
-; CHECK-LABEL: @add_v64i32
+; CHECK-LABEL: add_v64i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -328,7 +332,7 @@ define void @add_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <1 x i64> @add_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
-; CHECK-LABEL: @add_v1i64
+; CHECK-LABEL: add_v1i64:
; CHECK: add d0, d0, d1
; CHECK: ret
%res = add <1 x i64> %op1, %op2
@@ -337,7 +341,7 @@ define <1 x i64> @add_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <2 x i64> @add_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
-; CHECK-LABEL: @add_v2i64
+; CHECK-LABEL: add_v2i64:
; CHECK: add v0.2d, v0.2d, v1.2d
; CHECK: ret
%res = add <2 x i64> %op1, %op2
@@ -345,7 +349,7 @@ define <2 x i64> @add_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
}
define void @add_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
-; CHECK-LABEL: @add_v4i64
+; CHECK-LABEL: add_v4i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -362,7 +366,7 @@ define void @add_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the add_v#i8 tests
; already cover the general legalisation cases.
define void @add_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
-; CHECK-LABEL: @add_v8i64
+; CHECK-LABEL: add_v8i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -379,7 +383,7 @@ define void @add_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the add_v#i8 tests
; already cover the general legalisation cases.
define void @add_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
-; CHECK-LABEL: @add_v16i64
+; CHECK-LABEL: add_v16i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -396,7 +400,7 @@ define void @add_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the add_v#i8 tests
; already cover the general legalisation cases.
define void @add_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
-; CHECK-LABEL: @add_v32i64
+; CHECK-LABEL: add_v32i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -415,9 +419,13 @@ define void @add_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
; VBYTES because the add tests already validate the legalisation code paths.
;
+;
+; MUL
+;
+
; Don't use SVE for 64-bit vectors.
define <8 x i8> @mul_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
-; CHECK-LABEL: @mul_v8i8
+; CHECK-LABEL: mul_v8i8:
; CHECK: mul v0.8b, v0.8b, v1.8b
; CHECK: ret
%res = mul <8 x i8> %op1, %op2
@@ -426,7 +434,7 @@ define <8 x i8> @mul_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <16 x i8> @mul_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
-; CHECK-LABEL: @mul_v16i8
+; CHECK-LABEL: mul_v16i8:
; CHECK: mul v0.16b, v0.16b, v1.16b
; CHECK: ret
%res = mul <16 x i8> %op1, %op2
@@ -434,7 +442,7 @@ define <16 x i8> @mul_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
}
define void @mul_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
-; CHECK-LABEL: @mul_v32i8
+; CHECK-LABEL: mul_v32i8:
; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,32)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -449,7 +457,7 @@ define void @mul_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
}
define void @mul_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
-; CHECK-LABEL: @mul_v64i8
+; CHECK-LABEL: mul_v64i8:
; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,64)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -464,7 +472,7 @@ define void @mul_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
}
define void @mul_v128i8(<128 x i8>* %a, <128 x i8>* %b) #0 {
-; CHECK-LABEL: @mul_v128i8
+; CHECK-LABEL: mul_v128i8:
; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,128)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -479,7 +487,7 @@ define void @mul_v128i8(<128 x i8>* %a, <128 x i8>* %b) #0 {
}
define void @mul_v256i8(<256 x i8>* %a, <256 x i8>* %b) #0 {
-; CHECK-LABEL: @mul_v256i8
+; CHECK-LABEL: mul_v256i8:
; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,256)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -495,7 +503,7 @@ define void @mul_v256i8(<256 x i8>* %a, <256 x i8>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <4 x i16> @mul_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
-; CHECK-LABEL: @mul_v4i16
+; CHECK-LABEL: mul_v4i16:
; CHECK: mul v0.4h, v0.4h, v1.4h
; CHECK: ret
%res = mul <4 x i16> %op1, %op2
@@ -504,7 +512,7 @@ define <4 x i16> @mul_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <8 x i16> @mul_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
-; CHECK-LABEL: @mul_v8i16
+; CHECK-LABEL: mul_v8i16:
; CHECK: mul v0.8h, v0.8h, v1.8h
; CHECK: ret
%res = mul <8 x i16> %op1, %op2
@@ -512,7 +520,7 @@ define <8 x i16> @mul_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
}
define void @mul_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
-; CHECK-LABEL: @mul_v16i16
+; CHECK-LABEL: mul_v16i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),16)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -527,7 +535,7 @@ define void @mul_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
}
define void @mul_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 {
-; CHECK-LABEL: @mul_v32i16
+; CHECK-LABEL: mul_v32i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),32)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -542,7 +550,7 @@ define void @mul_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 {
}
define void @mul_v64i16(<64 x i16>* %a, <64 x i16>* %b) #0 {
-; CHECK-LABEL: @mul_v64i16
+; CHECK-LABEL: mul_v64i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),64)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -557,7 +565,7 @@ define void @mul_v64i16(<64 x i16>* %a, <64 x i16>* %b) #0 {
}
define void @mul_v128i16(<128 x i16>* %a, <128 x i16>* %b) #0 {
-; CHECK-LABEL: @mul_v128i16
+; CHECK-LABEL: mul_v128i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),128)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -573,7 +581,7 @@ define void @mul_v128i16(<128 x i16>* %a, <128 x i16>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <2 x i32> @mul_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
-; CHECK-LABEL: @mul_v2i32
+; CHECK-LABEL: mul_v2i32:
; CHECK: mul v0.2s, v0.2s, v1.2s
; CHECK: ret
%res = mul <2 x i32> %op1, %op2
@@ -582,7 +590,7 @@ define <2 x i32> @mul_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <4 x i32> @mul_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
-; CHECK-LABEL: @mul_v4i32
+; CHECK-LABEL: mul_v4i32:
; CHECK: mul v0.4s, v0.4s, v1.4s
; CHECK: ret
%res = mul <4 x i32> %op1, %op2
@@ -590,7 +598,7 @@ define <4 x i32> @mul_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
}
define void @mul_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
-; CHECK-LABEL: @mul_v8i32
+; CHECK-LABEL: mul_v8i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -605,7 +613,7 @@ define void @mul_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
}
define void @mul_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
-; CHECK-LABEL: @mul_v16i32
+; CHECK-LABEL: mul_v16i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -620,7 +628,7 @@ define void @mul_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
}
define void @mul_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
-; CHECK-LABEL: @mul_v32i32
+; CHECK-LABEL: mul_v32i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -635,7 +643,7 @@ define void @mul_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
}
define void @mul_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
-; CHECK-LABEL: @mul_v64i32
+; CHECK-LABEL: mul_v64i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -651,7 +659,7 @@ define void @mul_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
; Vector i64 multiplications are not legal for NEON so use SVE when available.
define <1 x i64> @mul_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
-; CHECK-LABEL: @mul_v1i64
+; CHECK-LABEL: mul_v1i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl1
; CHECK: mul z0.d, [[PG]]/m, z0.d, z1.d
; CHECK: ret
@@ -661,7 +669,7 @@ define <1 x i64> @mul_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
; Vector i64 multiplications are not legal for NEON so use SVE when available.
define <2 x i64> @mul_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
-; CHECK-LABEL: @mul_v2i64
+; CHECK-LABEL: mul_v2i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl2
; CHECK: mul z0.d, [[PG]]/m, z0.d, z1.d
; CHECK: ret
@@ -670,7 +678,7 @@ define <2 x i64> @mul_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
}
define void @mul_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
-; CHECK-LABEL: @mul_v4i64
+; CHECK-LABEL: mul_v4i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -685,7 +693,7 @@ define void @mul_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
}
define void @mul_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
-; CHECK-LABEL: @mul_v8i64
+; CHECK-LABEL: mul_v8i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -700,7 +708,7 @@ define void @mul_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
}
define void @mul_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
-; CHECK-LABEL: @mul_v16i64
+; CHECK-LABEL: mul_v16i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -715,7 +723,7 @@ define void @mul_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
}
define void @mul_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
-; CHECK-LABEL: @mul_v32i64
+; CHECK-LABEL: mul_v32i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll
index 7c1095b92009..0833ed53a932 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll
@@ -25,9 +25,13 @@ target triple = "aarch64-unknown-linux-gnu"
; Don't use SVE when its registers are no bigger than NEON.
; NO_SVE-NOT: ptrue
+;
+; AND
+;
+
; Don't use SVE for 64-bit vectors.
define <8 x i8> @and_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
-; CHECK-LABEL: @and_v8i8
+; CHECK-LABEL: and_v8i8:
; CHECK: and v0.8b, v0.8b, v1.8b
; CHECK: ret
%res = and <8 x i8> %op1, %op2
@@ -36,7 +40,7 @@ define <8 x i8> @and_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <16 x i8> @and_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
-; CHECK-LABEL: @and_v16i8
+; CHECK-LABEL: and_v16i8:
; CHECK: and v0.16b, v0.16b, v1.16b
; CHECK: ret
%res = and <16 x i8> %op1, %op2
@@ -44,7 +48,7 @@ define <16 x i8> @and_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
}
define void @and_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
-; CHECK-LABEL: @and_v32i8
+; CHECK-LABEL: and_v32i8:
; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,32)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -59,7 +63,7 @@ define void @and_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
}
define void @and_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
-; CHECK-LABEL: @and_v64i8
+; CHECK-LABEL: and_v64i8:
; CHECK-DAG: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,64)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -79,7 +83,7 @@ define void @and_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
}
define void @and_v128i8(<128 x i8>* %a, <128 x i8>* %b) #0 {
-; CHECK-LABEL: @and_v128i8
+; CHECK-LABEL: and_v128i8:
; CHECK-DAG: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,128)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -109,7 +113,7 @@ define void @and_v128i8(<128 x i8>* %a, <128 x i8>* %b) #0 {
}
define void @and_v256i8(<256 x i8>* %a, <256 x i8>* %b) #0 {
-; CHECK-LABEL: @and_v256i8
+; CHECK-LABEL: and_v256i8:
; CHECK-DAG: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,256)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -160,7 +164,7 @@ define void @and_v256i8(<256 x i8>* %a, <256 x i8>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <4 x i16> @and_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
-; CHECK-LABEL: @and_v4i16
+; CHECK-LABEL: and_v4i16:
; CHECK: and v0.8b, v0.8b, v1.8b
; CHECK: ret
%res = and <4 x i16> %op1, %op2
@@ -169,7 +173,7 @@ define <4 x i16> @and_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <8 x i16> @and_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
-; CHECK-LABEL: @and_v8i16
+; CHECK-LABEL: and_v8i16:
; CHECK: and v0.16b, v0.16b, v1.16b
; CHECK: ret
%res = and <8 x i16> %op1, %op2
@@ -177,7 +181,7 @@ define <8 x i16> @and_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
}
define void @and_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
-; CHECK-LABEL: @and_v16i16
+; CHECK-LABEL: and_v16i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),16)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -194,7 +198,7 @@ define void @and_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the and_v#i8 tests
; already cover the general legalisation cases.
define void @and_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 {
-; CHECK-LABEL: @and_v32i16
+; CHECK-LABEL: and_v32i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),32)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -211,7 +215,7 @@ define void @and_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the and_v#i8 tests
; already cover the general legalisation cases.
define void @and_v64i16(<64 x i16>* %a, <64 x i16>* %b) #0 {
-; CHECK-LABEL: @and_v64i16
+; CHECK-LABEL: and_v64i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),64)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -228,7 +232,7 @@ define void @and_v64i16(<64 x i16>* %a, <64 x i16>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the and_v#i8 tests
; already cover the general legalisation cases.
define void @and_v128i16(<128 x i16>* %a, <128 x i16>* %b) #0 {
-; CHECK-LABEL: @and_v128i16
+; CHECK-LABEL: and_v128i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),128)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -244,7 +248,7 @@ define void @and_v128i16(<128 x i16>* %a, <128 x i16>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <2 x i32> @and_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
-; CHECK-LABEL: @and_v2i32
+; CHECK-LABEL: and_v2i32:
; CHECK: and v0.8b, v0.8b, v1.8b
; CHECK: ret
%res = and <2 x i32> %op1, %op2
@@ -253,7 +257,7 @@ define <2 x i32> @and_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <4 x i32> @and_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
-; CHECK-LABEL: @and_v4i32
+; CHECK-LABEL: and_v4i32:
; CHECK: and v0.16b, v0.16b, v1.16b
; CHECK: ret
%res = and <4 x i32> %op1, %op2
@@ -261,7 +265,7 @@ define <4 x i32> @and_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
}
define void @and_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
-; CHECK-LABEL: @and_v8i32
+; CHECK-LABEL: and_v8i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -278,7 +282,7 @@ define void @and_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the and_v#i8 tests
; already cover the general legalisation cases.
define void @and_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
-; CHECK-LABEL: @and_v16i32
+; CHECK-LABEL: and_v16i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -295,7 +299,7 @@ define void @and_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the and_v#i8 tests
; already cover the general legalisation cases.
define void @and_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
-; CHECK-LABEL: @and_v32i32
+; CHECK-LABEL: and_v32i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -312,7 +316,7 @@ define void @and_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the and_v#i8 tests
; already cover the general legalisation cases.
define void @and_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
-; CHECK-LABEL: @and_v64i32
+; CHECK-LABEL: and_v64i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -328,7 +332,7 @@ define void @and_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <1 x i64> @and_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
-; CHECK-LABEL: @and_v1i64
+; CHECK-LABEL: and_v1i64:
; CHECK: and v0.8b, v0.8b, v1.8b
; CHECK: ret
%res = and <1 x i64> %op1, %op2
@@ -337,7 +341,7 @@ define <1 x i64> @and_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <2 x i64> @and_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
-; CHECK-LABEL: @and_v2i64
+; CHECK-LABEL: and_v2i64:
; CHECK: and v0.16b, v0.16b, v1.16b
; CHECK: ret
%res = and <2 x i64> %op1, %op2
@@ -345,7 +349,7 @@ define <2 x i64> @and_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
}
define void @and_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
-; CHECK-LABEL: @and_v4i64
+; CHECK-LABEL: and_v4i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -362,7 +366,7 @@ define void @and_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the and_v#i8 tests
; already cover the general legalisation cases.
define void @and_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
-; CHECK-LABEL: @and_v8i64
+; CHECK-LABEL: and_v8i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -379,7 +383,7 @@ define void @and_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the and_v#i8 tests
; already cover the general legalisation cases.
define void @and_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
-; CHECK-LABEL: @and_v16i64
+; CHECK-LABEL: and_v16i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -396,7 +400,7 @@ define void @and_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
; NOTE: Check lines only cover the first VBYTES because the and_v#i8 tests
; already cover the general legalisation cases.
define void @and_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
-; CHECK-LABEL: @and_v32i64
+; CHECK-LABEL: and_v32i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -415,9 +419,13 @@ define void @and_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
; VBYTES because the and tests already validate the legalisation code paths.
;
+;
+; OR
+;
+
; Don't use SVE for 64-bit vectors.
define <8 x i8> @or_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
-; CHECK-LABEL: @or_v8i8
+; CHECK-LABEL: or_v8i8:
; CHECK: orr v0.8b, v0.8b, v1.8b
; CHECK: ret
%res = or <8 x i8> %op1, %op2
@@ -426,7 +434,7 @@ define <8 x i8> @or_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <16 x i8> @or_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
-; CHECK-LABEL: @or_v16i8
+; CHECK-LABEL: or_v16i8:
; CHECK: orr v0.16b, v0.16b, v1.16b
; CHECK: ret
%res = or <16 x i8> %op1, %op2
@@ -434,7 +442,7 @@ define <16 x i8> @or_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
}
define void @or_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
-; CHECK-LABEL: @or_v32i8
+; CHECK-LABEL: or_v32i8:
; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,32)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -449,7 +457,7 @@ define void @or_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
}
define void @or_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
-; CHECK-LABEL: @or_v64i8
+; CHECK-LABEL: or_v64i8:
; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,64)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -464,7 +472,7 @@ define void @or_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
}
define void @or_v128i8(<128 x i8>* %a, <128 x i8>* %b) #0 {
-; CHECK-LABEL: @or_v128i8
+; CHECK-LABEL: or_v128i8:
; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,128)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -479,7 +487,7 @@ define void @or_v128i8(<128 x i8>* %a, <128 x i8>* %b) #0 {
}
define void @or_v256i8(<256 x i8>* %a, <256 x i8>* %b) #0 {
-; CHECK-LABEL: @or_v256i8
+; CHECK-LABEL: or_v256i8:
; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,256)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -495,7 +503,7 @@ define void @or_v256i8(<256 x i8>* %a, <256 x i8>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <4 x i16> @or_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
-; CHECK-LABEL: @or_v4i16
+; CHECK-LABEL: or_v4i16:
; CHECK: orr v0.8b, v0.8b, v1.8b
; CHECK: ret
%res = or <4 x i16> %op1, %op2
@@ -504,7 +512,7 @@ define <4 x i16> @or_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <8 x i16> @or_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
-; CHECK-LABEL: @or_v8i16
+; CHECK-LABEL: or_v8i16:
; CHECK: orr v0.16b, v0.16b, v1.16b
; CHECK: ret
%res = or <8 x i16> %op1, %op2
@@ -512,7 +520,7 @@ define <8 x i16> @or_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
}
define void @or_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
-; CHECK-LABEL: @or_v16i16
+; CHECK-LABEL: or_v16i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),16)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -527,7 +535,7 @@ define void @or_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
}
define void @or_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 {
-; CHECK-LABEL: @or_v32i16
+; CHECK-LABEL: or_v32i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),32)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -542,7 +550,7 @@ define void @or_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 {
}
define void @or_v64i16(<64 x i16>* %a, <64 x i16>* %b) #0 {
-; CHECK-LABEL: @or_v64i16
+; CHECK-LABEL: or_v64i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),64)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -557,7 +565,7 @@ define void @or_v64i16(<64 x i16>* %a, <64 x i16>* %b) #0 {
}
define void @or_v128i16(<128 x i16>* %a, <128 x i16>* %b) #0 {
-; CHECK-LABEL: @or_v128i16
+; CHECK-LABEL: or_v128i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),128)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -573,7 +581,7 @@ define void @or_v128i16(<128 x i16>* %a, <128 x i16>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <2 x i32> @or_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
-; CHECK-LABEL: @or_v2i32
+; CHECK-LABEL: or_v2i32:
; CHECK: orr v0.8b, v0.8b, v1.8b
; CHECK: ret
%res = or <2 x i32> %op1, %op2
@@ -582,7 +590,7 @@ define <2 x i32> @or_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <4 x i32> @or_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
-; CHECK-LABEL: @or_v4i32
+; CHECK-LABEL: or_v4i32:
; CHECK: orr v0.16b, v0.16b, v1.16b
; CHECK: ret
%res = or <4 x i32> %op1, %op2
@@ -590,7 +598,7 @@ define <4 x i32> @or_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
}
define void @or_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
-; CHECK-LABEL: @or_v8i32
+; CHECK-LABEL: or_v8i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -605,7 +613,7 @@ define void @or_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
}
define void @or_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
-; CHECK-LABEL: @or_v16i32
+; CHECK-LABEL: or_v16i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -620,7 +628,7 @@ define void @or_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
}
define void @or_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
-; CHECK-LABEL: @or_v32i32
+; CHECK-LABEL: or_v32i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -635,7 +643,7 @@ define void @or_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
}
define void @or_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
-; CHECK-LABEL: @or_v64i32
+; CHECK-LABEL: or_v64i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -651,7 +659,7 @@ define void @or_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <1 x i64> @or_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
-; CHECK-LABEL: @or_v1i64
+; CHECK-LABEL: or_v1i64:
; CHECK: orr v0.8b, v0.8b, v1.8b
; CHECK: ret
%res = or <1 x i64> %op1, %op2
@@ -660,7 +668,7 @@ define <1 x i64> @or_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <2 x i64> @or_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
-; CHECK-LABEL: @or_v2i64
+; CHECK-LABEL: or_v2i64:
; CHECK: orr v0.16b, v0.16b, v1.16b
; CHECK: ret
%res = or <2 x i64> %op1, %op2
@@ -668,7 +676,7 @@ define <2 x i64> @or_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
}
define void @or_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
-; CHECK-LABEL: @or_v4i64
+; CHECK-LABEL: or_v4i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -683,7 +691,7 @@ define void @or_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
}
define void @or_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
-; CHECK-LABEL: @or_v8i64
+; CHECK-LABEL: or_v8i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -698,7 +706,7 @@ define void @or_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
}
define void @or_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
-; CHECK-LABEL: @or_v16i64
+; CHECK-LABEL: or_v16i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -713,7 +721,7 @@ define void @or_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
}
define void @or_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
-; CHECK-LABEL: @or_v32i64
+; CHECK-LABEL: or_v32i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -727,9 +735,13 @@ define void @or_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
ret void
}
+;
+; XOR
+;
+
; Don't use SVE for 64-bit vectors.
define <8 x i8> @xor_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
-; CHECK-LABEL: @xor_v8i8
+; CHECK-LABEL: xor_v8i8:
; CHECK: eor v0.8b, v0.8b, v1.8b
; CHECK: ret
%res = xor <8 x i8> %op1, %op2
@@ -738,7 +750,7 @@ define <8 x i8> @xor_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <16 x i8> @xor_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
-; CHECK-LABEL: @xor_v16i8
+; CHECK-LABEL: xor_v16i8:
; CHECK: eor v0.16b, v0.16b, v1.16b
; CHECK: ret
%res = xor <16 x i8> %op1, %op2
@@ -746,7 +758,7 @@ define <16 x i8> @xor_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
}
define void @xor_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
-; CHECK-LABEL: @xor_v32i8
+; CHECK-LABEL: xor_v32i8:
; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,32)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -761,7 +773,7 @@ define void @xor_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 {
}
define void @xor_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
-; CHECK-LABEL: @xor_v64i8
+; CHECK-LABEL: xor_v64i8:
; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,64)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -776,7 +788,7 @@ define void @xor_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
}
define void @xor_v128i8(<128 x i8>* %a, <128 x i8>* %b) #0 {
-; CHECK-LABEL: @xor_v128i8
+; CHECK-LABEL: xor_v128i8:
; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,128)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -791,7 +803,7 @@ define void @xor_v128i8(<128 x i8>* %a, <128 x i8>* %b) #0 {
}
define void @xor_v256i8(<256 x i8>* %a, <256 x i8>* %b) #0 {
-; CHECK-LABEL: @xor_v256i8
+; CHECK-LABEL: xor_v256i8:
; CHECK: ptrue [[PG:p[0-9]+]].b, vl[[#min(VBYTES,256)]]
; CHECK-DAG: ld1b { [[OP1:z[0-9]+]].b }, [[PG]]/z, [x0]
; CHECK-DAG: ld1b { [[OP2:z[0-9]+]].b }, [[PG]]/z, [x1]
@@ -807,7 +819,7 @@ define void @xor_v256i8(<256 x i8>* %a, <256 x i8>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <4 x i16> @xor_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
-; CHECK-LABEL: @xor_v4i16
+; CHECK-LABEL: xor_v4i16:
; CHECK: eor v0.8b, v0.8b, v1.8b
; CHECK: ret
%res = xor <4 x i16> %op1, %op2
@@ -816,7 +828,7 @@ define <4 x i16> @xor_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <8 x i16> @xor_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
-; CHECK-LABEL: @xor_v8i16
+; CHECK-LABEL: xor_v8i16:
; CHECK: eor v0.16b, v0.16b, v1.16b
; CHECK: ret
%res = xor <8 x i16> %op1, %op2
@@ -824,7 +836,7 @@ define <8 x i16> @xor_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
}
define void @xor_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
-; CHECK-LABEL: @xor_v16i16
+; CHECK-LABEL: xor_v16i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),16)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -839,7 +851,7 @@ define void @xor_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 {
}
define void @xor_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 {
-; CHECK-LABEL: @xor_v32i16
+; CHECK-LABEL: xor_v32i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),32)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -854,7 +866,7 @@ define void @xor_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 {
}
define void @xor_v64i16(<64 x i16>* %a, <64 x i16>* %b) #0 {
-; CHECK-LABEL: @xor_v64i16
+; CHECK-LABEL: xor_v64i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),64)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -869,7 +881,7 @@ define void @xor_v64i16(<64 x i16>* %a, <64 x i16>* %b) #0 {
}
define void @xor_v128i16(<128 x i16>* %a, <128 x i16>* %b) #0 {
-; CHECK-LABEL: @xor_v128i16
+; CHECK-LABEL: xor_v128i16:
; CHECK: ptrue [[PG:p[0-9]+]].h, vl[[#min(div(VBYTES,2),128)]]
; CHECK-DAG: ld1h { [[OP1:z[0-9]+]].h }, [[PG]]/z, [x0]
; CHECK-DAG: ld1h { [[OP2:z[0-9]+]].h }, [[PG]]/z, [x1]
@@ -885,7 +897,7 @@ define void @xor_v128i16(<128 x i16>* %a, <128 x i16>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <2 x i32> @xor_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
-; CHECK-LABEL: @xor_v2i32
+; CHECK-LABEL: xor_v2i32:
; CHECK: eor v0.8b, v0.8b, v1.8b
; CHECK: ret
%res = xor <2 x i32> %op1, %op2
@@ -894,7 +906,7 @@ define <2 x i32> @xor_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <4 x i32> @xor_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
-; CHECK-LABEL: @xor_v4i32
+; CHECK-LABEL: xor_v4i32:
; CHECK: eor v0.16b, v0.16b, v1.16b
; CHECK: ret
%res = xor <4 x i32> %op1, %op2
@@ -902,7 +914,7 @@ define <4 x i32> @xor_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
}
define void @xor_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
-; CHECK-LABEL: @xor_v8i32
+; CHECK-LABEL: xor_v8i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),8)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -917,7 +929,7 @@ define void @xor_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 {
}
define void @xor_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
-; CHECK-LABEL: @xor_v16i32
+; CHECK-LABEL: xor_v16i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),16)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -932,7 +944,7 @@ define void @xor_v16i32(<16 x i32>* %a, <16 x i32>* %b) #0 {
}
define void @xor_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
-; CHECK-LABEL: @xor_v32i32
+; CHECK-LABEL: xor_v32i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),32)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -947,7 +959,7 @@ define void @xor_v32i32(<32 x i32>* %a, <32 x i32>* %b) #0 {
}
define void @xor_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
-; CHECK-LABEL: @xor_v64i32
+; CHECK-LABEL: xor_v64i32:
; CHECK: ptrue [[PG:p[0-9]+]].s, vl[[#min(div(VBYTES,4),64)]]
; CHECK-DAG: ld1w { [[OP1:z[0-9]+]].s }, [[PG]]/z, [x0]
; CHECK-DAG: ld1w { [[OP2:z[0-9]+]].s }, [[PG]]/z, [x1]
@@ -963,7 +975,7 @@ define void @xor_v64i32(<64 x i32>* %a, <64 x i32>* %b) #0 {
; Don't use SVE for 64-bit vectors.
define <1 x i64> @xor_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
-; CHECK-LABEL: @xor_v1i64
+; CHECK-LABEL: xor_v1i64:
; CHECK: eor v0.8b, v0.8b, v1.8b
; CHECK: ret
%res = xor <1 x i64> %op1, %op2
@@ -972,7 +984,7 @@ define <1 x i64> @xor_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
; Don't use SVE for 128-bit vectors.
define <2 x i64> @xor_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
-; CHECK-LABEL: @xor_v2i64
+; CHECK-LABEL: xor_v2i64:
; CHECK: eor v0.16b, v0.16b, v1.16b
; CHECK: ret
%res = xor <2 x i64> %op1, %op2
@@ -980,7 +992,7 @@ define <2 x i64> @xor_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
}
define void @xor_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
-; CHECK-LABEL: @xor_v4i64
+; CHECK-LABEL: xor_v4i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),4)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -995,7 +1007,7 @@ define void @xor_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 {
}
define void @xor_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
-; CHECK-LABEL: @xor_v8i64
+; CHECK-LABEL: xor_v8i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),8)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -1010,7 +1022,7 @@ define void @xor_v8i64(<8 x i64>* %a, <8 x i64>* %b) #0 {
}
define void @xor_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
-; CHECK-LABEL: @xor_v16i64
+; CHECK-LABEL: xor_v16i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),16)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
@@ -1025,7 +1037,7 @@ define void @xor_v16i64(<16 x i64>* %a, <16 x i64>* %b) #0 {
}
define void @xor_v32i64(<32 x i64>* %a, <32 x i64>* %b) #0 {
-; CHECK-LABEL: @xor_v32i64
+; CHECK-LABEL: xor_v32i64:
; CHECK: ptrue [[PG:p[0-9]+]].d, vl[[#min(div(VBYTES,8),32)]]
; CHECK-DAG: ld1d { [[OP1:z[0-9]+]].d }, [[PG]]/z, [x0]
; CHECK-DAG: ld1d { [[OP2:z[0-9]+]].d }, [[PG]]/z, [x1]
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