[llvm] 9533f0e - AMDGPU/GlobalISel: Use nicer form of buildInstr

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-08-10T08:41:07-04:00
New Revision: 9533f0ea68266b0c7c7ba2bed1d4ae410ce23f36

URL: https://github.com/llvm/llvm-project/commit/9533f0ea68266b0c7c7ba2bed1d4ae410ce23f36
DIFF: https://github.com/llvm/llvm-project/commit/9533f0ea68266b0c7c7ba2bed1d4ae410ce23f36.diff

LOG: AMDGPU/GlobalISel: Use nicer form of buildInstr

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 2c15967cb469..bb6c13a4f430 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -2319,15 +2319,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
 
     setRegsToType(MRI, DefRegs, HalfTy);
 
-    B.buildInstr(Opc)
-      .addDef(DefRegs[0])
-      .addUse(Src0Regs[0])
-      .addUse(Src1Regs[0]);
-
-    B.buildInstr(Opc)
-      .addDef(DefRegs[1])
-      .addUse(Src0Regs[1])
-      .addUse(Src1Regs[1]);
+    B.buildInstr(Opc, {DefRegs[0]}, {Src0Regs[0], Src1Regs[0]});
+    B.buildInstr(Opc, {DefRegs[1]}, {Src0Regs[1], Src1Regs[1]});
 
     MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank);
     MI.eraseFromParent();