[PATCH] D85069: [RISCV] add the MC layer support of riscv vector Zvamo extension

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added a comment.

In D85069#2204470 <https://reviews.llvm.org/D85069#2204470>, @StephenFan wrote:

> In D85069#2201754 <https://reviews.llvm.org/D85069#2201754>, @HsiangKai wrote:
>
>> I confused the relationship of sub-extensions before. Sorry for that.
>> There are some discussions[0] about the relationship between vector sub-extensions. It seems that

>>
>> V-extension implies Zvamo + Zvlsseg
>>
>> Zvqmac, Zvamo and Zvlsseg are stand alone sub extensions. That is, Zvamo does not imply V extension.
>>
>> Zvqmac has no implied extensions.
>> Zvamo implies A-extension.
>> Zvlsseg has no implied extensions.
>>
>> Do you agree with that?
>>
>> [0] https://github.com/riscv/riscv-v-spec/issues/546
>
> So, let me summarize:
> Zvlsseg has no implied extensions
> Zvqmac has no implied extensions
> Zvamo required A extension ? If so, is it suitable that use -mattr=+a, +experimental-zvamo to enable the zvamo extension?

Currently, FeatureStdExtV is the base V instructions. So, I will suggest the following relationships

Zvamo -> V (Does Zvamo -> A? I create an issue about it. https://github.com/riscv/riscv-v-spec/issues/555)
Zvqmac -> V
Zvlsseg -> V

The implementation looks like

def FeatureExtZvamo

  : SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true",
                     "'Zvamo'(Vector AMO Operations)",
                     [FeatureStdExtV]>;

def FeatureExtZvqmac

  : SubtargetFeature<"experimental-zvqmac", "HasStdExtZvqmac", "true",
                     "'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)",
                     [FeatureStdExtV]>;

def FeatureStdExtZvlsseg

  : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
                     "'Zvlsseg' (Vector segment load/store instructions)”,
                     [FeatureStdExtV]>;

In the future, “current V” may be changed to Zvbase in the specification. And “new V” will imply Zvbase + Zvamo + Zvlsseg. As described in https://github.com/riscv/riscv-v-spec/issues/547#issuecomment-670667964.


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