[PATCH] D85546: [SVE] Add ISD nodes for integer extend inreg operations.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.h:100
+  UXTH_MERGE_PASSTHRU,
+  UXTW_MERGE_PASSTHRU,
+
----------------
paulwalker-arm wrote:
> efriedma wrote:
> > The signed versions are essentially predicated versions of ISD::SIGN_EXTEND_INREG?  Can we use names that reflect that?
> It is more than a rename but I can do that, it might even allow an easier path to lowering for scalable vector types.  I do want the signed and unsigned variants to be consistent though. So, any objections to me creating a matching predicated zero_extend_inreg?
That's fine.  We actually have a function on SelectionDAG called getZeroExtendInReg(), so that isn't completely new terminology.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85546/new/

https://reviews.llvm.org/D85546