[llvm] 98eccec - [PowerPC] Add Vector Extract/Expand/Count with Mask, Move to VSR Mask Instruction Definitions and MC Tests
Amy Kwan via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 7 09:06:28 PDT 2020
Author: Amy Kwan
Date: 2020-08-07T11:02:08-05:00
New Revision: 98eccec3ae3e6bd9b6ecd7a132d936c9d70893d1
URL: https://github.com/llvm/llvm-project/commit/98eccec3ae3e6bd9b6ecd7a132d936c9d70893d1
DIFF: https://github.com/llvm/llvm-project/commit/98eccec3ae3e6bd9b6ecd7a132d936c9d70893d1.diff
LOG: [PowerPC] Add Vector Extract/Expand/Count with Mask, Move to VSR Mask Instruction Definitions and MC Tests
This patch adds the instruction definitions and assembly/disassembly tests for
the following set of instructions:
Vector Extract [byte | half | word | doubleword | quad] with mask
Vector Expand [byte | half | word | doubleword | quad] with mask
Move to VSR [byte | byte immediate | half | word | doubleword | quad] with mask
Vector Count Mask Bits [byte | half | word | doubleword]
Differential Revision: https://reviews.llvm.org/D83724
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 1eed58dfbbb79..cb2997a04ef7f 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -326,6 +326,22 @@ class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr,
let Inst{26-31} = xo;
}
+class VXForm_RD5_MP_VB5<bits<11> xo, bits<4> eo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin, list<dag> pattern>
+ : I<4, OOL, IOL, asmstr, itin> {
+ bits<5> RD;
+ bits<5> VB;
+ bit MP;
+
+ let Pattern = pattern;
+
+ let Inst{6-10} = RD;
+ let Inst{11-14} = eo;
+ let Inst{15} = MP;
+ let Inst{16-20} = VB;
+ let Inst{21-31} = xo;
+}
+
// 8RR:D-Form: [ 1 1 0 // // imm0
// PO T XO TX imm1 ].
class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
@@ -947,6 +963,70 @@ let Predicates = [IsISA3_1] in {
[(set v2i64:$vD,
(int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA, i64:$rB))]>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$rD), (ins vrrc:$vB),
+ "vextractbm $rD, $vB", IIC_VecGeneral,
+ []>;
+ def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$rD), (ins vrrc:$vB),
+ "vextracthm $rD, $vB", IIC_VecGeneral,
+ []>;
+ def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$rD), (ins vrrc:$vB),
+ "vextractwm $rD, $vB", IIC_VecGeneral,
+ []>;
+ def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$rD), (ins vrrc:$vB),
+ "vextractdm $rD, $vB", IIC_VecGeneral,
+ []>;
+ def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$rD), (ins vrrc:$vB),
+ "vextractqm $rD, $vB", IIC_VecGeneral,
+ []>;
+ def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB),
+ "vexpandbm $vD, $vB", IIC_VecGeneral,
+ []>;
+ def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB),
+ "vexpandhm $vD, $vB", IIC_VecGeneral,
+ []>;
+ def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$vD), (ins vrrc:$vB),
+ "vexpandwm $vD, $vB", IIC_VecGeneral,
+ []>;
+ def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB),
+ "vexpanddm $vD, $vB", IIC_VecGeneral,
+ []>;
+ def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB),
+ "vexpandqm $vD, $vB", IIC_VecGeneral,
+ []>;
+ def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB),
+ "mtvsrbm $vD, $rB", IIC_VecGeneral,
+ []>;
+ def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$vD), (ins g8rc:$rB),
+ "mtvsrhm $vD, $rB", IIC_VecGeneral,
+ []>;
+ def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$vD), (ins g8rc:$rB),
+ "mtvsrwm $vD, $rB", IIC_VecGeneral,
+ []>;
+ def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$vD), (ins g8rc:$rB),
+ "mtvsrdm $vD, $rB", IIC_VecGeneral,
+ []>;
+ def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$vD), (ins g8rc:$rB),
+ "mtvsrqm $vD, $rB", IIC_VecGeneral,
+ []>;
+ def MTVSRBMI : DXForm<4, 10, (outs vrrc:$vD), (ins u16imm64:$D),
+ "mtvsrbmi $vD, $D", IIC_VecGeneral,
+ []>;
+ def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$rD),
+ (ins vrrc:$vB, u1imm:$MP),
+ "vcntmbb $rD, $vB, $MP", IIC_VecGeneral,
+ []>;
+ def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$rD),
+ (ins vrrc:$vB, u1imm:$MP),
+ "vcntmbh $rD, $vB, $MP", IIC_VecGeneral,
+ []>;
+ def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$rD),
+ (ins vrrc:$vB, u1imm:$MP),
+ "vcntmbw $rD, $vB, $MP", IIC_VecGeneral,
+ []>;
+ def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$rD),
+ (ins vrrc:$vB, u1imm:$MP),
+ "vcntmbd $rD, $vB, $MP", IIC_VecGeneral,
+ []>;
def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$vD),
(ins vrrc:$vA, vrrc:$vB, gprc:$rC),
"vextdubvlx $vD, $vA, $vB, $rC",
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
index 569068ab21a7a..eb17515de0ca9 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
@@ -378,6 +378,66 @@
# CHECK: stxvrdx 35, 3, 1
0x7c 0x63 0x09 0xdb
+# CHECK: vextractbm 1, 2
+0x10 0x28 0x16 0x42
+
+# CHECK: vextracthm 1, 2
+0x10 0x29 0x16 0x42
+
+# CHECK: vextractwm 1, 2
+0x10 0x2a 0x16 0x42
+
+# CHECK: vextractdm 1, 2
+0x10 0x2b 0x16 0x42
+
+# CHECK: vextractqm 1, 2
+0x10 0x2c 0x16 0x42
+
+# CHECK: vexpandbm 1, 2
+0x10 0x20 0x16 0x42
+
+# CHECK: vexpandhm 1, 2
+0x10 0x21 0x16 0x42
+
+# CHECK: vexpandwm 1, 2
+0x10 0x22 0x16 0x42
+
+# CHECK: vexpanddm 1, 2
+0x10 0x23 0x16 0x42
+
+# CHECK: vexpandqm 1, 2
+0x10 0x24 0x16 0x42
+
+# CHECK: mtvsrbm 1, 2
+0x10 0x30 0x16 0x42
+
+# CHECK: mtvsrhm 1, 2
+0x10 0x31 0x16 0x42
+
+# CHECK: mtvsrwm 1, 2
+0x10 0x32 0x16 0x42
+
+# CHECK: mtvsrdm 1, 2
+0x10 0x33 0x16 0x42
+
+# CHECK: mtvsrqm 1, 2
+0x10 0x34 0x16 0x42
+
+# CHECK: mtvsrbmi 1, 65535
+0x10 0x3f 0xff 0xd5
+
+# CHECK: vcntmbb 1, 2, 1
+0x10 0x39 0x16 0x42
+
+# CHECK: vcntmbh 1, 2, 1
+0x10 0x3b 0x16 0x42
+
+# CHECK: vcntmbw 1, 2, 0
+0x10 0x3c 0x16 0x42
+
+# CHECK: vcntmbd 1, 2, 0
+0x10 0x3e 0x16 0x42
+
# CHECK: vmulesd 1, 2, 3
0x10 0x22 0x1b 0xc8
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
index 6968821a3c09b..d925f717d0546 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -504,6 +504,66 @@
# CHECK-BE: stxvrdx 35, 3, 1 # encoding: [0x7c,0x63,0x09,0xdb]
# CHECK-LE: stxvrdx 35, 3, 1 # encoding: [0xdb,0x09,0x63,0x7c]
stxvrdx 35, 3, 1
+# CHECK-BE: vextractbm 1, 2 # encoding: [0x10,0x28,0x16,0x42]
+# CHECK-LE: vextractbm 1, 2 # encoding: [0x42,0x16,0x28,0x10]
+ vextractbm 1, 2
+# CHECK-BE: vextracthm 1, 2 # encoding: [0x10,0x29,0x16,0x42]
+# CHECK-LE: vextracthm 1, 2 # encoding: [0x42,0x16,0x29,0x10]
+ vextracthm 1, 2
+# CHECK-BE: vextractwm 1, 2 # encoding: [0x10,0x2a,0x16,0x42]
+# CHECK-LE: vextractwm 1, 2 # encoding: [0x42,0x16,0x2a,0x10]
+ vextractwm 1, 2
+# CHECK-BE: vextractdm 1, 2 # encoding: [0x10,0x2b,0x16,0x42]
+# CHECK-LE: vextractdm 1, 2 # encoding: [0x42,0x16,0x2b,0x10]
+ vextractdm 1, 2
+# CHECK-BE: vextractqm 1, 2 # encoding: [0x10,0x2c,0x16,0x42]
+# CHECK-LE: vextractqm 1, 2 # encoding: [0x42,0x16,0x2c,0x10]
+ vextractqm 1, 2
+# CHECK-BE: vexpandbm 1, 2 # encoding: [0x10,0x20,0x16,0x42]
+# CHECK-LE: vexpandbm 1, 2 # encoding: [0x42,0x16,0x20,0x10]
+ vexpandbm 1, 2
+# CHECK-BE: vexpandhm 1, 2 # encoding: [0x10,0x21,0x16,0x42]
+# CHECK-LE: vexpandhm 1, 2 # encoding: [0x42,0x16,0x21,0x10]
+ vexpandhm 1, 2
+# CHECK-BE: vexpandwm 1, 2 # encoding: [0x10,0x22,0x16,0x42]
+# CHECK-LE: vexpandwm 1, 2 # encoding: [0x42,0x16,0x22,0x10]
+ vexpandwm 1, 2
+# CHECK-BE: vexpanddm 1, 2 # encoding: [0x10,0x23,0x16,0x42]
+# CHECK-LE: vexpanddm 1, 2 # encoding: [0x42,0x16,0x23,0x10]
+ vexpanddm 1, 2
+# CHECK-BE: vexpandqm 1, 2 # encoding: [0x10,0x24,0x16,0x42]
+# CHECK-LE: vexpandqm 1, 2 # encoding: [0x42,0x16,0x24,0x10]
+ vexpandqm 1, 2
+# CHECK-BE: mtvsrbm 1, 2 # encoding: [0x10,0x30,0x16,0x42]
+# CHECK-LE: mtvsrbm 1, 2 # encoding: [0x42,0x16,0x30,0x10]
+ mtvsrbm 1, 2
+# CHECK-BE: mtvsrhm 1, 2 # encoding: [0x10,0x31,0x16,0x42]
+# CHECK-LE: mtvsrhm 1, 2 # encoding: [0x42,0x16,0x31,0x10]
+ mtvsrhm 1, 2
+# CHECK-BE: mtvsrwm 1, 2 # encoding: [0x10,0x32,0x16,0x42]
+# CHECK-LE: mtvsrwm 1, 2 # encoding: [0x42,0x16,0x32,0x10]
+ mtvsrwm 1, 2
+# CHECK-BE: mtvsrdm 1, 2 # encoding: [0x10,0x33,0x16,0x42]
+# CHECK-LE: mtvsrdm 1, 2 # encoding: [0x42,0x16,0x33,0x10]
+ mtvsrdm 1, 2
+# CHECK-BE: mtvsrqm 1, 2 # encoding: [0x10,0x34,0x16,0x42]
+# CHECK-LE: mtvsrqm 1, 2 # encoding: [0x42,0x16,0x34,0x10]
+ mtvsrqm 1, 2
+# CHECK-BE: mtvsrbmi 1, 31 # encoding: [0x10,0x2f,0x00,0x15]
+# CHECK-LE: mtvsrbmi 1, 31 # encoding: [0x15,0x00,0x2f,0x10]
+ mtvsrbmi 1, 31
+# CHECK-BE: vcntmbb 1, 2, 1 # encoding: [0x10,0x39,0x16,0x42]
+# CHECK-LE: vcntmbb 1, 2, 1 # encoding: [0x42,0x16,0x39,0x10]
+ vcntmbb 1, 2, 1
+# CHECK-BE: vcntmbh 1, 2, 1 # encoding: [0x10,0x3b,0x16,0x42]
+# CHECK-LE: vcntmbh 1, 2, 1 # encoding: [0x42,0x16,0x3b,0x10]
+ vcntmbh 1, 2, 1
+# CHECK-BE: vcntmbw 1, 2, 0 # encoding: [0x10,0x3c,0x16,0x42]
+# CHECK-LE: vcntmbw 1, 2, 0 # encoding: [0x42,0x16,0x3c,0x10]
+ vcntmbw 1, 2, 0
+# CHECK-BE: vcntmbd 1, 2, 0 # encoding: [0x10,0x3e,0x16,0x42]
+# CHECK-LE: vcntmbd 1, 2, 0 # encoding: [0x42,0x16,0x3e,0x10]
+ vcntmbd 1, 2, 0
# CHECK-BE: vmulesd 1, 2, 3 # encoding: [0x10,0x22,0x1b,0xc8]
# CHECK-LE: vmulesd 1, 2, 3 # encoding: [0xc8,0x1b,0x22,0x10]
vmulesd 1, 2, 3
More information about the llvm-commits
mailing list