[llvm] 34040a4 - GlobalISel: Define InvalidRegBankID enum value

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-08-06T12:39:49-04:00
New Revision: 34040a4f61fecaa8e901ca2e5e587df13d7097ac

URL: https://github.com/llvm/llvm-project/commit/34040a4f61fecaa8e901ca2e5e587df13d7097ac
DIFF: https://github.com/llvm/llvm-project/commit/34040a4f61fecaa8e901ca2e5e587df13d7097ac.diff

LOG: GlobalISel: Define InvalidRegBankID enum value

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    llvm/utils/TableGen/RegisterBankEmitter.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 9c9f14427782..7e664492ee46 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -3302,10 +3302,10 @@ static unsigned regBankUnion(unsigned RB0, unsigned RB1) {
     AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
 }
 
-static int regBankBoolUnion(int RB0, int RB1) {
-  if (RB0 == -1)
+static unsigned regBankBoolUnion(unsigned RB0, unsigned RB1) {
+  if (RB0 == AMDGPU::InvalidRegBankID)
     return RB1;
-  if (RB1 == -1)
+  if (RB1 == AMDGPU::InvalidRegBankID)
     return RB0;
 
   // vcc, vcc -> vcc
@@ -3413,8 +3413,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   //
   // TODO: There are additional exec masking dependencies to analyze.
   if (MI.getOpcode() == TargetOpcode::G_PHI) {
-    // TODO: Generate proper invalid bank enum.
-    int ResultBank = -1;
+    unsigned ResultBank = AMDGPU::InvalidRegBankID;
     Register DstReg = MI.getOperand(0).getReg();
 
     // Sometimes the result may have already been assigned a bank.
@@ -3436,7 +3435,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       ResultBank = regBankBoolUnion(ResultBank, OpBank);
     }
 
-    assert(ResultBank != -1);
+    assert(ResultBank != AMDGPU::InvalidRegBankID);
 
     unsigned Size = MRI.getType(DstReg).getSizeInBits();
 
@@ -3465,9 +3464,9 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
       const RegisterBank *DstBank
         = getRegBank(MI.getOperand(0).getReg(), MRI, *TRI);
 
-      unsigned TargetBankID = -1;
-      unsigned BankLHS = -1;
-      unsigned BankRHS = -1;
+      unsigned TargetBankID = AMDGPU::InvalidRegBankID;
+      unsigned BankLHS = AMDGPU::InvalidRegBankID;
+      unsigned BankRHS = AMDGPU::InvalidRegBankID;
       if (DstBank) {
         TargetBankID = DstBank->getID();
         if (DstBank == &AMDGPU::VCCRegBank) {

diff  --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index 586f857b1fb0..9a4c448921ea 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -131,9 +131,12 @@ void RegisterBankEmitter::emitHeader(raw_ostream &OS,
   // <Target>RegisterBankInfo.h
   OS << "namespace llvm {\n"
      << "namespace " << TargetName << " {\n"
-     << "enum {\n";
+     << "enum : unsigned {\n";
+
+  OS << "InvalidRegBankID = ~0u,\n";
+  unsigned ID = 0;
   for (const auto &Bank : Banks)
-    OS << "  " << Bank.getEnumeratorName() << ",\n";
+    OS << "  " << Bank.getEnumeratorName() << " = " << ID++ << ",\n";
   OS << "  NumRegisterBanks,\n"
      << "};\n"
      << "} // end namespace " << TargetName << "\n"