[PATCH] D84324: AMDGPU/GlobalISel: Lower G_FREM

[Jay Foad via Phabricator via llvm-commits]

foad accepted this revision.
foad added a comment.

Looks OK to me but please wait to hear from @arsenm too.



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Comment at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1661-1667
+  /// Build and insert \p Res = G_FDIV \p Op0, \p Op1
+  MachineInstrBuilder buildFDiv(const DstOp &Dst, const SrcOp &Src0,
+                                const SrcOp &Src1,
+                                Optional<unsigned> Flags = None) {
+    return buildInstr(TargetOpcode::G_FDIV, {Dst}, {Src0, Src1}, Flags);
+  }
+
----------------
Maybe put this declaration next to buildFAdd / buildFSub ?


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:703-705
+  getActionDefinitionsBuilder(G_FREM)
+    .customFor({S16, S32, S64})
+    .scalarize(0);
----------------
Does this need to be conditional on ST.has16BitInsts ?


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:1868-1869
+    auto Div = B.buildFDiv(Ty, Src0Reg, Src1Reg, Flags);
+    auto FpTrunc = B.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Ty},
+                                                {Div}, Flags);
+    auto Neg = B.buildFNeg(Ty, FpTrunc, Flags);
----------------
Use buildIntrinsicTrunc?


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https://reviews.llvm.org/D84324