[PATCH] D84937: [SVE][CodeGen] Fix scalable vector issues in DAGTypeLegalizer::GenWidenVectorStores

Thu Aug 6 00:41:22 PDT 2020

david-arm added a comment.

Hi @efriedma I tried rebasing and I do get a little further, but then fail at isel:

LLVM ERROR: Cannot select: t22: ch = store<(store unknown-size, align 32)> t0, t27, t19, undef:i64

  t27: nxv2f32 = extract_subvector t28, Constant:i64<0>
    t28: nxv4f32 = AArch64ISD::DUP ConstantFP:f32<1.000000e+00>
      t4: f32 = ConstantFP<1.000000e+00>
    t14: i64 = Constant<0>
  t19: i64 = add t2, t18
    t2: i64,ch = CopyFromReg t0, Register:i64 %0
      t1: i64 = Register %0
    t18: i64 = vscale Constant:i64<16>
      t17: i64 = Constant<16>
  t9: i64 = undef

In function: store_nxv6f32

I can try to fix this as part of this change if you want? Alternatively, this could be done in a parent patch that adds support for storing <vscale x 2 x float>if you think this is worthwhile? The alignment also looks wrong for the store.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84937/new/

https://reviews.llvm.org/D84937