[PATCH] D85364: [SVE][WIP] Implement lowering for fixed width select

Wed Aug 5 16:29:06 PDT 2020

cameron.mcinally added a comment.

In D85364#2197931 <https://reviews.llvm.org/D85364#2197931>, @efriedma wrote:

> For `load <8 x i1>` specifically, the code is terrible because we're using the generic target-independent expansion, which goes element by element.  If we cared, we could custom-lower it to something more reasonable.  Nobody has looked into it because there isn't any way to generate that operation from C code.

That's interesting. If we could load the vXi1 and then vector extend it, it might be more palatable. I haven't checked if there are instructions to support that though. And I wonder if it will get weird with a vector-of-i1s smaller than a byte...

In D85364#2197915 <https://reviews.llvm.org/D85364#2197915>, @efriedma wrote:

>> At VL=512, the v8i1 mask will be promoted to v8i64. In order to lower this to a scalable mask, we'd need to insert the v8i64 subvector into a nxv2i64. And then truncate that ZPR by performing a CMPNE against 0, to get the final nxv2i1 mask. Between the zero extend to promote the vXi1 mask, and the truncate to get back to a nxvXi1, there's a lot of extra instructions.
>
> I had this concern when I was reviewing the code in question. @paulwalker-arm said he found the conversions were usually folded away in his prototype. Most i1 vectors will be produced by a compare that returns an nxv2i1 or something like that.

I guess if it is amortized away, it's not a big deal. But a CMPNE is 4 cycles and a SX is 4 cycles. So we have an 8 cycle no-op. That's not great.

Also, I think we can get rid of this AND, unless I'm missing an edge case. The LSB will still be 1 without the AND. I'm not sure if the top bits could get us in trouble though:

          // Truncate the mask: nxv2i64 -> nxv2i1
  	and	z0.d, z0.d, #0x1
  	cmpne	p2.d, p1/z, z0.d, #0

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