[PATCH] D85234: [AMDGPU] Scavenge a temp register for AGPR spill in fast RA

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:1361
+      MachineRegisterInfo &MRI = MF->getRegInfo();
+      Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+    }
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arsenm wrote:
> rampitec wrote:
> > arsenm wrote:
> > > I think this should be dealt with in eliminateFrameIndex rather than trying to speculatively add the def here
> > It seems more robust to use the allocator rather than scavenger. We may need scavenger at -O0, but at least can do it better at a normal opt level.
> I'm not sure it's necessarily correct in greedy. You're not updating the live intervals here for example, and am not sure it will end up working out always.
> 
> In general you need a reserved register to deal with spilling. Maybe we could add some mechanism to inform the allocator when a temp reg with another class is needed for spilling?
That would require some implementation in all of the allocators...


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  https://reviews.llvm.org/D85234/new/

https://reviews.llvm.org/D85234