[llvm] 486e84d - AMDGPU/GlobalISel: Use live in helper function for returnaddress

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2020-08-04T17:36:01-04:00
New Revision: 486e84dfa4923ba506e715098699fc17aa7f9e40

URL: https://github.com/llvm/llvm-project/commit/486e84dfa4923ba506e715098699fc17aa7f9e40
DIFF: https://github.com/llvm/llvm-project/commit/486e84dfa4923ba506e715098699fc17aa7f9e40.diff

LOG: AMDGPU/GlobalISel: Use live in helper function for returnaddress

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 0beff5c5f571..d3e792b5832b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1094,8 +1094,6 @@ bool AMDGPUInstructionSelector::selectReturnAddress(MachineInstr &I) const {
       !RBI.constrainGenericRegister(DstReg, *RC, *MRI))
     return false;
 
-  MachineBasicBlock &EntryMBB = MF.front();
-
   // Check for kernel and shader functions
   if (Depth != 0 ||
       MF.getInfo<SIMachineFunctionInfo>()->isEntryFunction()) {
@@ -1105,22 +1103,14 @@ bool AMDGPUInstructionSelector::selectReturnAddress(MachineInstr &I) const {
     return true;
   }
 
-  Register ReturnAddrReg = TRI.getReturnAddressReg(MF);
-
   MachineFrameInfo &MFI = MF.getFrameInfo();
   // There is a call to @llvm.returnaddress in this function
   MFI.setReturnAddressIsTaken(true);
 
   // Get the return address reg and mark it as an implicit live-in
-  Register LiveIn = MRI->getLiveInVirtReg(ReturnAddrReg);
-  if (!LiveIn) {
-    LiveIn = MF.addLiveIn(ReturnAddrReg, RC);
-    BuildMI(EntryMBB, EntryMBB.begin(), DL, TII.get(AMDGPU::COPY), LiveIn)
-      .addReg(ReturnAddrReg);
-    if (!EntryMBB.isLiveIn(ReturnAddrReg))
-      EntryMBB.addLiveIn(ReturnAddrReg);
-  }
-
+  Register ReturnAddrReg = TRI.getReturnAddressReg(MF);
+  Register LiveIn = getFunctionLiveInPhysReg(MF, TII, ReturnAddrReg,
+                                             AMDGPU::SReg_64RegClass);
   BuildMI(*MBB, &I, DL, TII.get(AMDGPU::COPY), DstReg)
     .addReg(LiveIn);
   I.eraseFromParent();