[PATCH] D85202: TableGen/GlobalISel: Partially handle immAllOnesV/immAllZerosV

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: dsanders, paquette, aemerson, aditya_nandakumar.
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These should really match either G_BUILD_VECTOR or
G_BUILD_VECTOR_TRUNC, but there doesn't seem to be an existing
mechanism for matching alternative opcodes. There is GIM_SwitchOpcode,
but it seems to assume it's oly only used for matcher optimization.

      

I could also omit any opcode check and rely on the matcher directly
checking the opcode, but the table optimizer currently assumes there
has to be an opcode check.

      

Also doesn't try to handle undef elements like the DAG version.


https://reviews.llvm.org/D85202

Files:
  llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h
  llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  llvm/include/llvm/CodeGen/GlobalISel/Utils.h
  llvm/lib/CodeGen/GlobalISel/Utils.cpp
  llvm/test/CodeGen/AArch64/arm64-vabs.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
  llvm/test/TableGen/Common/GlobalISelEmitterCommon.td
  llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td
  llvm/utils/TableGen/GlobalISelEmitter.cpp

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