[PATCH] D85142: [SVE] Replace remaining _MERGE_OP1 nodes with _PRED variants.

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

LGTM



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11960
+  // ISD way to specify an all active predicate.
+  if ((Pg.getOpcode() == AArch64ISD::PTRUE) &&
+      (Pg.getConstantOperandVal(0) == AArch64SVEPredPattern::all))
----------------
You don't need to change it here, but should we be lowering aarch64_sve_ptrue to AArch64ISD::PTRUE, instead of supporting both forms through isel?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85142/new/

https://reviews.llvm.org/D85142