[PATCH] D85117: [SVE] Add lowering for fixed length vector and, or & xor operations.

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added a comment.

In D85117#2190432 <https://reviews.llvm.org/D85117#2190432>, @paulwalker-arm wrote:

> I have mixed feelings out this patch.  Ideally I would like everything lowered to _PRED nodes and then let ISel decide which instruction best does the job.  Unfortunately I could not see a clear way to write a pattern where one of the inputs is ignored.  Am I missing something obvious here? if not then I guess this patch will have to do.

I think you're looking for something like `immAllOnesV`. So you'd use XXX_PRED and pass an all-1s mask. Then a pattern would be needed to match it to the unpredicated instruction. Something roughly like this:

  def : Pat<(XOR_PRED (mask_vt immAllOnesV), ZPR:$src1, ZPR:$src2),
            (XOR ZPR:$src1, ZPR:$src2)>;


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  https://reviews.llvm.org/D85117/new/

https://reviews.llvm.org/D85117