[PATCH] D85117: [SVE] Add lowering for fixed length vector and, or & xor operations.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm created this revision.
Herald added subscribers: llvm-commits, psnobl, hiraditya, tschuett.
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Herald added a project: LLVM.
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Since there are no ill effects when performing these operations
with undefined elements, they are lowered to the already supported
unpredicated scalable vector equivalents.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D85117

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll

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