[PATCH] D85101: [AArch64][CodeGen] Restrict bfloat vector operations to what's actually supported

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Quick question - what is the expected behaviour? Do we just never expect to see an bf16 add, and if we do it's a fatal error? Or is some form of automatic promotion expected to happen?



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1021
+  if (VT.getVectorElementType() != MVT::bf16) {
+    setOperationAction(ISD::SRA, VT, Custom);
+    setOperationAction(ISD::SRL, VT, Custom);
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These are integer, so I wouldn't expect then to cause much trouble.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1045
+    setOperationAction(ISD::SREM, VT, Expand);
+    setOperationAction(ISD::FREM, VT, Expand);
+  }
----------------
Why not leave these as expand?


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https://reviews.llvm.org/D85101