[llvm] 09f9f7d - [AArch64][GlobalISel] Add legalization & selection support for G_INTRINSIC_LRINT.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 30 16:15:25 PDT 2020
Author: Amara Emerson
Date: 2020-07-30T16:14:56-07:00
New Revision: 09f9f7dd1bfe3ec2625fec4de36f4d9c63593bf7
URL: https://github.com/llvm/llvm-project/commit/09f9f7dd1bfe3ec2625fec4de36f4d9c63593bf7
DIFF: https://github.com/llvm/llvm-project/commit/09f9f7dd1bfe3ec2625fec4de36f4d9c63593bf7.diff
LOG: [AArch64][GlobalISel] Add legalization & selection support for G_INTRINSIC_LRINT.
Differential Revision: https://reviews.llvm.org/D84552
Added:
llvm/test/CodeGen/AArch64/GlobalISel/legalize-lrint.mir
Modified:
llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
llvm/test/CodeGen/AArch64/lrint-conv.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index 14718556810f..d3ca771ad3ad 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -125,6 +125,7 @@ def : GINodeEquiv<G_FRINT, frint>;
def : GINodeEquiv<G_FNEARBYINT, fnearbyint>;
def : GINodeEquiv<G_INTRINSIC_TRUNC, ftrunc>;
def : GINodeEquiv<G_INTRINSIC_ROUND, fround>;
+def : GINodeEquiv<G_INTRINSIC_LRINT, lrint>;
def : GINodeEquiv<G_FCOPYSIGN, fcopysign>;
def : GINodeEquiv<G_SMIN, smin>;
def : GINodeEquiv<G_SMAX, smax>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 54e368cd7768..6e5563af4363 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -156,7 +156,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR, G_FRINT,
G_FMA, G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND,
- G_FNEARBYINT})
+ G_FNEARBYINT, G_INTRINSIC_LRINT})
// If we don't have full FP16 support, then scalarize the elements of
// vectors containing fp16 types.
.fewerElementsIf(
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-lrint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-lrint.mir
new file mode 100644
index 000000000000..ddc4f07e1a14
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-lrint.mir
@@ -0,0 +1,94 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=legalizer %s -o - | FileCheck %s
+---
+name: testmsws
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$s0' }
+body: |
+ bb.1:
+ liveins: $s0
+
+ ; CHECK-LABEL: name: testmsws
+ ; CHECK: liveins: $s0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+ ; CHECK: [[INTRINSIC_LRINT:%[0-9]+]]:_(s64) = G_INTRINSIC_LRINT [[COPY]](s32)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[INTRINSIC_LRINT]](s64)
+ ; CHECK: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK: RET_ReallyLR implicit $w0
+ %0:_(s32) = COPY $s0
+ %1:_(s64) = G_INTRINSIC_LRINT %0(s32)
+ %2:_(s32) = G_TRUNC %1(s64)
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: testmsxs
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$s0' }
+body: |
+ bb.1:
+ liveins: $s0
+
+ ; CHECK-LABEL: name: testmsxs
+ ; CHECK: liveins: $s0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
+ ; CHECK: [[INTRINSIC_LRINT:%[0-9]+]]:_(s64) = G_INTRINSIC_LRINT [[COPY]](s32)
+ ; CHECK: $x0 = COPY [[INTRINSIC_LRINT]](s64)
+ ; CHECK: RET_ReallyLR implicit $x0
+ %0:_(s32) = COPY $s0
+ %1:_(s64) = G_INTRINSIC_LRINT %0(s32)
+ $x0 = COPY %1(s64)
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: testmswd
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$d0' }
+body: |
+ bb.1:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: testmswd
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+ ; CHECK: [[INTRINSIC_LRINT:%[0-9]+]]:_(s64) = G_INTRINSIC_LRINT [[COPY]](s64)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[INTRINSIC_LRINT]](s64)
+ ; CHECK: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK: RET_ReallyLR implicit $w0
+ %0:_(s64) = COPY $d0
+ %1:_(s64) = G_INTRINSIC_LRINT %0(s64)
+ %2:_(s32) = G_TRUNC %1(s64)
+ $w0 = COPY %2(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: testmsxd
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$d0' }
+body: |
+ bb.1:
+ liveins: $d0
+
+ ; CHECK-LABEL: name: testmsxd
+ ; CHECK: liveins: $d0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+ ; CHECK: [[INTRINSIC_LRINT:%[0-9]+]]:_(s64) = G_INTRINSIC_LRINT [[COPY]](s64)
+ ; CHECK: $x0 = COPY [[INTRINSIC_LRINT]](s64)
+ ; CHECK: RET_ReallyLR implicit $x0
+ %0:_(s64) = COPY $d0
+ %1:_(s64) = G_INTRINSIC_LRINT %0(s64)
+ $x0 = COPY %1(s64)
+ RET_ReallyLR implicit $x0
+
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 705f7cd1a058..110c57408c05 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -130,8 +130,9 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_INTRINSIC_LRINT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_INTRINSIC_ROUNDEVEN (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
diff --git a/llvm/test/CodeGen/AArch64/lrint-conv.ll b/llvm/test/CodeGen/AArch64/lrint-conv.ll
index 14d078b96ff1..80f1e8b8fc18 100644
--- a/llvm/test/CodeGen/AArch64/lrint-conv.ll
+++ b/llvm/test/CodeGen/AArch64/lrint-conv.ll
@@ -1,9 +1,11 @@
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
+; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=aarch64 | FileCheck %s --check-prefixes=FALLBACK,CHECK
; CHECK-LABEL: testmsws:
; CHECK: frintx [[REG:s[0-9]]], s0
; CHECK-NEXT: fcvtzs x0, [[REG]]
; CHECK: ret
+; FALLBACK-NOT: remark{{.*}}testmsws
define i32 @testmsws(float %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f32(float %x)
@@ -15,6 +17,7 @@ entry:
; CHECK: frintx [[REG:s[0-9]]], s0
; CHECK-NEXT: fcvtzs x0, [[REG]]
; CHECK-NEXT: ret
+; FALLBACK-NOT: remark{{.*}}testmsxs
define i64 @testmsxs(float %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f32(float %x)
@@ -25,6 +28,7 @@ entry:
; CHECK: frintx [[REG:d[0-9]]], d0
; CHECK-NEXT: fcvtzs x0, [[REG]]
; CHECK: ret
+; FALLBACK-NOT: remark{{.*}}testmswd
define i32 @testmswd(double %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f64(double %x)
@@ -36,6 +40,7 @@ entry:
; CHECK: frintx [[REG:d[0-9]]], d0
; CHECK-NEXT: fcvtzs x0, [[REG]]
; CHECK-NEXT: ret
+; FALLBACK-NOT: remark{{.*}}testmsxd
define i64 @testmsxd(double %x) {
entry:
%0 = tail call i64 @llvm.lrint.i64.f64(double %x)
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