[PATCH] D81648: MIR Statepoint refactoring. Part 4: ISEL changes.

Thu Jul 30 12:04:00 PDT 2020

reames added a comment.

In D81648#2150053 <https://reviews.llvm.org/D81648#2150053>, @dantrushin wrote:

> In D81648#2146051 <https://reviews.llvm.org/D81648#2146051>, @reames wrote:
>
>> Second, there appears to be a semantic problem around the handling of base vs derived slots unless we *always* spill the base.  We can't tie both uses to a single def.  This may warrant some offline discussion.
>
> Yes, we can't. But apparently, we do not need to.
> Basically, that tied-ness information is only needed to glue two live ranges into one during SSA flattening. And it does not matter how many uses end live range at the same instruction.
> Luckily, LLVM appears to handle it properly.
>
> But if included tests (and checks) do not make you believe it works, we should throw all this stuff away and try some different approach.

I filed a bug with a detailed description of the problem and one suggestion as to how to approach.  See https://bugs.llvm.org/show_bug.cgi?id=46917, let's take discussion there (or offline).

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https://reviews.llvm.org/D81648