[PATCH] D84833: Implement indirect branch generation in position independent code for the RISC-V target

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 requested changes to this revision.
jrtc27 added a comment.
This revision now requires changes to proceed.

Given @luismarques's comment, have you now actually run the tests (and I mean all RISC-V tests, not just branch-relaxation.ll, in case anything has been missed)? Perhaps I shouldn't take it for granted that people run tests before submitting patches, including revisions (though I'd still verify myself before committing anything), but you really should as otherwise it just wastes our time having to tell you they're broken when you could just run them yourself.



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1015-1017
+let isCall = 0, isBarrier = 1, isCodeGenOnly = 0, hasSideEffects = 0,
+    isBranch = 1, isTerminator = 1,
     mayStore = 0, mayLoad = 0 in
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Group the branch/terminator-related bits together and avoid unnecessary line breaks


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84833/new/

https://reviews.llvm.org/D84833