[PATCH] D84833: Implement indirect branch generation in position independent code for the RISC-V target

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/branch-relaxation.ll:4
 ; RUN:   -o /dev/null 2>&1
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -relocation-model=pic -verify-machineinstrs -filetype=obj < %s \
+; RUN:   -o /dev/null 2>&1
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This isn't quite what I suggested, as it's too long a line without wrapping more of the arguments to the next line.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84833/new/

https://reviews.llvm.org/D84833