[PATCH] D84833: Implement indirect branch generation in position independent code for the RISC-V target

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

This looks good to me now, let's see what others think. But please update `llvm/test/CodeGen/RISCV/branch-relaxation.ll` to reflect the change in CodeGen from LUI/JALR to AUIPC/JALR, and add PIC RUN lines. Plus whilst you're there I guess it wouldn't hurt to add RV64 variants too.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84833/new/

https://reviews.llvm.org/D84833