[PATCH] D84833: Implement indirect branch generation in position independent code for the RISC-V target and reorder BranchRelaxation to be run after RISCVExpandPseudo

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

(the fact that FreeBSD kernel builds could trigger relaxation is what exposed the bug fixed in https://reviews.llvm.org/D77443)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84833/new/

https://reviews.llvm.org/D84833