[llvm] a4edc04 - AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 28 08:18:13 PDT 2020
Author: Matt Arsenault
Date: 2020-07-28T11:18:05-04:00
New Revision: a4edc04693f76eec9068db0556d6533e4c201d74
URL: https://github.com/llvm/llvm-project/commit/a4edc04693f76eec9068db0556d6533e4c201d74
DIFF: https://github.com/llvm/llvm-project/commit/a4edc04693f76eec9068db0556d6533e4c201d74.diff
LOG: AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat
We also have never handled this for SelectionDAG, which needs
additional work.
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUGISel.td
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
llvm/lib/Target/AMDGPU/VOP2Instructions.td
llvm/lib/Target/AMDGPU/VOP3Instructions.td
llvm/lib/Target/AMDGPU/VOP3PInstructions.td
llvm/lib/Target/AMDGPU/VOPInstructions.td
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
index 3f12addbcc79..056f91db24ff 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
@@ -51,6 +51,11 @@ def gi_vop3opselmods :
GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">,
GIComplexPatternEquiv<VOP3OpSelMods>;
+// FIXME: Why do we have both VOP3OpSel and VOP3OpSelMods?
+def gi_vop3opsel :
+ GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">,
+ GIComplexPatternEquiv<VOP3OpSel>;
+
def gi_smrd_imm :
GIComplexOperandMatcher<s64, "selectSmrdImm">,
GIComplexPatternEquiv<SMRDImm>;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index bf0ebd322aa9..e14623e650d4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -422,7 +422,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
.scalarize(0);
- if (ST.hasVOP3PInsts()) {
+ if (ST.hasVOP3PInsts() && ST.hasAddNoCarry() && ST.hasIntClamp()) {
+ // Full set of gfx9 features.
getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
.legalFor({S32, S16, V2S16})
.clampScalar(0, S16, S32)
@@ -431,7 +432,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.widenScalarToNextPow2(0, 32);
getActionDefinitionsBuilder({G_UADDSAT, G_USUBSAT, G_SADDSAT, G_SSUBSAT})
- .lowerFor({S32, S16, V2S16}) // FIXME: legal and merge with add/sub/mul
+ .legalFor({S32, S16, V2S16}) // Clamp modifier
.minScalar(0, S16)
.clampMaxNumElements(0, S16, 2)
.scalarize(0)
@@ -447,7 +448,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
// Technically the saturating operations require clamp bit support, but this
// was introduced at the same time as 16-bit operations.
getActionDefinitionsBuilder({G_UADDSAT, G_USUBSAT})
- .lowerFor({S32, S16}) // FIXME: legal with clamp modifier
+ .legalFor({S32, S16}) // Clamp modifier
.minScalar(0, S16)
.scalarize(0)
.widenScalarToNextPow2(0, 16)
@@ -467,7 +468,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
if (ST.hasIntClamp()) {
getActionDefinitionsBuilder({G_UADDSAT, G_USUBSAT})
- .lowerFor({S32}) // FIXME: legal with clamp modifier.
+ .legalFor({S32}) // Clamp modifier.
.scalarize(0)
.minScalarOrElt(0, S32)
.lower();
@@ -479,6 +480,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.lower();
}
+ // FIXME: DAG expansion gets better results. The widening uses the smaller
+ // range values and goes for the min/max lowering directly.
getActionDefinitionsBuilder({G_SADDSAT, G_SSUBSAT})
.minScalar(0, S32)
.scalarize(0)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
index 6b2383049123..6848f762fc27 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -791,6 +791,10 @@ class GCNSubtarget : public AMDGPUGenSubtargetInfo,
return CIInsts;
}
+ /// \returns true if the target has integer add/sub instructions that do not
+ /// produce a carry-out. This includes v_add_[iu]32, v_sub_[iu]32,
+ /// v_add_[iu]16, and v_sub_[iu]16, all of which support the clamp modifier
+ /// for saturation.
bool hasAddNoCarry() const {
return AddNoCarryInsts;
}
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index d9dcfdca23b3..3451c2389181 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -828,6 +828,24 @@ def : GCNPat <
} // End Predicates = [Has16BitInsts]
+let SubtargetPredicate = HasIntClamp in {
+// Set clamp bit for saturation.
+def : VOPBinOpClampPat<uaddsat, V_ADD_CO_U32_e64, i32>;
+def : VOPBinOpClampPat<usubsat, V_SUB_CO_U32_e64, i32>;
+}
+
+let SubtargetPredicate = HasAddNoCarryInsts, OtherPredicates = [HasIntClamp] in {
+let AddedComplexity = 1 in { // Prefer over form with carry-out.
+def : VOPBinOpClampPat<uaddsat, V_ADD_U32_e64, i32>;
+def : VOPBinOpClampPat<usubsat, V_SUB_U32_e64, i32>;
+}
+}
+
+let SubtargetPredicate = Has16BitInsts, OtherPredicates = [HasIntClamp] in {
+def : VOPBinOpClampPat<uaddsat, V_ADD_U16_e64, i16>;
+def : VOPBinOpClampPat<usubsat, V_SUB_U16_e64, i16>;
+}
+
//===----------------------------------------------------------------------===//
// Target-specific instruction encodings.
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index dcbfeb547a32..3048bcc610c7 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -667,6 +667,20 @@ def : ThreeOp_i32_Pats<and, or, V_AND_OR_B32>;
def : ThreeOp_i32_Pats<or, or, V_OR3_B32>;
def : ThreeOp_i32_Pats<xor, add, V_XAD_U32>;
+def : VOPBinOpClampPat<saddsat, V_ADD_I32, i32>;
+def : VOPBinOpClampPat<ssubsat, V_SUB_I32, i32>;
+
+
+// FIXME: Probably should hardcode clamp bit in pseudo and avoid this.
+class OpSelBinOpClampPat<SDPatternOperator node,
+ Instruction inst> : GCNPat<
+ (node (i16 (VOP3OpSel i16:$src0, i32:$src0_modifiers)),
+ (i16 (VOP3OpSel i16:$src1, i32:$src1_modifiers))),
+ (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE, 0)
+>;
+
+def : OpSelBinOpClampPat<saddsat, V_ADD_I16>;
+def : OpSelBinOpClampPat<ssubsat, V_SUB_I16>;
} // End SubtargetPredicate = isGFX9Plus
def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3_OPSEL> {
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index fc457ad212d4..446e87ab3fc9 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -77,6 +77,8 @@ def V_PK_ASHRREV_I16 : VOP3PInst<"v_pk_ashrrev_i16", VOP3_Profile<VOP_V2I16_V2I1
def V_PK_LSHRREV_B16 : VOP3PInst<"v_pk_lshrrev_b16", VOP3_Profile<VOP_V2I16_V2I16_V2I16>, lshr_rev>;
+let SubtargetPredicate = HasVOP3PInsts in {
+
// Undo sub x, c -> add x, -c canonicalization since c is more likely
// an inline immediate than -c.
// The constant will be emitted as a mov, and folded later.
@@ -86,6 +88,19 @@ def : GCNPat<
(V_PK_SUB_U16 $src0_modifiers, $src0, SRCMODS.OP_SEL_1, NegSubInlineConstV216:$src1)
>;
+// Integer operations with clamp bit set.
+class VOP3PSatPat<SDPatternOperator pat, Instruction inst> : GCNPat<
+ (pat (v2i16 (VOP3PMods v2i16:$src0, i32:$src0_modifiers)),
+ (v2i16 (VOP3PMods v2i16:$src1, i32:$src1_modifiers))),
+ (inst $src0_modifiers, $src0, $src1_modifiers, $src1, DSTCLAMP.ENABLE)
+>;
+
+def : VOP3PSatPat<uaddsat, V_PK_ADD_U16>;
+def : VOP3PSatPat<saddsat, V_PK_ADD_I16>;
+def : VOP3PSatPat<usubsat, V_PK_SUB_U16>;
+def : VOP3PSatPat<ssubsat, V_PK_SUB_I16>;
+} // End SubtargetPredicate = HasVOP3PInsts
+
multiclass MadFmaMixPats<SDPatternOperator fma_like,
Instruction mix_inst,
Instruction mixlo_inst,
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index f8a83e5f74c0..ab1915de0c73 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -776,6 +776,19 @@ class DivergentFragOrOp<SDPatternOperator Op, VOPProfile P> {
!if(!isa<SDNode>(Op), getDivergentFrag<Op>.ret, Op), Op);
}
+class getVSrcOp<ValueType vt> {
+ RegisterOperand ret = !if(!eq(vt.Size, 32), VSrc_b32, VSrc_b16);
+}
+
+// Class for binary integer operations with the clamp bit set for saturation
+// TODO: Add sub with negated inline constant pattern.
+class VOPBinOpClampPat<SDPatternOperator node, Instruction inst, ValueType vt> :
+ GCNPat<(node vt:$src0, vt:$src1),
+ (inst getVSrcOp<vt>.ret:$src0, getVSrcOp<vt>.ret:$src1,
+ DSTCLAMP.ENABLE)
+>;
+
+
include "VOPCInstructions.td"
include "VOP1Instructions.td"
include "VOP2Instructions.td"
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
index 28a8efad1d10..51b6e014a937 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
@@ -59,17 +59,8 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
- ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
- ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
- ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[SHL]], [[C3]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[C1]], [[SMAX]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[C2]], [[SMIN]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB1]], [[SHL1]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB]]
- ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[SMIN1]]
- ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[ADD]], [[C]](s16)
+ ; GFX9: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[SHL]], [[SHL1]]
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SADDSAT]], [[C]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -137,17 +128,8 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
- ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
- ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
- ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[SHL]], [[C3]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[C1]], [[SMAX]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[C2]], [[SMIN]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB1]], [[SHL1]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB]]
- ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[SMIN1]]
- ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[ADD]], [[C]](s16)
+ ; GFX9: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[SHL]], [[SHL1]]
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SADDSAT]], [[C]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -282,34 +264,19 @@ body: |
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16)
- ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
- ; GFX9: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
- ; GFX9: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[SHL]], [[C6]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[C4]], [[SMAX]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C6]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[C5]], [[SMIN]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB1]], [[SHL1]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB]]
- ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[SMIN1]]
- ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[ADD]], [[C3]](s16)
+ ; GFX9: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[SHL]], [[SHL1]]
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SADDSAT]], [[C3]](s16)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16)
; GFX9: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16)
- ; GFX9: [[SMAX2:%[0-9]+]]:_(s16) = G_SMAX [[SHL2]], [[C6]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[C4]], [[SMAX2]]
- ; GFX9: [[SMIN2:%[0-9]+]]:_(s16) = G_SMIN [[SHL2]], [[C6]]
- ; GFX9: [[SUB3:%[0-9]+]]:_(s16) = G_SUB [[C5]], [[SMIN2]]
- ; GFX9: [[SMAX3:%[0-9]+]]:_(s16) = G_SMAX [[SUB3]], [[SHL3]]
- ; GFX9: [[SMIN3:%[0-9]+]]:_(s16) = G_SMIN [[SMAX3]], [[SUB2]]
- ; GFX9: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[SHL2]], [[SMIN3]]
- ; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ADD1]], [[C3]](s16)
- ; GFX9: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9: [[SADDSAT1:%[0-9]+]]:_(s16) = G_SADDSAT [[SHL2]], [[SHL3]]
+ ; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SADDSAT1]], [[C3]](s16)
+ ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ASHR]](s16)
- ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C7]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]]
; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C7]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C4]]
; GFX9: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -375,17 +342,8 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
- ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
- ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
- ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[TRUNC]], [[C2]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[C]], [[SMAX]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[TRUNC]], [[C2]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[C1]], [[SMIN]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB1]], [[TRUNC1]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB]]
- ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[SMIN1]]
- ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
+ ; GFX9: [[SADDSAT:%[0-9]+]]:_(s16) = G_SADDSAT [[TRUNC]], [[TRUNC1]]
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SADDSAT]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -484,20 +442,8 @@ body: |
; GFX9-LABEL: name: saddsat_v2s16
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32)
- ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
- ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32)
- ; GFX9: [[SMAX:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[COPY]], [[BUILD_VECTOR_TRUNC2]]
- ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC]], [[SMAX]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[COPY]], [[BUILD_VECTOR_TRUNC2]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC1]], [[SMIN]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB1]], [[COPY1]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX1]], [[SUB]]
- ; GFX9: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD [[COPY]], [[SMIN1]]
- ; GFX9: $vgpr0 = COPY [[ADD]](<2 x s16>)
+ ; GFX9: [[SADDSAT:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[COPY]], [[COPY1]]
+ ; GFX9: $vgpr0 = COPY [[SADDSAT]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<2 x s16>) = G_SADDSAT %0, %1
@@ -676,30 +622,9 @@ body: |
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[DEF1]](s32)
- ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
- ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32)
- ; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C3]](s32), [[C3]](s32)
- ; GFX9: [[SMAX:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC6]]
- ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC4]], [[SMAX]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC6]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC5]], [[SMIN]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB1]], [[BUILD_VECTOR_TRUNC2]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX1]], [[SUB]]
- ; GFX9: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD [[BUILD_VECTOR_TRUNC]], [[SMIN1]]
- ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C3]](s32), [[C3]](s32)
- ; GFX9: [[SMAX2:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC9]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC7]], [[SMAX2]]
- ; GFX9: [[SMIN2:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC9]]
- ; GFX9: [[SUB3:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC8]], [[SMIN2]]
- ; GFX9: [[SMAX3:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB3]], [[BUILD_VECTOR_TRUNC3]]
- ; GFX9: [[SMIN3:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX3]], [[SUB2]]
- ; GFX9: [[ADD1:%[0-9]+]]:_(<2 x s16>) = G_ADD [[BUILD_VECTOR_TRUNC1]], [[SMIN3]]
- ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[ADD]](<2 x s16>), [[ADD1]](<2 x s16>), [[DEF2]](<2 x s16>)
+ ; GFX9: [[SADDSAT:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
+ ; GFX9: [[SADDSAT1:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
+ ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[SADDSAT]](<2 x s16>), [[SADDSAT1]](<2 x s16>), [[DEF2]](<2 x s16>)
; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
; GFX9: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0
; GFX9: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT]](<3 x s16>), [[EXTRACT1]](<3 x s16>)
@@ -870,30 +795,9 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; GFX9: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32)
- ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
- ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32)
- ; GFX9: [[SMAX:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[UV]], [[BUILD_VECTOR_TRUNC2]]
- ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC]], [[SMAX]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[UV]], [[BUILD_VECTOR_TRUNC2]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC1]], [[SMIN]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB1]], [[UV2]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX1]], [[SUB]]
- ; GFX9: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD [[UV]], [[SMIN1]]
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32)
- ; GFX9: [[SMAX2:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[UV1]], [[BUILD_VECTOR_TRUNC5]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC3]], [[SMAX2]]
- ; GFX9: [[SMIN2:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[UV1]], [[BUILD_VECTOR_TRUNC5]]
- ; GFX9: [[SUB3:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC4]], [[SMIN2]]
- ; GFX9: [[SMAX3:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB3]], [[UV3]]
- ; GFX9: [[SMIN3:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX3]], [[SUB2]]
- ; GFX9: [[ADD1:%[0-9]+]]:_(<2 x s16>) = G_ADD [[UV1]], [[SMIN3]]
- ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[ADD]](<2 x s16>), [[ADD1]](<2 x s16>)
+ ; GFX9: [[SADDSAT:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[UV]], [[UV2]]
+ ; GFX9: [[SADDSAT1:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[UV1]], [[UV3]]
+ ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[SADDSAT]](<2 x s16>), [[SADDSAT1]](<2 x s16>)
; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
@@ -938,17 +842,8 @@ body: |
; GFX9-LABEL: name: saddsat_s32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
- ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[C2]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SMAX]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[C2]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMIN]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[COPY1]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
- ; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[SMIN1]]
- ; GFX9: $vgpr0 = COPY [[ADD]](s32)
+ ; GFX9: [[SADDSAT:%[0-9]+]]:_(s32) = G_SADDSAT [[COPY]], [[COPY1]]
+ ; GFX9: $vgpr0 = COPY [[SADDSAT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_SADDSAT %0, %1
@@ -1014,24 +909,9 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
- ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[UV]], [[C2]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SMAX]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[UV]], [[C2]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMIN]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[UV2]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
- ; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[SMIN1]]
- ; GFX9: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[UV1]], [[C2]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SMAX2]]
- ; GFX9: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[UV1]], [[C2]]
- ; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMIN2]]
- ; GFX9: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SUB3]], [[UV3]]
- ; GFX9: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB2]]
- ; GFX9: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[SMIN3]]
- ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32)
+ ; GFX9: [[SADDSAT:%[0-9]+]]:_(s32) = G_SADDSAT [[UV]], [[UV2]]
+ ; GFX9: [[SADDSAT1:%[0-9]+]]:_(s32) = G_SADDSAT [[UV1]], [[UV3]]
+ ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SADDSAT]](s32), [[SADDSAT1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
index 40eb12034c97..f38da863cba9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
@@ -59,17 +59,8 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
- ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
- ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
- ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[SHL]], [[C3]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SMAX]], [[C1]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SMIN]], [[C2]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB]], [[SHL1]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB1]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[SMIN1]]
- ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SUB2]], [[C]](s16)
+ ; GFX9: [[SSUBSAT:%[0-9]+]]:_(s16) = G_SSUBSAT [[SHL]], [[SHL1]]
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SSUBSAT]], [[C]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -137,17 +128,8 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
- ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
- ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
- ; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[SHL]], [[C3]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SMAX]], [[C1]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C3]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SMIN]], [[C2]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB]], [[SHL1]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB1]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[SMIN1]]
- ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SUB2]], [[C]](s16)
+ ; GFX9: [[SSUBSAT:%[0-9]+]]:_(s16) = G_SSUBSAT [[SHL]], [[SHL1]]
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SSUBSAT]], [[C]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -282,34 +264,19 @@ body: |
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16)
- ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
- ; GFX9: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
- ; GFX9: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[SHL]], [[C6]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SMAX]], [[C4]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[SHL]], [[C6]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SMIN]], [[C5]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB]], [[SHL1]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB1]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[SMIN1]]
- ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SUB2]], [[C3]](s16)
+ ; GFX9: [[SSUBSAT:%[0-9]+]]:_(s16) = G_SSUBSAT [[SHL]], [[SHL1]]
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SSUBSAT]], [[C3]](s16)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16)
; GFX9: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16)
- ; GFX9: [[SMAX2:%[0-9]+]]:_(s16) = G_SMAX [[SHL2]], [[C6]]
- ; GFX9: [[SUB3:%[0-9]+]]:_(s16) = G_SUB [[SMAX2]], [[C4]]
- ; GFX9: [[SMIN2:%[0-9]+]]:_(s16) = G_SMIN [[SHL2]], [[C6]]
- ; GFX9: [[SUB4:%[0-9]+]]:_(s16) = G_SUB [[SMIN2]], [[C5]]
- ; GFX9: [[SMAX3:%[0-9]+]]:_(s16) = G_SMAX [[SUB3]], [[SHL3]]
- ; GFX9: [[SMIN3:%[0-9]+]]:_(s16) = G_SMIN [[SMAX3]], [[SUB4]]
- ; GFX9: [[SUB5:%[0-9]+]]:_(s16) = G_SUB [[SHL2]], [[SMIN3]]
- ; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SUB5]], [[C3]](s16)
- ; GFX9: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9: [[SSUBSAT1:%[0-9]+]]:_(s16) = G_SSUBSAT [[SHL2]], [[SHL3]]
+ ; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SSUBSAT1]], [[C3]](s16)
+ ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ASHR]](s16)
- ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C7]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]]
; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C7]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C4]]
; GFX9: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -375,17 +342,8 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
- ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
- ; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[TRUNC]], [[C2]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SMAX]], [[C]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[TRUNC]], [[C2]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SMIN]], [[C1]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(s16) = G_SMAX [[SUB]], [[TRUNC1]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(s16) = G_SMIN [[SMAX1]], [[SUB1]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[SMIN1]]
- ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB2]](s16)
+ ; GFX9: [[SSUBSAT:%[0-9]+]]:_(s16) = G_SSUBSAT [[TRUNC]], [[TRUNC1]]
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SSUBSAT]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -484,20 +442,8 @@ body: |
; GFX9-LABEL: name: ssubsat_v2s16
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32)
- ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
- ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32)
- ; GFX9: [[SMAX:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[COPY]], [[BUILD_VECTOR_TRUNC2]]
- ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMAX]], [[BUILD_VECTOR_TRUNC]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[COPY]], [[BUILD_VECTOR_TRUNC2]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMIN]], [[BUILD_VECTOR_TRUNC1]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB]], [[COPY1]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX1]], [[SUB1]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(<2 x s16>) = G_SUB [[COPY]], [[SMIN1]]
- ; GFX9: $vgpr0 = COPY [[SUB2]](<2 x s16>)
+ ; GFX9: [[SSUBSAT:%[0-9]+]]:_(<2 x s16>) = G_SSUBSAT [[COPY]], [[COPY1]]
+ ; GFX9: $vgpr0 = COPY [[SSUBSAT]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<2 x s16>) = G_SSUBSAT %0, %1
@@ -676,30 +622,9 @@ body: |
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[DEF1]](s32)
- ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
- ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32)
- ; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C3]](s32), [[C3]](s32)
- ; GFX9: [[SMAX:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC6]]
- ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMAX]], [[BUILD_VECTOR_TRUNC4]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC6]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMIN]], [[BUILD_VECTOR_TRUNC5]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB]], [[BUILD_VECTOR_TRUNC2]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX1]], [[SUB1]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC]], [[SMIN1]]
- ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C3]](s32), [[C3]](s32)
- ; GFX9: [[SMAX2:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC9]]
- ; GFX9: [[SUB3:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMAX2]], [[BUILD_VECTOR_TRUNC7]]
- ; GFX9: [[SMIN2:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC9]]
- ; GFX9: [[SUB4:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMIN2]], [[BUILD_VECTOR_TRUNC8]]
- ; GFX9: [[SMAX3:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB3]], [[BUILD_VECTOR_TRUNC3]]
- ; GFX9: [[SMIN3:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX3]], [[SUB4]]
- ; GFX9: [[SUB5:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC1]], [[SMIN3]]
- ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[SUB2]](<2 x s16>), [[SUB5]](<2 x s16>), [[DEF2]](<2 x s16>)
+ ; GFX9: [[SSUBSAT:%[0-9]+]]:_(<2 x s16>) = G_SSUBSAT [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
+ ; GFX9: [[SSUBSAT1:%[0-9]+]]:_(<2 x s16>) = G_SSUBSAT [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
+ ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[SSUBSAT]](<2 x s16>), [[SSUBSAT1]](<2 x s16>), [[DEF2]](<2 x s16>)
; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
; GFX9: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0
; GFX9: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT]](<3 x s16>), [[EXTRACT1]](<3 x s16>)
@@ -870,30 +795,9 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; GFX9: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32)
- ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
- ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32)
- ; GFX9: [[SMAX:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[UV]], [[BUILD_VECTOR_TRUNC2]]
- ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMAX]], [[BUILD_VECTOR_TRUNC]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[UV]], [[BUILD_VECTOR_TRUNC2]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMIN]], [[BUILD_VECTOR_TRUNC1]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB]], [[UV2]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX1]], [[SUB1]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(<2 x s16>) = G_SUB [[UV]], [[SMIN1]]
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C2]](s32), [[C2]](s32)
- ; GFX9: [[SMAX2:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[UV1]], [[BUILD_VECTOR_TRUNC5]]
- ; GFX9: [[SUB3:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMAX2]], [[BUILD_VECTOR_TRUNC3]]
- ; GFX9: [[SMIN2:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[UV1]], [[BUILD_VECTOR_TRUNC5]]
- ; GFX9: [[SUB4:%[0-9]+]]:_(<2 x s16>) = G_SUB [[SMIN2]], [[BUILD_VECTOR_TRUNC4]]
- ; GFX9: [[SMAX3:%[0-9]+]]:_(<2 x s16>) = G_SMAX [[SUB3]], [[UV3]]
- ; GFX9: [[SMIN3:%[0-9]+]]:_(<2 x s16>) = G_SMIN [[SMAX3]], [[SUB4]]
- ; GFX9: [[SUB5:%[0-9]+]]:_(<2 x s16>) = G_SUB [[UV1]], [[SMIN3]]
- ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[SUB2]](<2 x s16>), [[SUB5]](<2 x s16>)
+ ; GFX9: [[SSUBSAT:%[0-9]+]]:_(<2 x s16>) = G_SSUBSAT [[UV]], [[UV2]]
+ ; GFX9: [[SSUBSAT1:%[0-9]+]]:_(<2 x s16>) = G_SSUBSAT [[UV1]], [[UV3]]
+ ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[SSUBSAT]](<2 x s16>), [[SSUBSAT1]](<2 x s16>)
; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
@@ -938,17 +842,8 @@ body: |
; GFX9-LABEL: name: ssubsat_s32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
- ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX9: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[C2]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[C]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[C2]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C1]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[COPY1]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[SMIN1]]
- ; GFX9: $vgpr0 = COPY [[SUB2]](s32)
+ ; GFX9: [[SSUBSAT:%[0-9]+]]:_(s32) = G_SSUBSAT [[COPY]], [[COPY1]]
+ ; GFX9: $vgpr0 = COPY [[SSUBSAT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_SSUBSAT %0, %1
@@ -1014,24 +909,9 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
- ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
- ; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX9: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[UV]], [[C2]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[C]]
- ; GFX9: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[UV]], [[C2]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C1]]
- ; GFX9: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[UV2]]
- ; GFX9: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UV]], [[SMIN1]]
- ; GFX9: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[UV1]], [[C2]]
- ; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SMAX2]], [[C]]
- ; GFX9: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[UV1]], [[C2]]
- ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SMIN2]], [[C1]]
- ; GFX9: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SUB3]], [[UV3]]
- ; GFX9: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB4]]
- ; GFX9: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[UV1]], [[SMIN3]]
- ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB2]](s32), [[SUB5]](s32)
+ ; GFX9: [[SSUBSAT:%[0-9]+]]:_(s32) = G_SSUBSAT [[UV]], [[UV2]]
+ ; GFX9: [[SSUBSAT1:%[0-9]+]]:_(s32) = G_SSUBSAT [[UV1]], [[UV3]]
+ ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SSUBSAT]](s32), [[SSUBSAT1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
index 690bf34482dd..9d51870b4fed 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
@@ -32,11 +32,8 @@ body: |
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
- ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[SHL]], [[C1]]
- ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[SHL1]]
- ; GFX8: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[UMIN]]
- ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[ADD]], [[C]](s16)
+ ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]]
+ ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16)
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: uaddsat_s7
@@ -47,11 +44,8 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
- ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX9: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[SHL]], [[C1]]
- ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[SHL1]]
- ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[UMIN]]
- ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[ADD]], [[C]](s16)
+ ; GFX9: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]]
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -92,11 +86,8 @@ body: |
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
- ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[SHL]], [[C1]]
- ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[SHL1]]
- ; GFX8: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[UMIN]]
- ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[ADD]], [[C]](s16)
+ ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]]
+ ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16)
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: uaddsat_s8
@@ -107,11 +98,8 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
- ; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX9: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[SHL]], [[C1]]
- ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[SHL1]]
- ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[UMIN]]
- ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[ADD]], [[C]](s16)
+ ; GFX9: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]]
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -187,24 +175,19 @@ body: |
; GFX8: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16)
; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16)
- ; GFX8: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[SHL]], [[C4]]
- ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[SHL1]]
- ; GFX8: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[UMIN]]
- ; GFX8: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[ADD]], [[C3]](s16)
+ ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]]
+ ; GFX8: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C3]](s16)
; GFX8: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX8: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; GFX8: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16)
; GFX8: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16)
- ; GFX8: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[SHL2]], [[C4]]
- ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[XOR1]], [[SHL3]]
- ; GFX8: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[SHL2]], [[UMIN1]]
- ; GFX8: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[ADD1]], [[C3]](s16)
- ; GFX8: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX8: [[UADDSAT1:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL2]], [[SHL3]]
+ ; GFX8: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT1]], [[C3]](s16)
+ ; GFX8: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX8: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16)
- ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C5]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]]
; GFX8: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR7]](s16)
- ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C5]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C4]]
; GFX8: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX8: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -226,24 +209,19 @@ body: |
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16)
- ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX9: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[SHL]], [[C4]]
- ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[SHL1]]
- ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[SHL]], [[UMIN]]
- ; GFX9: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[ADD]], [[C3]](s16)
+ ; GFX9: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL]], [[SHL1]]
+ ; GFX9: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT]], [[C3]](s16)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16)
; GFX9: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16)
- ; GFX9: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[SHL2]], [[C4]]
- ; GFX9: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[XOR1]], [[SHL3]]
- ; GFX9: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[SHL2]], [[UMIN1]]
- ; GFX9: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[ADD1]], [[C3]](s16)
- ; GFX9: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
+ ; GFX9: [[UADDSAT1:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL2]], [[SHL3]]
+ ; GFX9: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT1]], [[C3]](s16)
+ ; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16)
- ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C5]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]]
; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR7]](s16)
- ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C5]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C4]]
; GFX9: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -286,22 +264,16 @@ body: |
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C]]
- ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[TRUNC1]]
- ; GFX8: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[UMIN]]
- ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
+ ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC1]]
+ ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDSAT]](s16)
; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: uaddsat_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX9: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C]]
- ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[TRUNC1]]
- ; GFX9: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[UMIN]]
- ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
+ ; GFX9: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC1]]
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDSAT]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -364,15 +336,10 @@ body: |
; GFX8: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
- ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C1]]
- ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[TRUNC2]]
- ; GFX8: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[UMIN]]
- ; GFX8: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C1]]
- ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[XOR1]], [[TRUNC3]]
- ; GFX8: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[UMIN1]]
- ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ADD]](s16)
- ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ADD1]](s16)
+ ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC2]]
+ ; GFX8: [[UADDSAT1:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC1]], [[TRUNC3]]
+ ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT]](s16)
+ ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT1]](s16)
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -380,12 +347,8 @@ body: |
; GFX9-LABEL: name: uaddsat_v2s16
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32)
- ; GFX9: [[XOR:%[0-9]+]]:_(<2 x s16>) = G_XOR [[COPY]], [[BUILD_VECTOR_TRUNC]]
- ; GFX9: [[UMIN:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[XOR]], [[COPY1]]
- ; GFX9: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD [[COPY]], [[UMIN]]
- ; GFX9: $vgpr0 = COPY [[ADD]](<2 x s16>)
+ ; GFX9: [[UADDSAT:%[0-9]+]]:_(<2 x s16>) = G_UADDSAT [[COPY]], [[COPY1]]
+ ; GFX9: $vgpr0 = COPY [[UADDSAT]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<2 x s16>) = G_UADDSAT %0, %1
@@ -482,24 +445,17 @@ body: |
; GFX8: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX8: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](s32)
; GFX8: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C1]]
- ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[TRUNC3]]
- ; GFX8: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[UMIN]]
- ; GFX8: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C1]]
- ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[XOR1]], [[TRUNC4]]
- ; GFX8: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[UMIN1]]
- ; GFX8: [[XOR2:%[0-9]+]]:_(s16) = G_XOR [[TRUNC2]], [[C1]]
- ; GFX8: [[UMIN2:%[0-9]+]]:_(s16) = G_UMIN [[XOR2]], [[TRUNC5]]
- ; GFX8: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[TRUNC2]], [[UMIN2]]
- ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ADD]](s16)
- ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ADD1]](s16)
+ ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC3]]
+ ; GFX8: [[UADDSAT1:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC1]], [[TRUNC4]]
+ ; GFX8: [[UADDSAT2:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC2]], [[TRUNC5]]
+ ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT]](s16)
+ ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT1]](s16)
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; GFX8: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ADD2]](s16)
- ; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
+ ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT2]](s16)
+ ; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX8: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX8: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
@@ -536,16 +492,9 @@ body: |
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[DEF1]](s32)
- ; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
- ; GFX9: [[XOR:%[0-9]+]]:_(<2 x s16>) = G_XOR [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC4]]
- ; GFX9: [[UMIN:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[XOR]], [[BUILD_VECTOR_TRUNC2]]
- ; GFX9: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD [[BUILD_VECTOR_TRUNC]], [[UMIN]]
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32)
- ; GFX9: [[XOR1:%[0-9]+]]:_(<2 x s16>) = G_XOR [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC5]]
- ; GFX9: [[UMIN1:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[XOR1]], [[BUILD_VECTOR_TRUNC3]]
- ; GFX9: [[ADD1:%[0-9]+]]:_(<2 x s16>) = G_ADD [[BUILD_VECTOR_TRUNC1]], [[UMIN1]]
- ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[ADD]](<2 x s16>), [[ADD1]](<2 x s16>), [[DEF2]](<2 x s16>)
+ ; GFX9: [[UADDSAT:%[0-9]+]]:_(<2 x s16>) = G_UADDSAT [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
+ ; GFX9: [[UADDSAT1:%[0-9]+]]:_(<2 x s16>) = G_UADDSAT [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
+ ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[UADDSAT]](<2 x s16>), [[UADDSAT1]](<2 x s16>), [[DEF2]](<2 x s16>)
; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
; GFX9: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0
; GFX9: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT]](<3 x s16>), [[EXTRACT1]](<3 x s16>)
@@ -650,26 +599,17 @@ body: |
; GFX8: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](s32)
; GFX8: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX8: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
- ; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
- ; GFX8: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C1]]
- ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[XOR]], [[TRUNC4]]
- ; GFX8: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[UMIN]]
- ; GFX8: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C1]]
- ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[XOR1]], [[TRUNC5]]
- ; GFX8: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[UMIN1]]
- ; GFX8: [[XOR2:%[0-9]+]]:_(s16) = G_XOR [[TRUNC2]], [[C1]]
- ; GFX8: [[UMIN2:%[0-9]+]]:_(s16) = G_UMIN [[XOR2]], [[TRUNC6]]
- ; GFX8: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[TRUNC2]], [[UMIN2]]
- ; GFX8: [[XOR3:%[0-9]+]]:_(s16) = G_XOR [[TRUNC3]], [[C1]]
- ; GFX8: [[UMIN3:%[0-9]+]]:_(s16) = G_UMIN [[XOR3]], [[TRUNC7]]
- ; GFX8: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[TRUNC3]], [[UMIN3]]
- ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ADD]](s16)
- ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ADD1]](s16)
+ ; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC4]]
+ ; GFX8: [[UADDSAT1:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC1]], [[TRUNC5]]
+ ; GFX8: [[UADDSAT2:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC2]], [[TRUNC6]]
+ ; GFX8: [[UADDSAT3:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC3]], [[TRUNC7]]
+ ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT]](s16)
+ ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT1]](s16)
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; GFX8: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ADD2]](s16)
- ; GFX8: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[ADD3]](s16)
+ ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT2]](s16)
+ ; GFX8: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT3]](s16)
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX8: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -680,16 +620,9 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; GFX9: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32)
- ; GFX9: [[XOR:%[0-9]+]]:_(<2 x s16>) = G_XOR [[UV]], [[BUILD_VECTOR_TRUNC]]
- ; GFX9: [[UMIN:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[XOR]], [[UV2]]
- ; GFX9: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD [[UV]], [[UMIN]]
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32)
- ; GFX9: [[XOR1:%[0-9]+]]:_(<2 x s16>) = G_XOR [[UV1]], [[BUILD_VECTOR_TRUNC1]]
- ; GFX9: [[UMIN1:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[XOR1]], [[UV3]]
- ; GFX9: [[ADD1:%[0-9]+]]:_(<2 x s16>) = G_ADD [[UV1]], [[UMIN1]]
- ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[ADD]](<2 x s16>), [[ADD1]](<2 x s16>)
+ ; GFX9: [[UADDSAT:%[0-9]+]]:_(<2 x s16>) = G_UADDSAT [[UV]], [[UV2]]
+ ; GFX9: [[UADDSAT1:%[0-9]+]]:_(<2 x s16>) = G_UADDSAT [[UV1]], [[UV3]]
+ ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[UADDSAT]](<2 x s16>), [[UADDSAT1]](<2 x s16>)
; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
@@ -714,19 +647,13 @@ body: |
; GFX8-LABEL: name: uaddsat_s32
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX8: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]
- ; GFX8: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[COPY1]]
- ; GFX8: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[UMIN]]
- ; GFX8: $vgpr0 = COPY [[ADD]](s32)
+ ; GFX8: [[UADDSAT:%[0-9]+]]:_(s32) = G_UADDSAT [[COPY]], [[COPY1]]
+ ; GFX8: $vgpr0 = COPY [[UADDSAT]](s32)
; GFX9-LABEL: name: uaddsat_s32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX9: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]
- ; GFX9: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[COPY1]]
- ; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[UMIN]]
- ; GFX9: $vgpr0 = COPY [[ADD]](s32)
+ ; GFX9: [[UADDSAT:%[0-9]+]]:_(s32) = G_UADDSAT [[COPY]], [[COPY1]]
+ ; GFX9: $vgpr0 = COPY [[UADDSAT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_UADDSAT %0, %1
@@ -758,28 +685,18 @@ body: |
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX8: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX8: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[UV]], [[C]]
- ; GFX8: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[UV2]]
- ; GFX8: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UMIN]]
- ; GFX8: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[UV1]], [[C]]
- ; GFX8: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[XOR1]], [[UV3]]
- ; GFX8: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UMIN1]]
- ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32)
+ ; GFX8: [[UADDSAT:%[0-9]+]]:_(s32) = G_UADDSAT [[UV]], [[UV2]]
+ ; GFX8: [[UADDSAT1:%[0-9]+]]:_(s32) = G_UADDSAT [[UV1]], [[UV3]]
+ ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UADDSAT]](s32), [[UADDSAT1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: uaddsat_v2s32
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX9: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[UV]], [[C]]
- ; GFX9: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[UV2]]
- ; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[UV]], [[UMIN]]
- ; GFX9: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[UV1]], [[C]]
- ; GFX9: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[XOR1]], [[UV3]]
- ; GFX9: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[UV1]], [[UMIN1]]
- ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ADD]](s32), [[ADD1]](s32)
+ ; GFX9: [[UADDSAT:%[0-9]+]]:_(s32) = G_UADDSAT [[UV]], [[UV2]]
+ ; GFX9: [[UADDSAT1:%[0-9]+]]:_(s32) = G_UADDSAT [[UV1]], [[UV3]]
+ ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UADDSAT]](s32), [[UADDSAT1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
index 356bb38456ea..5bb430cf4a06 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
@@ -30,9 +30,8 @@ body: |
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
- ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[SHL]], [[SHL1]]
- ; GFX8: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[UMIN]]
- ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[SUB]], [[C]](s16)
+ ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]]
+ ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C]](s16)
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: usubsat_s7
@@ -43,9 +42,8 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
- ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[SHL]], [[SHL1]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[UMIN]]
- ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[SUB]], [[C]](s16)
+ ; GFX9: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]]
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -84,9 +82,8 @@ body: |
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
- ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[SHL]], [[SHL1]]
- ; GFX8: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[UMIN]]
- ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[SUB]], [[C]](s16)
+ ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]]
+ ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C]](s16)
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: usubsat_s8
@@ -97,9 +94,8 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C]](s16)
- ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[SHL]], [[SHL1]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[UMIN]]
- ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[SUB]], [[C]](s16)
+ ; GFX9: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]]
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -172,16 +168,14 @@ body: |
; GFX8: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16)
; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16)
- ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[SHL]], [[SHL1]]
- ; GFX8: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[UMIN]]
- ; GFX8: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[SUB]], [[C3]](s16)
+ ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]]
+ ; GFX8: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C3]](s16)
; GFX8: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX8: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; GFX8: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16)
; GFX8: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16)
- ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[SHL2]], [[SHL3]]
- ; GFX8: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SHL2]], [[UMIN1]]
- ; GFX8: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[SUB1]], [[C3]](s16)
+ ; GFX8: [[USUBSAT1:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL2]], [[SHL3]]
+ ; GFX8: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT1]], [[C3]](s16)
; GFX8: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX8: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16)
; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]]
@@ -208,16 +202,14 @@ body: |
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16)
; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[C3]](s16)
- ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[SHL]], [[SHL1]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[SHL]], [[UMIN]]
- ; GFX9: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[SUB]], [[C3]](s16)
+ ; GFX9: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL]], [[SHL1]]
+ ; GFX9: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT]], [[C3]](s16)
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[C3]](s16)
; GFX9: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16)
- ; GFX9: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[SHL2]], [[SHL3]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[SHL2]], [[UMIN1]]
- ; GFX9: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[SUB1]], [[C3]](s16)
+ ; GFX9: [[USUBSAT1:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL2]], [[SHL3]]
+ ; GFX9: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT1]], [[C3]](s16)
; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16)
; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]]
@@ -263,18 +255,16 @@ body: |
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC]], [[TRUNC1]]
- ; GFX8: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[UMIN]]
- ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB]](s16)
+ ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC1]]
+ ; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USUBSAT]](s16)
; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: usubsat_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC]], [[TRUNC1]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[UMIN]]
- ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUB]](s16)
+ ; GFX9: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC1]]
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USUBSAT]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -334,12 +324,10 @@ body: |
; GFX8: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
- ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC]], [[TRUNC2]]
- ; GFX8: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[UMIN]]
- ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC1]], [[TRUNC3]]
- ; GFX8: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[TRUNC1]], [[UMIN1]]
- ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SUB]](s16)
- ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[SUB1]](s16)
+ ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC2]]
+ ; GFX8: [[USUBSAT1:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC1]], [[TRUNC3]]
+ ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT]](s16)
+ ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT1]](s16)
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -347,9 +335,8 @@ body: |
; GFX9-LABEL: name: usubsat_v2s16
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
- ; GFX9: [[UMIN:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[COPY]], [[COPY1]]
- ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[COPY]], [[UMIN]]
- ; GFX9: $vgpr0 = COPY [[SUB]](<2 x s16>)
+ ; GFX9: [[USUBSAT:%[0-9]+]]:_(<2 x s16>) = G_USUBSAT [[COPY]], [[COPY1]]
+ ; GFX9: $vgpr0 = COPY [[USUBSAT]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<2 x s16>) = G_USUBSAT %0, %1
@@ -442,18 +429,15 @@ body: |
; GFX8: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX8: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](s32)
; GFX8: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC]], [[TRUNC3]]
- ; GFX8: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[UMIN]]
- ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC1]], [[TRUNC4]]
- ; GFX8: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[TRUNC1]], [[UMIN1]]
- ; GFX8: [[UMIN2:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC2]], [[TRUNC5]]
- ; GFX8: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[TRUNC2]], [[UMIN2]]
- ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SUB]](s16)
- ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[SUB1]](s16)
+ ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC3]]
+ ; GFX8: [[USUBSAT1:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC1]], [[TRUNC4]]
+ ; GFX8: [[USUBSAT2:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC2]], [[TRUNC5]]
+ ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT]](s16)
+ ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT1]](s16)
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; GFX8: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SUB2]](s16)
+ ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT2]](s16)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
@@ -492,11 +476,9 @@ body: |
; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[DEF1]](s32)
- ; GFX9: [[UMIN:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
- ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC]], [[UMIN]]
- ; GFX9: [[UMIN1:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC1]], [[UMIN1]]
- ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[SUB]](<2 x s16>), [[SUB1]](<2 x s16>), [[DEF2]](<2 x s16>)
+ ; GFX9: [[USUBSAT:%[0-9]+]]:_(<2 x s16>) = G_USUBSAT [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
+ ; GFX9: [[USUBSAT1:%[0-9]+]]:_(<2 x s16>) = G_USUBSAT [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
+ ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[USUBSAT]](<2 x s16>), [[USUBSAT1]](<2 x s16>), [[DEF2]](<2 x s16>)
; GFX9: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
; GFX9: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[DEF]](<4 x s16>), 0
; GFX9: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[EXTRACT]](<3 x s16>), [[EXTRACT1]](<3 x s16>)
@@ -596,21 +578,17 @@ body: |
; GFX8: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](s32)
; GFX8: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX8: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
- ; GFX8: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC]], [[TRUNC4]]
- ; GFX8: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[TRUNC]], [[UMIN]]
- ; GFX8: [[UMIN1:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC1]], [[TRUNC5]]
- ; GFX8: [[SUB1:%[0-9]+]]:_(s16) = G_SUB [[TRUNC1]], [[UMIN1]]
- ; GFX8: [[UMIN2:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC2]], [[TRUNC6]]
- ; GFX8: [[SUB2:%[0-9]+]]:_(s16) = G_SUB [[TRUNC2]], [[UMIN2]]
- ; GFX8: [[UMIN3:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC3]], [[TRUNC7]]
- ; GFX8: [[SUB3:%[0-9]+]]:_(s16) = G_SUB [[TRUNC3]], [[UMIN3]]
- ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SUB]](s16)
- ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[SUB1]](s16)
+ ; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC4]]
+ ; GFX8: [[USUBSAT1:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC1]], [[TRUNC5]]
+ ; GFX8: [[USUBSAT2:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC2]], [[TRUNC6]]
+ ; GFX8: [[USUBSAT3:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC3]], [[TRUNC7]]
+ ; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT]](s16)
+ ; GFX8: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT1]](s16)
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL]]
; GFX8: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SUB2]](s16)
- ; GFX8: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[SUB3]](s16)
+ ; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT2]](s16)
+ ; GFX8: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT3]](s16)
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX8: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -621,11 +599,9 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; GFX9: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
- ; GFX9: [[UMIN:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[UV]], [[UV2]]
- ; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[UV]], [[UMIN]]
- ; GFX9: [[UMIN1:%[0-9]+]]:_(<2 x s16>) = G_UMIN [[UV1]], [[UV3]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[UV1]], [[UMIN1]]
- ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[SUB]](<2 x s16>), [[SUB1]](<2 x s16>)
+ ; GFX9: [[USUBSAT:%[0-9]+]]:_(<2 x s16>) = G_USUBSAT [[UV]], [[UV2]]
+ ; GFX9: [[USUBSAT1:%[0-9]+]]:_(<2 x s16>) = G_USUBSAT [[UV1]], [[UV3]]
+ ; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[USUBSAT]](<2 x s16>), [[USUBSAT1]](<2 x s16>)
; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
@@ -648,15 +624,13 @@ body: |
; GFX8-LABEL: name: usubsat_s32
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]]
- ; GFX8: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[UMIN]]
- ; GFX8: $vgpr0 = COPY [[SUB]](s32)
+ ; GFX8: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[COPY]], [[COPY1]]
+ ; GFX8: $vgpr0 = COPY [[USUBSAT]](s32)
; GFX9-LABEL: name: usubsat_s32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[UMIN]]
- ; GFX9: $vgpr0 = COPY [[SUB]](s32)
+ ; GFX9: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[COPY]], [[COPY1]]
+ ; GFX9: $vgpr0 = COPY [[USUBSAT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_USUBSAT %0, %1
@@ -685,22 +659,18 @@ body: |
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX8: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX8: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[UV]], [[UV2]]
- ; GFX8: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV]], [[UMIN]]
- ; GFX8: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[UV1]], [[UV3]]
- ; GFX8: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV1]], [[UMIN1]]
- ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB]](s32), [[SUB1]](s32)
+ ; GFX8: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[UV]], [[UV2]]
+ ; GFX8: [[USUBSAT1:%[0-9]+]]:_(s32) = G_USUBSAT [[UV1]], [[UV3]]
+ ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[USUBSAT]](s32), [[USUBSAT1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: usubsat_v2s32
; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX9: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[UV]], [[UV2]]
- ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV]], [[UMIN]]
- ; GFX9: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[UV1]], [[UV3]]
- ; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV1]], [[UMIN1]]
- ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB]](s32), [[SUB1]](s32)
+ ; GFX9: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[UV]], [[UV2]]
+ ; GFX9: [[USUBSAT1:%[0-9]+]]:_(s32) = G_USUBSAT [[UV1]], [[UV3]]
+ ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[USUBSAT]](s32), [[USUBSAT1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index ba672883fa56..7b88123b2c9b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -39,14 +39,8 @@ define i7 @v_saddsat_i7(i7 %lhs, i7 %rhs) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 9, v0
-; GFX9-NEXT: v_min_i16_e32 v3, 0, v0
-; GFX9-NEXT: v_max_i16_e32 v2, 0, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 9, v1
-; GFX9-NEXT: v_sub_u16_e32 v3, 0x8000, v3
-; GFX9-NEXT: v_sub_u16_e32 v2, 0x7fff, v2
-; GFX9-NEXT: v_max_i16_e32 v1, v3, v1
-; GFX9-NEXT: v_min_i16_e32 v1, v1, v2
-; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 9, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -57,13 +51,7 @@ define i7 @v_saddsat_i7(i7 %lhs, i7 %rhs) {
; GFX10-NEXT: v_lshlrev_b16_e64 v0, 9, v0
; GFX10-NEXT: v_lshlrev_b16_e64 v1, 9, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_i16_e64 v2, v0, 0
-; GFX10-NEXT: v_max_i16_e64 v3, v0, 0
-; GFX10-NEXT: v_sub_nc_u16_e64 v2, 0x8000, v2
-; GFX10-NEXT: v_sub_nc_u16_e64 v3, 0x7fff, v3
-; GFX10-NEXT: v_max_i16_e64 v1, v2, v1
-; GFX10-NEXT: v_min_i16_e64 v1, v1, v3
-; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1
+; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp
; GFX10-NEXT: v_ashrrev_i16_e64 v0, 9, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs)
@@ -118,54 +106,23 @@ define amdgpu_ps i7 @s_saddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX9-LABEL: s_saddsat_i7:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s2, 9, 0x100000
-; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
-; GFX9-NEXT: s_sext_i32_i16 s3, s0
-; GFX9-NEXT: s_sext_i32_i16 s4, 0
-; GFX9-NEXT: s_cmp_gt_i32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s5, s3, s4
-; GFX9-NEXT: s_sub_i32 s5, 0x7fff, s5
-; GFX9-NEXT: s_cmp_lt_i32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s3, s3, s4
-; GFX9-NEXT: s_sub_i32 s3, 0xffff8000, s3
-; GFX9-NEXT: s_sext_i32_i16 s3, s3
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_cmp_gt_i32 s3, s1
-; GFX9-NEXT: s_cselect_b32 s1, s3, s1
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_sext_i32_i16 s3, s5
-; GFX9-NEXT: s_cmp_lt_i32 s1, s3
-; GFX9-NEXT: s_cselect_b32 s1, s1, s3
-; GFX9-NEXT: s_add_i32 s0, s0, s1
-; GFX9-NEXT: s_sext_i32_i16 s0, s0
-; GFX9-NEXT: s_ashr_i32 s0, s0, s2
+; GFX9-NEXT: s_lshl_b32 s0, s0, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_ashrrev_i16_e32 v0, 9, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_i7:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s2, 9, 0x100000
-; GFX10-NEXT: s_sext_i32_i16 s4, 0
+; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_lshl_b32 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: s_sext_i32_i16 s3, s0
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_gt_i32 s3, s4
-; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s5, s3, s4
-; GFX10-NEXT: s_sub_i32 s5, 0x7fff, s5
-; GFX10-NEXT: s_cmp_lt_i32 s3, s4
-; GFX10-NEXT: s_cselect_b32 s3, s3, s4
-; GFX10-NEXT: s_sub_i32 s3, 0xffff8000, s3
-; GFX10-NEXT: s_sext_i32_i16 s3, s3
-; GFX10-NEXT: s_cmp_gt_i32 s3, s1
-; GFX10-NEXT: s_cselect_b32 s1, s3, s1
-; GFX10-NEXT: s_sext_i32_i16 s3, s5
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s3
-; GFX10-NEXT: s_cselect_b32 s1, s1, s3
-; GFX10-NEXT: s_add_i32 s0, s0, s1
-; GFX10-NEXT: s_sext_i32_i16 s0, s0
-; GFX10-NEXT: s_ashr_i32 s0, s0, s2
+; GFX10-NEXT: v_add_nc_i16 v0, s0, s1 clamp
+; GFX10-NEXT: v_ashrrev_i16_e64 v0, 9, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result
@@ -206,14 +163,8 @@ define i8 @v_saddsat_i8(i8 %lhs, i8 %rhs) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX9-NEXT: v_min_i16_e32 v3, 0, v0
-; GFX9-NEXT: v_max_i16_e32 v2, 0, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX9-NEXT: v_sub_u16_e32 v3, 0x8000, v3
-; GFX9-NEXT: v_sub_u16_e32 v2, 0x7fff, v2
-; GFX9-NEXT: v_max_i16_e32 v1, v3, v1
-; GFX9-NEXT: v_min_i16_e32 v1, v1, v2
-; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -224,13 +175,7 @@ define i8 @v_saddsat_i8(i8 %lhs, i8 %rhs) {
; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0
; GFX10-NEXT: v_lshlrev_b16_e64 v1, 8, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_i16_e64 v2, v0, 0
-; GFX10-NEXT: v_max_i16_e64 v3, v0, 0
-; GFX10-NEXT: v_sub_nc_u16_e64 v2, 0x8000, v2
-; GFX10-NEXT: v_sub_nc_u16_e64 v3, 0x7fff, v3
-; GFX10-NEXT: v_max_i16_e64 v1, v2, v1
-; GFX10-NEXT: v_min_i16_e64 v1, v1, v3
-; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1
+; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp
; GFX10-NEXT: v_ashrrev_i16_e64 v0, 8, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
@@ -285,54 +230,23 @@ define amdgpu_ps i8 @s_saddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX9-LABEL: s_saddsat_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s2, 8, 0x100000
-; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
-; GFX9-NEXT: s_sext_i32_i16 s3, s0
-; GFX9-NEXT: s_sext_i32_i16 s4, 0
-; GFX9-NEXT: s_cmp_gt_i32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s5, s3, s4
-; GFX9-NEXT: s_sub_i32 s5, 0x7fff, s5
-; GFX9-NEXT: s_cmp_lt_i32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s3, s3, s4
-; GFX9-NEXT: s_sub_i32 s3, 0xffff8000, s3
-; GFX9-NEXT: s_sext_i32_i16 s3, s3
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_cmp_gt_i32 s3, s1
-; GFX9-NEXT: s_cselect_b32 s1, s3, s1
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_sext_i32_i16 s3, s5
-; GFX9-NEXT: s_cmp_lt_i32 s1, s3
-; GFX9-NEXT: s_cselect_b32 s1, s1, s3
-; GFX9-NEXT: s_add_i32 s0, s0, s1
-; GFX9-NEXT: s_sext_i32_i16 s0, s0
-; GFX9-NEXT: s_ashr_i32 s0, s0, s2
+; GFX9-NEXT: s_lshl_b32 s0, s0, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000
-; GFX10-NEXT: s_sext_i32_i16 s4, 0
+; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_lshl_b32 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: s_sext_i32_i16 s3, s0
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_gt_i32 s3, s4
-; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s5, s3, s4
-; GFX10-NEXT: s_sub_i32 s5, 0x7fff, s5
-; GFX10-NEXT: s_cmp_lt_i32 s3, s4
-; GFX10-NEXT: s_cselect_b32 s3, s3, s4
-; GFX10-NEXT: s_sub_i32 s3, 0xffff8000, s3
-; GFX10-NEXT: s_sext_i32_i16 s3, s3
-; GFX10-NEXT: s_cmp_gt_i32 s3, s1
-; GFX10-NEXT: s_cselect_b32 s1, s3, s1
-; GFX10-NEXT: s_sext_i32_i16 s3, s5
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s3
-; GFX10-NEXT: s_cselect_b32 s1, s1, s3
-; GFX10-NEXT: s_add_i32 s0, s0, s1
-; GFX10-NEXT: s_sext_i32_i16 s0, s0
-; GFX10-NEXT: s_ashr_i32 s0, s0, s2
+; GFX10-NEXT: v_add_nc_i16 v0, s0, s1 clamp
+; GFX10-NEXT: v_ashrrev_i16_e64 v0, 8, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result
@@ -408,26 +322,12 @@ define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX9-NEXT: s_movk_i32 s5, 0x8000
-; GFX9-NEXT: v_min_i16_e32 v5, 0, v0
; GFX9-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX9-NEXT: v_sub_u16_e32 v5, s5, v5
-; GFX9-NEXT: s_movk_i32 s4, 0x7fff
-; GFX9-NEXT: v_max_i16_e32 v4, 0, v0
-; GFX9-NEXT: v_sub_u16_e32 v4, s4, v4
-; GFX9-NEXT: v_max_i16_e32 v1, v5, v1
-; GFX9-NEXT: v_min_i16_e32 v1, v1, v4
-; GFX9-NEXT: v_min_i16_e32 v4, 0, v2
-; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX9-NEXT: v_max_i16_e32 v1, 0, v2
-; GFX9-NEXT: v_sub_u16_e32 v4, s5, v4
-; GFX9-NEXT: v_sub_u16_e32 v1, s4, v1
-; GFX9-NEXT: v_max_i16_e32 v3, v4, v3
-; GFX9-NEXT: v_min_i16_e32 v1, v3, v1
+; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp
; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: v_add_u16_e32 v1, v2, v1
+; GFX9-NEXT: v_add_i16 v1, v2, v3 clamp
; GFX9-NEXT: v_and_b32_sdwa v0, sext(v0), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
@@ -438,31 +338,17 @@ define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8
-; GFX10-NEXT: v_lshlrev_b16_e64 v2, 8, v0
-; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: s_movk_i32 s5, 0x8000
-; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_lshlrev_b16_e64 v1, 8, v1
-; GFX10-NEXT: v_min_i16_e64 v4, v2, 0
-; GFX10-NEXT: v_min_i16_e64 v5, v0, 0
-; GFX10-NEXT: v_max_i16_e64 v6, v2, 0
-; GFX10-NEXT: v_max_i16_e64 v7, v0, 0
-; GFX10-NEXT: s_movk_i32 s4, 0x7fff
-; GFX10-NEXT: v_sub_nc_u16_e64 v4, s5, v4
-; GFX10-NEXT: v_sub_nc_u16_e64 v5, s5, v5
-; GFX10-NEXT: v_sub_nc_u16_e64 v6, s4, v6
-; GFX10-NEXT: v_sub_nc_u16_e64 v7, s4, v7
+; GFX10-NEXT: v_lshlrev_b16_e64 v3, 8, v1
+; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0
; GFX10-NEXT: s_movk_i32 s4, 0xff
-; GFX10-NEXT: v_max_i16_e64 v1, v4, v1
-; GFX10-NEXT: v_max_i16_e64 v10, v5, v3
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_i16_e64 v1, v1, v6
-; GFX10-NEXT: v_min_i16_e64 v3, v10, v7
-; GFX10-NEXT: v_add_nc_u16_e64 v1, v2, v1
-; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v3
-; GFX10-NEXT: v_and_b32_sdwa v1, sext(v1), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX10-NEXT: v_add_nc_i16 v1, v2, v1 clamp
+; GFX10-NEXT: v_add_nc_i16 v0, v0, v3 clamp
+; GFX10-NEXT: v_and_b32_sdwa v1, sext(v1), s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
@@ -571,112 +457,40 @@ define amdgpu_ps i16 @s_saddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX9-LABEL: s_saddsat_v2i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s4, 8, 0x100000
-; GFX9-NEXT: s_lshr_b32 s2, s0, 8
-; GFX9-NEXT: s_lshl_b32 s0, s0, s4
; GFX9-NEXT: s_lshr_b32 s3, s1, 8
; GFX9-NEXT: s_lshl_b32 s1, s1, s4
-; GFX9-NEXT: s_sext_i32_i16 s7, s0
-; GFX9-NEXT: s_sext_i32_i16 s8, 0
-; GFX9-NEXT: s_cmp_gt_i32 s7, s8
-; GFX9-NEXT: s_movk_i32 s5, 0x7fff
-; GFX9-NEXT: s_cselect_b32 s9, s7, s8
-; GFX9-NEXT: s_sub_i32 s9, s5, s9
-; GFX9-NEXT: s_cmp_lt_i32 s7, s8
-; GFX9-NEXT: s_movk_i32 s6, 0x8000
-; GFX9-NEXT: s_cselect_b32 s7, s7, s8
-; GFX9-NEXT: s_sub_i32 s7, s6, s7
-; GFX9-NEXT: s_sext_i32_i16 s7, s7
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_cmp_gt_i32 s7, s1
-; GFX9-NEXT: s_cselect_b32 s1, s7, s1
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_sext_i32_i16 s7, s9
-; GFX9-NEXT: s_cmp_lt_i32 s1, s7
-; GFX9-NEXT: s_cselect_b32 s1, s1, s7
-; GFX9-NEXT: s_add_i32 s0, s0, s1
-; GFX9-NEXT: s_sext_i32_i16 s0, s0
-; GFX9-NEXT: s_lshl_b32 s1, s2, s4
-; GFX9-NEXT: s_lshl_b32 s2, s3, s4
-; GFX9-NEXT: s_ashr_i32 s0, s0, s4
-; GFX9-NEXT: s_sext_i32_i16 s3, s1
-; GFX9-NEXT: s_cmp_gt_i32 s3, s8
-; GFX9-NEXT: s_cselect_b32 s7, s3, s8
-; GFX9-NEXT: s_sub_i32 s5, s5, s7
-; GFX9-NEXT: s_cmp_lt_i32 s3, s8
-; GFX9-NEXT: s_cselect_b32 s3, s3, s8
-; GFX9-NEXT: s_sub_i32 s3, s6, s3
-; GFX9-NEXT: s_sext_i32_i16 s3, s3
-; GFX9-NEXT: s_sext_i32_i16 s2, s2
-; GFX9-NEXT: s_cmp_gt_i32 s3, s2
-; GFX9-NEXT: s_cselect_b32 s2, s3, s2
-; GFX9-NEXT: s_sext_i32_i16 s2, s2
-; GFX9-NEXT: s_sext_i32_i16 s3, s5
-; GFX9-NEXT: s_cmp_lt_i32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s2, s3
-; GFX9-NEXT: s_add_i32 s1, s1, s2
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_movk_i32 s2, 0xff
-; GFX9-NEXT: s_ashr_i32 s1, s1, s4
-; GFX9-NEXT: s_and_b32 s1, s1, s2
-; GFX9-NEXT: s_and_b32 s0, s0, s2
-; GFX9-NEXT: s_lshl_b32 s1, s1, s4
-; GFX9-NEXT: s_or_b32 s0, s0, s1
+; GFX9-NEXT: s_lshr_b32 s2, s0, 8
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: s_lshl_b32 s0, s0, s4
+; GFX9-NEXT: s_lshl_b32 s1, s3, s4
+; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp
+; GFX9-NEXT: s_lshl_b32 s0, s2, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_add_i16 v1, s0, v1 clamp
+; GFX9-NEXT: s_movk_i32 s0, 0xff
+; GFX9-NEXT: v_and_b32_sdwa v0, sext(v0), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_v2i8:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000
-; GFX10-NEXT: s_lshr_b32 s3, s0, 8
-; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_sext_i32_i16 s6, 0
-; GFX10-NEXT: s_sext_i32_i16 s5, s0
+; GFX10-NEXT: s_lshr_b32 s2, s0, 8
+; GFX10-NEXT: s_bfe_u32 s3, 8, 0x100000
; GFX10-NEXT: s_lshr_b32 s4, s1, 8
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: s_cmp_gt_i32 s5, s6
-; GFX10-NEXT: s_movk_i32 s7, 0x7fff
-; GFX10-NEXT: s_cselect_b32 s8, s5, s6
-; GFX10-NEXT: s_movk_i32 s9, 0x8000
-; GFX10-NEXT: s_sub_i32 s8, s7, s8
-; GFX10-NEXT: s_cmp_lt_i32 s5, s6
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cselect_b32 s5, s5, s6
+; GFX10-NEXT: s_lshl_b32 s0, s0, s3
+; GFX10-NEXT: s_lshl_b32 s1, s1, s3
+; GFX10-NEXT: s_lshl_b32 s2, s2, s3
+; GFX10-NEXT: s_lshl_b32 s3, s4, s3
+; GFX10-NEXT: v_add_nc_i16 v0, s0, s1 clamp
+; GFX10-NEXT: v_add_nc_i16 v1, s2, s3 clamp
+; GFX10-NEXT: s_movk_i32 s0, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_sub_i32 s5, s9, s5
-; GFX10-NEXT: s_sext_i32_i16 s5, s5
-; GFX10-NEXT: s_cmp_gt_i32 s5, s1
-; GFX10-NEXT: s_cselect_b32 s1, s5, s1
-; GFX10-NEXT: s_sext_i32_i16 s5, s8
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s5
-; GFX10-NEXT: s_cselect_b32 s1, s1, s5
-; GFX10-NEXT: s_lshl_b32 s3, s3, s2
-; GFX10-NEXT: s_add_i32 s0, s0, s1
-; GFX10-NEXT: s_lshl_b32 s1, s4, s2
-; GFX10-NEXT: s_sext_i32_i16 s0, s0
-; GFX10-NEXT: s_sext_i32_i16 s4, s3
-; GFX10-NEXT: s_ashr_i32 s0, s0, s2
-; GFX10-NEXT: s_cmp_gt_i32 s4, s6
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cselect_b32 s5, s4, s6
-; GFX10-NEXT: s_sub_i32 s5, s7, s5
-; GFX10-NEXT: s_cmp_lt_i32 s4, s6
-; GFX10-NEXT: s_cselect_b32 s4, s4, s6
-; GFX10-NEXT: s_sub_i32 s4, s9, s4
-; GFX10-NEXT: s_sext_i32_i16 s4, s4
-; GFX10-NEXT: s_cmp_gt_i32 s4, s1
-; GFX10-NEXT: s_cselect_b32 s1, s4, s1
-; GFX10-NEXT: s_sext_i32_i16 s4, s5
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s4
-; GFX10-NEXT: s_cselect_b32 s1, s1, s4
-; GFX10-NEXT: s_add_i32 s3, s3, s1
-; GFX10-NEXT: s_sext_i32_i16 s1, s3
-; GFX10-NEXT: s_movk_i32 s3, 0xff
-; GFX10-NEXT: s_ashr_i32 s1, s1, s2
-; GFX10-NEXT: s_and_b32 s0, s0, s3
-; GFX10-NEXT: s_and_b32 s1, s1, s3
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: s_or_b32 s0, s0, s1
+; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v1, sext(v1), s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
@@ -815,52 +629,25 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 24, v0
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX9-NEXT: s_movk_i32 s5, 0x8000
-; GFX9-NEXT: v_min_i16_e32 v10, 0, v0
-; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX9-NEXT: v_sub_u16_e32 v10, s5, v10
-; GFX9-NEXT: s_movk_i32 s4, 0x7fff
-; GFX9-NEXT: v_max_i16_e32 v8, 0, v0
-; GFX9-NEXT: v_sub_u16_e32 v8, s4, v8
-; GFX9-NEXT: v_max_i16_e32 v1, v10, v1
-; GFX9-NEXT: v_min_i16_e32 v1, v1, v8
-; GFX9-NEXT: v_min_i16_e32 v8, 0, v2
-; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX9-NEXT: v_max_i16_e32 v1, 0, v2
-; GFX9-NEXT: v_sub_u16_e32 v8, s5, v8
-; GFX9-NEXT: v_sub_u16_e32 v1, s4, v1
-; GFX9-NEXT: v_max_i16_e32 v5, v8, v5
-; GFX9-NEXT: v_min_i16_e32 v1, v5, v1
-; GFX9-NEXT: v_add_u16_e32 v1, v2, v1
+; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp
+; GFX9-NEXT: v_add_i16 v1, v2, v5 clamp
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v6
-; GFX9-NEXT: v_min_i16_e32 v6, 0, v2
-; GFX9-NEXT: v_sub_u16_e32 v6, s5, v6
-; GFX9-NEXT: v_mov_b32_e32 v9, 0x7fff
-; GFX9-NEXT: v_max_i16_e32 v5, 0, v2
-; GFX9-NEXT: v_sub_u16_e32 v5, v9, v5
-; GFX9-NEXT: v_max_i16_e32 v3, v6, v3
-; GFX9-NEXT: v_min_i16_e32 v3, v3, v5
-; GFX9-NEXT: v_add_u16_e32 v2, v2, v3
-; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v4
-; GFX9-NEXT: v_min_i16_e32 v6, 0, v3
-; GFX9-NEXT: v_max_i16_e32 v5, 0, v3
-; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v7
-; GFX9-NEXT: v_sub_u16_e32 v6, 0x8000, v6
; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: v_sub_u16_e32 v5, v9, v5
-; GFX9-NEXT: v_max_i16_e32 v4, v6, v4
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX9-NEXT: v_min_i16_e32 v4, v4, v5
+; GFX9-NEXT: v_add_i16 v2, v2, v3 clamp
+; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v4
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v7
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX9-NEXT: v_add_u16_e32 v3, v3, v4
+; GFX9-NEXT: v_add_i16 v3, v3, v4 clamp
; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v1
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v2), s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v2, sext(v3), s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
@@ -871,57 +658,30 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_lshlrev_b16_e64 v4, 8, v0
; GFX10-NEXT: s_mov_b32 s4, 8
-; GFX10-NEXT: s_mov_b32 s5, 16
+; GFX10-NEXT: v_lshlrev_b16_e64 v5, 8, v0
; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s5, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_min_i16_e64 v8, v4, 0
-; GFX10-NEXT: v_lshrrev_b32_sdwa v6, s5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: s_movk_i32 s5, 0x8000
-; GFX10-NEXT: v_min_i16_e64 v9, v2, 0
-; GFX10-NEXT: v_lshlrev_b16_e64 v7, 8, v1
-; GFX10-NEXT: v_sub_nc_u16_e64 v8, s5, v8
-; GFX10-NEXT: v_max_i16_e64 v10, v4, 0
-; GFX10-NEXT: s_mov_b32 s6, 24
-; GFX10-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: s_movk_i32 s4, 0x7fff
-; GFX10-NEXT: v_sub_nc_u16_e64 v15, s5, v9
-; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s6, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_max_i16_e64 v11, v2, 0
-; GFX10-NEXT: v_max_i16_e64 v7, v8, v7
-; GFX10-NEXT: v_sub_nc_u16_e64 v10, s4, v10
-; GFX10-NEXT: v_max_i16_e64 v5, v15, v5
-; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s6, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_sub_nc_u16_e64 v8, s4, v11
-; GFX10-NEXT: v_min_i16_e64 v11, v3, 0
-; GFX10-NEXT: v_min_i16_e64 v7, v7, v10
-; GFX10-NEXT: v_min_i16_e64 v10, v0, 0
-; GFX10-NEXT: v_mov_b32_e32 v9, 0x7fff
-; GFX10-NEXT: v_min_i16_e64 v5, v5, v8
-; GFX10-NEXT: v_sub_nc_u16_e64 v11, s5, v11
-; GFX10-NEXT: v_max_i16_e64 v8, v3, 0
-; GFX10-NEXT: v_sub_nc_u16_e64 v10, 0x8000, v10
-; GFX10-NEXT: v_max_i16_e64 v12, v0, 0
-; GFX10-NEXT: v_add_nc_u16_e64 v2, v2, v5
-; GFX10-NEXT: v_max_i16_e64 v6, v11, v6
-; GFX10-NEXT: v_sub_nc_u16_e64 v5, v9, v8
-; GFX10-NEXT: v_max_i16_e64 v1, v10, v1
-; GFX10-NEXT: v_sub_nc_u16_e64 v8, v9, v12
-; GFX10-NEXT: s_movk_i32 s4, 0xff
-; GFX10-NEXT: v_add_nc_u16_e64 v4, v4, v7
-; GFX10-NEXT: v_and_b32_sdwa v2, sext(v2), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_min_i16_e64 v5, v6, v5
-; GFX10-NEXT: v_min_i16_e64 v1, v1, v8
+; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshlrev_b16_e64 v6, 8, v1
+; GFX10-NEXT: s_mov_b32 s5, 16
+; GFX10-NEXT: s_mov_b32 s4, 24
+; GFX10-NEXT: v_lshrrev_b32_sdwa v4, s5, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_add_nc_i16 v2, v2, v3 clamp
+; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: s_movk_i32 s5, 0xff
+; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v2, sext(v2), s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_add_nc_i16 v5, v5, v6 clamp
+; GFX10-NEXT: v_add_nc_i16 v3, v4, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_ashrrev_i16_e64 v4, 8, v4
+; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; GFX10-NEXT: v_add_nc_u16_e64 v3, v3, v5
-; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1
-; GFX10-NEXT: v_and_or_b32 v1, v4, s4, v2
-; GFX10-NEXT: v_and_b32_sdwa v2, sext(v3), s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0
+; GFX10-NEXT: v_ashrrev_i16_e64 v4, 8, v5
+; GFX10-NEXT: v_and_b32_sdwa v1, sext(v3), s5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s5 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_or_b32 v2, v4, s5, v2
+; GFX10-NEXT: v_or3_b32 v0, v2, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
@@ -1118,212 +878,70 @@ define amdgpu_ps i32 @s_saddsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX9-LABEL: s_saddsat_v4i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s8, 8, 0x100000
-; GFX9-NEXT: s_lshr_b32 s2, s0, 8
-; GFX9-NEXT: s_lshr_b32 s3, s0, 16
-; GFX9-NEXT: s_lshr_b32 s4, s0, 24
-; GFX9-NEXT: s_lshl_b32 s0, s0, s8
; GFX9-NEXT: s_lshr_b32 s5, s1, 8
; GFX9-NEXT: s_lshr_b32 s6, s1, 16
; GFX9-NEXT: s_lshr_b32 s7, s1, 24
; GFX9-NEXT: s_lshl_b32 s1, s1, s8
-; GFX9-NEXT: s_sext_i32_i16 s11, s0
-; GFX9-NEXT: s_sext_i32_i16 s12, 0
-; GFX9-NEXT: s_cmp_gt_i32 s11, s12
-; GFX9-NEXT: s_movk_i32 s9, 0x7fff
-; GFX9-NEXT: s_cselect_b32 s13, s11, s12
-; GFX9-NEXT: s_sub_i32 s13, s9, s13
-; GFX9-NEXT: s_cmp_lt_i32 s11, s12
-; GFX9-NEXT: s_movk_i32 s10, 0x8000
-; GFX9-NEXT: s_cselect_b32 s11, s11, s12
-; GFX9-NEXT: s_sub_i32 s11, s10, s11
-; GFX9-NEXT: s_sext_i32_i16 s11, s11
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_cmp_gt_i32 s11, s1
-; GFX9-NEXT: s_cselect_b32 s1, s11, s1
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_sext_i32_i16 s11, s13
-; GFX9-NEXT: s_cmp_lt_i32 s1, s11
-; GFX9-NEXT: s_cselect_b32 s1, s1, s11
-; GFX9-NEXT: s_add_i32 s0, s0, s1
-; GFX9-NEXT: s_sext_i32_i16 s0, s0
-; GFX9-NEXT: s_lshl_b32 s1, s2, s8
-; GFX9-NEXT: s_lshl_b32 s2, s5, s8
-; GFX9-NEXT: s_ashr_i32 s0, s0, s8
-; GFX9-NEXT: s_sext_i32_i16 s5, s1
-; GFX9-NEXT: s_cmp_gt_i32 s5, s12
-; GFX9-NEXT: s_cselect_b32 s11, s5, s12
-; GFX9-NEXT: s_sub_i32 s11, s9, s11
-; GFX9-NEXT: s_cmp_lt_i32 s5, s12
-; GFX9-NEXT: s_cselect_b32 s5, s5, s12
-; GFX9-NEXT: s_sub_i32 s5, s10, s5
-; GFX9-NEXT: s_sext_i32_i16 s5, s5
-; GFX9-NEXT: s_sext_i32_i16 s2, s2
-; GFX9-NEXT: s_cmp_gt_i32 s5, s2
-; GFX9-NEXT: s_cselect_b32 s2, s5, s2
-; GFX9-NEXT: s_sext_i32_i16 s2, s2
-; GFX9-NEXT: s_sext_i32_i16 s5, s11
-; GFX9-NEXT: s_cmp_lt_i32 s2, s5
-; GFX9-NEXT: s_cselect_b32 s2, s2, s5
-; GFX9-NEXT: s_add_i32 s1, s1, s2
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_lshl_b32 s2, s3, s8
-; GFX9-NEXT: s_lshl_b32 s3, s6, s8
-; GFX9-NEXT: s_ashr_i32 s1, s1, s8
-; GFX9-NEXT: s_sext_i32_i16 s5, s2
-; GFX9-NEXT: s_cmp_gt_i32 s5, s12
-; GFX9-NEXT: s_cselect_b32 s6, s5, s12
-; GFX9-NEXT: s_sub_i32 s6, s9, s6
-; GFX9-NEXT: s_cmp_lt_i32 s5, s12
-; GFX9-NEXT: s_cselect_b32 s5, s5, s12
-; GFX9-NEXT: s_sub_i32 s5, s10, s5
-; GFX9-NEXT: s_sext_i32_i16 s5, s5
-; GFX9-NEXT: s_sext_i32_i16 s3, s3
-; GFX9-NEXT: s_cmp_gt_i32 s5, s3
-; GFX9-NEXT: s_cselect_b32 s3, s5, s3
-; GFX9-NEXT: s_sext_i32_i16 s3, s3
-; GFX9-NEXT: s_sext_i32_i16 s5, s6
-; GFX9-NEXT: s_cmp_lt_i32 s3, s5
-; GFX9-NEXT: s_cselect_b32 s3, s3, s5
-; GFX9-NEXT: s_add_i32 s2, s2, s3
-; GFX9-NEXT: s_sext_i32_i16 s2, s2
-; GFX9-NEXT: s_lshl_b32 s3, s4, s8
-; GFX9-NEXT: s_lshl_b32 s4, s7, s8
-; GFX9-NEXT: s_ashr_i32 s2, s2, s8
-; GFX9-NEXT: s_sext_i32_i16 s5, s3
-; GFX9-NEXT: s_cmp_gt_i32 s5, s12
-; GFX9-NEXT: s_cselect_b32 s6, s5, s12
-; GFX9-NEXT: s_sub_i32 s6, s9, s6
-; GFX9-NEXT: s_cmp_lt_i32 s5, s12
-; GFX9-NEXT: s_cselect_b32 s5, s5, s12
-; GFX9-NEXT: s_sub_i32 s5, s10, s5
-; GFX9-NEXT: s_sext_i32_i16 s5, s5
-; GFX9-NEXT: s_sext_i32_i16 s4, s4
-; GFX9-NEXT: s_cmp_gt_i32 s5, s4
-; GFX9-NEXT: s_cselect_b32 s4, s5, s4
-; GFX9-NEXT: s_sext_i32_i16 s4, s4
-; GFX9-NEXT: s_sext_i32_i16 s5, s6
-; GFX9-NEXT: s_cmp_lt_i32 s4, s5
-; GFX9-NEXT: s_cselect_b32 s4, s4, s5
-; GFX9-NEXT: s_add_i32 s3, s3, s4
-; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: s_and_b32 s1, s1, s4
-; GFX9-NEXT: s_and_b32 s0, s0, s4
-; GFX9-NEXT: s_lshl_b32 s1, s1, 8
-; GFX9-NEXT: s_sext_i32_i16 s3, s3
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: s_and_b32 s1, s2, s4
-; GFX9-NEXT: s_lshl_b32 s1, s1, 16
-; GFX9-NEXT: s_ashr_i32 s3, s3, s8
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: s_and_b32 s1, s3, s4
-; GFX9-NEXT: s_lshl_b32 s1, s1, 24
-; GFX9-NEXT: s_or_b32 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: s_lshl_b32 s1, s5, s8
+; GFX9-NEXT: s_lshr_b32 s2, s0, 8
+; GFX9-NEXT: s_lshr_b32 s3, s0, 16
+; GFX9-NEXT: s_lshr_b32 s4, s0, 24
+; GFX9-NEXT: s_lshl_b32 s0, s0, s8
+; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: s_lshl_b32 s0, s2, s8
+; GFX9-NEXT: s_lshl_b32 s1, s6, s8
+; GFX9-NEXT: v_add_i16 v1, s0, v1 clamp
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-NEXT: s_lshl_b32 s0, s3, s8
+; GFX9-NEXT: s_lshl_b32 s1, s7, s8
+; GFX9-NEXT: v_add_i16 v2, s0, v2 clamp
+; GFX9-NEXT: s_lshl_b32 s0, s4, s8
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_add_i16 v3, s0, v3 clamp
+; GFX9-NEXT: s_movk_i32 s0, 0xff
+; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v1
+; GFX9-NEXT: v_and_b32_sdwa v1, sext(v2), s0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_sdwa v2, sext(v3), s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_v4i8:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s6, 8, 0x100000
+; GFX10-NEXT: s_bfe_u32 s5, 8, 0x100000
; GFX10-NEXT: s_lshr_b32 s2, s0, 8
+; GFX10-NEXT: s_lshr_b32 s6, s1, 8
+; GFX10-NEXT: s_lshl_b32 s2, s2, s5
+; GFX10-NEXT: s_lshl_b32 s6, s6, s5
; GFX10-NEXT: s_lshr_b32 s3, s0, 16
+; GFX10-NEXT: v_add_nc_i16 v1, s2, s6 clamp
; GFX10-NEXT: s_lshr_b32 s4, s0, 24
-; GFX10-NEXT: s_lshl_b32 s0, s0, s6
-; GFX10-NEXT: s_sext_i32_i16 s10, 0
-; GFX10-NEXT: s_sext_i32_i16 s9, s0
-; GFX10-NEXT: s_lshr_b32 s5, s1, 8
-; GFX10-NEXT: s_lshr_b32 s7, s1, 16
-; GFX10-NEXT: s_lshr_b32 s8, s1, 24
-; GFX10-NEXT: s_lshl_b32 s1, s1, s6
-; GFX10-NEXT: s_cmp_gt_i32 s9, s10
-; GFX10-NEXT: s_movk_i32 s11, 0x7fff
-; GFX10-NEXT: s_cselect_b32 s12, s9, s10
-; GFX10-NEXT: s_movk_i32 s13, 0x8000
-; GFX10-NEXT: s_sub_i32 s12, s11, s12
-; GFX10-NEXT: s_cmp_lt_i32 s9, s10
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cselect_b32 s9, s9, s10
+; GFX10-NEXT: s_movk_i32 s2, 0xff
+; GFX10-NEXT: s_lshl_b32 s0, s0, s5
+; GFX10-NEXT: s_lshl_b32 s7, s1, s5
+; GFX10-NEXT: v_and_b32_sdwa v1, sext(v1), s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_add_nc_i16 v0, s0, s7 clamp
+; GFX10-NEXT: s_lshr_b32 s0, s1, 16
+; GFX10-NEXT: s_lshr_b32 s1, s1, 24
+; GFX10-NEXT: s_lshl_b32 s3, s3, s5
+; GFX10-NEXT: s_lshl_b32 s0, s0, s5
+; GFX10-NEXT: s_lshl_b32 s4, s4, s5
+; GFX10-NEXT: s_lshl_b32 s1, s1, s5
+; GFX10-NEXT: v_ashrrev_i16_e64 v0, 8, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX10-NEXT: v_add_nc_i16 v2, s3, s0 clamp
+; GFX10-NEXT: v_add_nc_i16 v3, s4, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_sub_i32 s9, s13, s9
-; GFX10-NEXT: s_sext_i32_i16 s9, s9
-; GFX10-NEXT: s_cmp_gt_i32 s9, s1
-; GFX10-NEXT: s_cselect_b32 s1, s9, s1
-; GFX10-NEXT: s_sext_i32_i16 s9, s12
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s9
-; GFX10-NEXT: s_cselect_b32 s1, s1, s9
-; GFX10-NEXT: s_lshl_b32 s5, s5, s6
-; GFX10-NEXT: s_add_i32 s0, s0, s1
-; GFX10-NEXT: s_lshl_b32 s1, s2, s6
-; GFX10-NEXT: s_sext_i32_i16 s0, s0
-; GFX10-NEXT: s_sext_i32_i16 s2, s1
-; GFX10-NEXT: s_ashr_i32 s0, s0, s6
-; GFX10-NEXT: s_cmp_gt_i32 s2, s10
-; GFX10-NEXT: s_sext_i32_i16 s5, s5
-; GFX10-NEXT: s_cselect_b32 s9, s2, s10
-; GFX10-NEXT: s_sub_i32 s9, s11, s9
-; GFX10-NEXT: s_cmp_lt_i32 s2, s10
-; GFX10-NEXT: s_cselect_b32 s2, s2, s10
-; GFX10-NEXT: s_sub_i32 s2, s13, s2
-; GFX10-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-NEXT: s_cmp_gt_i32 s2, s5
-; GFX10-NEXT: s_cselect_b32 s2, s2, s5
-; GFX10-NEXT: s_sext_i32_i16 s5, s9
-; GFX10-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-NEXT: s_cmp_lt_i32 s2, s5
-; GFX10-NEXT: s_cselect_b32 s2, s2, s5
-; GFX10-NEXT: s_lshl_b32 s3, s3, s6
-; GFX10-NEXT: s_add_i32 s1, s1, s2
-; GFX10-NEXT: s_sext_i32_i16 s5, s3
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_lshl_b32 s2, s7, s6
-; GFX10-NEXT: s_ashr_i32 s1, s1, s6
-; GFX10-NEXT: s_cmp_gt_i32 s5, s10
-; GFX10-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-NEXT: s_cselect_b32 s7, s5, s10
-; GFX10-NEXT: s_sub_i32 s7, s11, s7
-; GFX10-NEXT: s_cmp_lt_i32 s5, s10
-; GFX10-NEXT: s_cselect_b32 s5, s5, s10
-; GFX10-NEXT: s_sub_i32 s5, s13, s5
-; GFX10-NEXT: s_sext_i32_i16 s5, s5
-; GFX10-NEXT: s_cmp_gt_i32 s5, s2
-; GFX10-NEXT: s_cselect_b32 s2, s5, s2
-; GFX10-NEXT: s_sext_i32_i16 s5, s7
-; GFX10-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-NEXT: s_cmp_lt_i32 s2, s5
-; GFX10-NEXT: s_cselect_b32 s2, s2, s5
-; GFX10-NEXT: s_lshl_b32 s4, s4, s6
-; GFX10-NEXT: s_add_i32 s3, s3, s2
-; GFX10-NEXT: s_sext_i32_i16 s5, s4
-; GFX10-NEXT: s_sext_i32_i16 s3, s3
-; GFX10-NEXT: s_lshl_b32 s2, s8, s6
-; GFX10-NEXT: s_ashr_i32 s3, s3, s6
-; GFX10-NEXT: s_cmp_gt_i32 s5, s10
-; GFX10-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-NEXT: s_cselect_b32 s7, s5, s10
-; GFX10-NEXT: s_sub_i32 s7, s11, s7
-; GFX10-NEXT: s_cmp_lt_i32 s5, s10
-; GFX10-NEXT: s_cselect_b32 s5, s5, s10
-; GFX10-NEXT: s_sub_i32 s5, s13, s5
-; GFX10-NEXT: s_sext_i32_i16 s5, s5
-; GFX10-NEXT: s_cmp_gt_i32 s5, s2
-; GFX10-NEXT: s_cselect_b32 s2, s5, s2
-; GFX10-NEXT: s_sext_i32_i16 s5, s7
-; GFX10-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-NEXT: s_movk_i32 s7, 0xff
-; GFX10-NEXT: s_cmp_lt_i32 s2, s5
-; GFX10-NEXT: s_cselect_b32 s2, s2, s5
-; GFX10-NEXT: s_and_b32 s1, s1, s7
-; GFX10-NEXT: s_add_i32 s4, s4, s2
-; GFX10-NEXT: s_and_b32 s2, s3, s7
-; GFX10-NEXT: s_sext_i32_i16 s3, s4
-; GFX10-NEXT: s_and_b32 s0, s0, s7
-; GFX10-NEXT: s_lshl_b32 s1, s1, 8
-; GFX10-NEXT: s_ashr_i32 s3, s3, s6
-; GFX10-NEXT: s_or_b32 s0, s0, s1
-; GFX10-NEXT: s_lshl_b32 s1, s2, 16
-; GFX10-NEXT: s_and_b32 s2, s3, s7
-; GFX10-NEXT: s_or_b32 s0, s0, s1
-; GFX10-NEXT: s_lshl_b32 s1, s2, 24
-; GFX10-NEXT: s_or_b32 s0, s0, s1
+; GFX10-NEXT: v_and_or_b32 v0, v0, s2, v1
+; GFX10-NEXT: v_and_b32_sdwa v1, sext(v2), s2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v2, sext(v3), s2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
@@ -1368,14 +986,8 @@ define i24 @v_saddsat_i24(i24 %lhs, i24 %rhs) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX9-NEXT: v_min_i32_e32 v3, 0, v0
-; GFX9-NEXT: v_max_i32_e32 v2, 0, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX9-NEXT: v_sub_u32_e32 v3, 0x80000000, v3
-; GFX9-NEXT: v_sub_u32_e32 v2, 0x7fffffff, v2
-; GFX9-NEXT: v_max_i32_e32 v1, v3, v1
-; GFX9-NEXT: v_min_i32_e32 v1, v1, v2
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_i32 v0, v0, v1 clamp
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1386,13 +998,7 @@ define i24 @v_saddsat_i24(i24 %lhs, i24 %rhs) {
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_i32_e32 v2, 0, v0
-; GFX10-NEXT: v_max_i32_e32 v3, 0, v0
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, 0x80000000, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, 0x7fffffff, v3
-; GFX10-NEXT: v_max_i32_e32 v1, v2, v1
-; GFX10-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX10-NEXT: v_add_nc_i32 v0, v0, v1 clamp
; GFX10-NEXT: v_ashrrev_i32_e32 v0, 8, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.sadd.sat.i24(i24 %lhs, i24 %rhs)
@@ -1439,39 +1045,22 @@ define amdgpu_ps i24 @s_saddsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
;
; GFX9-LABEL: s_saddsat_i24:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshl_b32 s0, s0, 8
; GFX9-NEXT: s_lshl_b32 s1, s1, 8
-; GFX9-NEXT: s_cmp_gt_i32 s0, 0
-; GFX9-NEXT: s_cselect_b32 s2, s0, 0
-; GFX9-NEXT: s_sub_i32 s2, 0x7fffffff, s2
-; GFX9-NEXT: s_cmp_lt_i32 s0, 0
-; GFX9-NEXT: s_cselect_b32 s3, s0, 0
-; GFX9-NEXT: s_sub_i32 s3, 0x80000000, s3
-; GFX9-NEXT: s_cmp_gt_i32 s3, s1
-; GFX9-NEXT: s_cselect_b32 s1, s3, s1
-; GFX9-NEXT: s_cmp_lt_i32 s1, s2
-; GFX9-NEXT: s_cselect_b32 s1, s1, s2
-; GFX9-NEXT: s_add_i32 s0, s0, s1
-; GFX9-NEXT: s_ashr_i32 s0, s0, 8
+; GFX9-NEXT: s_lshl_b32 s0, s0, 8
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
+; GFX9-NEXT: v_ashrrev_i32_e32 v0, 8, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshl_b32 s0, s0, 8
; GFX10-NEXT: s_lshl_b32 s1, s1, 8
-; GFX10-NEXT: s_cmp_gt_i32 s0, 0
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s2, s0, 0
-; GFX10-NEXT: s_sub_i32 s2, 0x7fffffff, s2
-; GFX10-NEXT: s_cmp_lt_i32 s0, 0
-; GFX10-NEXT: s_cselect_b32 s3, s0, 0
-; GFX10-NEXT: s_sub_i32 s3, 0x80000000, s3
-; GFX10-NEXT: s_cmp_gt_i32 s3, s1
-; GFX10-NEXT: s_cselect_b32 s1, s3, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s2
-; GFX10-NEXT: s_cselect_b32 s1, s1, s2
-; GFX10-NEXT: s_add_i32 s0, s0, s1
-; GFX10-NEXT: s_ashr_i32 s0, s0, 8
+; GFX10-NEXT: v_add_nc_i32 v0, s0, s1 clamp
+; GFX10-NEXT: v_ashrrev_i32_e32 v0, 8, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i24 @llvm.sadd.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result
@@ -1505,27 +1094,15 @@ define i32 @v_saddsat_i32(i32 %lhs, i32 %rhs) {
; GFX9-LABEL: v_saddsat_i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_i32_e32 v3, 0, v0
-; GFX9-NEXT: v_max_i32_e32 v2, 0, v0
-; GFX9-NEXT: v_sub_u32_e32 v3, 0x80000000, v3
-; GFX9-NEXT: v_sub_u32_e32 v2, 0x7fffffff, v2
-; GFX9-NEXT: v_max_i32_e32 v1, v3, v1
-; GFX9-NEXT: v_min_i32_e32 v1, v1, v2
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_i32 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_saddsat_i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_min_i32_e32 v2, 0, v0
-; GFX10-NEXT: v_max_i32_e32 v3, 0, v0
+; GFX10-NEXT: v_add_nc_i32 v0, v0, v1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, 0x80000000, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, 0x7fffffff, v3
-; GFX10-NEXT: v_max_i32_e32 v1, v2, v1
-; GFX10-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
@@ -1579,33 +1156,16 @@ define amdgpu_ps i32 @s_saddsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
;
; GFX9-LABEL: s_saddsat_i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_gt_i32 s0, 0
-; GFX9-NEXT: s_cselect_b32 s2, s0, 0
-; GFX9-NEXT: s_sub_i32 s2, 0x7fffffff, s2
-; GFX9-NEXT: s_cmp_lt_i32 s0, 0
-; GFX9-NEXT: s_cselect_b32 s3, s0, 0
-; GFX9-NEXT: s_sub_i32 s3, 0x80000000, s3
-; GFX9-NEXT: s_cmp_gt_i32 s3, s1
-; GFX9-NEXT: s_cselect_b32 s1, s3, s1
-; GFX9-NEXT: s_cmp_lt_i32 s1, s2
-; GFX9-NEXT: s_cselect_b32 s1, s1, s2
-; GFX9-NEXT: s_add_i32 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_gt_i32 s0, 0
+; GFX10-NEXT: v_add_nc_i32 v0, s0, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s2, s0, 0
-; GFX10-NEXT: s_sub_i32 s2, 0x7fffffff, s2
-; GFX10-NEXT: s_cmp_lt_i32 s0, 0
-; GFX10-NEXT: s_cselect_b32 s3, s0, 0
-; GFX10-NEXT: s_sub_i32 s3, 0x80000000, s3
-; GFX10-NEXT: s_cmp_gt_i32 s3, s1
-; GFX10-NEXT: s_cselect_b32 s1, s3, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s2
-; GFX10-NEXT: s_cselect_b32 s1, s1, s2
-; GFX10-NEXT: s_add_i32 s0, s0, s1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
@@ -1640,29 +1200,13 @@ define amdgpu_ps float @saddsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
;
; GFX9-LABEL: saddsat_i32_sv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_gt_i32 s0, 0
-; GFX9-NEXT: s_cselect_b32 s1, s0, 0
-; GFX9-NEXT: s_sub_i32 s1, 0x7fffffff, s1
-; GFX9-NEXT: s_cmp_lt_i32 s0, 0
-; GFX9-NEXT: s_cselect_b32 s2, s0, 0
-; GFX9-NEXT: s_sub_i32 s2, 0x80000000, s2
-; GFX9-NEXT: v_max_i32_e32 v0, s2, v0
-; GFX9-NEXT: v_min_i32_e32 v0, s1, v0
-; GFX9-NEXT: v_add_u32_e32 v0, s0, v0
+; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: saddsat_i32_sv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_gt_i32 s0, 0
+; GFX10-NEXT: v_add_nc_i32 v0, s0, v0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s1, s0, 0
-; GFX10-NEXT: s_sub_i32 s1, 0x7fffffff, s1
-; GFX10-NEXT: s_cmp_lt_i32 s0, 0
-; GFX10-NEXT: s_cselect_b32 s2, s0, 0
-; GFX10-NEXT: s_sub_i32 s2, 0x80000000, s2
-; GFX10-NEXT: v_max_i32_e32 v0, s2, v0
-; GFX10-NEXT: v_min_i32_e32 v0, s1, v0
-; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
@@ -1694,25 +1238,13 @@ define amdgpu_ps float @saddsat_i32_vs(i32 %lhs, i32 inreg %rhs) {
;
; GFX9-LABEL: saddsat_i32_vs:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_min_i32_e32 v2, 0, v0
-; GFX9-NEXT: v_max_i32_e32 v1, 0, v0
-; GFX9-NEXT: v_sub_u32_e32 v2, 0x80000000, v2
-; GFX9-NEXT: v_sub_u32_e32 v1, 0x7fffffff, v1
-; GFX9-NEXT: v_max_i32_e32 v2, s0, v2
-; GFX9-NEXT: v_min_i32_e32 v1, v2, v1
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_i32 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: saddsat_i32_vs:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_min_i32_e32 v1, 0, v0
-; GFX10-NEXT: v_max_i32_e32 v2, 0, v0
+; GFX10-NEXT: v_add_nc_i32 v0, v0, s0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0x80000000, v1
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, 0x7fffffff, v2
-; GFX10-NEXT: v_max_i32_e32 v1, s0, v1
-; GFX10-NEXT: v_min_i32_e32 v1, v1, v2
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
@@ -1765,45 +1297,17 @@ define <2 x i32> @v_saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX9-LABEL: v_saddsat_v2i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_brev_b32 s5, 1
-; GFX9-NEXT: v_min_i32_e32 v5, 0, v0
-; GFX9-NEXT: v_sub_u32_e32 v5, s5, v5
-; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: v_max_i32_e32 v4, 0, v0
-; GFX9-NEXT: v_sub_u32_e32 v4, s4, v4
-; GFX9-NEXT: v_max_i32_e32 v2, v5, v2
-; GFX9-NEXT: v_min_i32_e32 v2, v2, v4
-; GFX9-NEXT: v_min_i32_e32 v4, 0, v1
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
-; GFX9-NEXT: v_max_i32_e32 v2, 0, v1
-; GFX9-NEXT: v_sub_u32_e32 v4, s5, v4
-; GFX9-NEXT: v_sub_u32_e32 v2, s4, v2
-; GFX9-NEXT: v_max_i32_e32 v3, v4, v3
-; GFX9-NEXT: v_min_i32_e32 v2, v3, v2
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_i32 v0, v0, v2 clamp
+; GFX9-NEXT: v_add_i32 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_saddsat_v2i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_min_i32_e32 v4, 0, v0
-; GFX10-NEXT: v_min_i32_e32 v5, 0, v1
-; GFX10-NEXT: s_brev_b32 s4, 1
-; GFX10-NEXT: v_max_i32_e32 v6, 0, v0
-; GFX10-NEXT: v_max_i32_e32 v7, 0, v1
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, s4, v4
-; GFX10-NEXT: v_sub_nc_u32_e32 v5, s4, v5
-; GFX10-NEXT: s_brev_b32 s4, -2
+; GFX10-NEXT: v_add_nc_i32 v0, v0, v2 clamp
+; GFX10-NEXT: v_add_nc_i32 v1, v1, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u32_e32 v6, s4, v6
-; GFX10-NEXT: v_max_i32_e32 v11, v4, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v7, s4, v7
-; GFX10-NEXT: v_max_i32_e32 v10, v5, v3
-; GFX10-NEXT: v_min_i32_e32 v2, v11, v6
-; GFX10-NEXT: v_min_i32_e32 v3, v10, v7
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
@@ -1868,59 +1372,21 @@ define amdgpu_ps <2 x i32> @s_saddsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inre
;
; GFX9-LABEL: s_saddsat_v2i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_gt_i32 s0, 0
-; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: s_cselect_b32 s6, s0, 0
-; GFX9-NEXT: s_sub_i32 s6, s4, s6
-; GFX9-NEXT: s_cmp_lt_i32 s0, 0
-; GFX9-NEXT: s_brev_b32 s5, 1
-; GFX9-NEXT: s_cselect_b32 s7, s0, 0
-; GFX9-NEXT: s_sub_i32 s7, s5, s7
-; GFX9-NEXT: s_cmp_gt_i32 s7, s2
-; GFX9-NEXT: s_cselect_b32 s2, s7, s2
-; GFX9-NEXT: s_cmp_lt_i32 s2, s6
-; GFX9-NEXT: s_cselect_b32 s2, s2, s6
-; GFX9-NEXT: s_add_i32 s0, s0, s2
-; GFX9-NEXT: s_cmp_gt_i32 s1, 0
-; GFX9-NEXT: s_cselect_b32 s2, s1, 0
-; GFX9-NEXT: s_sub_i32 s2, s4, s2
-; GFX9-NEXT: s_cmp_lt_i32 s1, 0
-; GFX9-NEXT: s_cselect_b32 s4, s1, 0
-; GFX9-NEXT: s_sub_i32 s4, s5, s4
-; GFX9-NEXT: s_cmp_gt_i32 s4, s3
-; GFX9-NEXT: s_cselect_b32 s3, s4, s3
-; GFX9-NEXT: s_cmp_lt_i32 s3, s2
-; GFX9-NEXT: s_cselect_b32 s2, s3, s2
-; GFX9-NEXT: s_add_i32 s1, s1, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
+; GFX9-NEXT: v_add_i32 v1, s1, v1 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_v2i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_gt_i32 s0, 0
-; GFX10-NEXT: s_brev_b32 s4, -2
-; GFX10-NEXT: s_cselect_b32 s5, s0, 0
-; GFX10-NEXT: s_brev_b32 s6, 1
-; GFX10-NEXT: s_sub_i32 s5, s4, s5
-; GFX10-NEXT: s_cmp_lt_i32 s0, 0
+; GFX10-NEXT: v_add_nc_i32 v0, s0, s2 clamp
+; GFX10-NEXT: v_add_nc_i32 v1, s1, s3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s7, s0, 0
-; GFX10-NEXT: s_sub_i32 s7, s6, s7
-; GFX10-NEXT: s_cmp_gt_i32 s7, s2
-; GFX10-NEXT: s_cselect_b32 s2, s7, s2
-; GFX10-NEXT: s_cmp_lt_i32 s2, s5
-; GFX10-NEXT: s_cselect_b32 s2, s2, s5
-; GFX10-NEXT: s_add_i32 s0, s0, s2
-; GFX10-NEXT: s_cmp_gt_i32 s1, 0
-; GFX10-NEXT: s_cselect_b32 s2, s1, 0
-; GFX10-NEXT: s_sub_i32 s2, s4, s2
-; GFX10-NEXT: s_cmp_lt_i32 s1, 0
-; GFX10-NEXT: s_cselect_b32 s4, s1, 0
-; GFX10-NEXT: s_sub_i32 s4, s6, s4
-; GFX10-NEXT: s_cmp_gt_i32 s4, s3
-; GFX10-NEXT: s_cselect_b32 s3, s4, s3
-; GFX10-NEXT: s_cmp_lt_i32 s3, s2
-; GFX10-NEXT: s_cselect_b32 s2, s3, s2
-; GFX10-NEXT: s_add_i32 s1, s1, s2
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
@@ -1986,59 +1452,19 @@ define <3 x i32> @v_saddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX9-LABEL: v_saddsat_v3i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_brev_b32 s5, 1
-; GFX9-NEXT: v_min_i32_e32 v7, 0, v0
-; GFX9-NEXT: v_sub_u32_e32 v7, s5, v7
-; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: v_max_i32_e32 v6, 0, v0
-; GFX9-NEXT: v_sub_u32_e32 v6, s4, v6
-; GFX9-NEXT: v_max_i32_e32 v3, v7, v3
-; GFX9-NEXT: v_min_i32_e32 v3, v3, v6
-; GFX9-NEXT: v_min_i32_e32 v6, 0, v1
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
-; GFX9-NEXT: v_max_i32_e32 v3, 0, v1
-; GFX9-NEXT: v_sub_u32_e32 v6, s5, v6
-; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3
-; GFX9-NEXT: v_max_i32_e32 v4, v6, v4
-; GFX9-NEXT: v_min_i32_e32 v3, v4, v3
-; GFX9-NEXT: v_min_i32_e32 v4, 0, v2
-; GFX9-NEXT: v_sub_u32_e32 v4, s5, v4
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT: v_max_i32_e32 v3, 0, v2
-; GFX9-NEXT: v_sub_u32_e32 v3, s4, v3
-; GFX9-NEXT: v_max_i32_e32 v4, v4, v5
-; GFX9-NEXT: v_min_i32_e32 v3, v4, v3
-; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_i32 v0, v0, v3 clamp
+; GFX9-NEXT: v_add_i32 v1, v1, v4 clamp
+; GFX9-NEXT: v_add_i32 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_saddsat_v3i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_min_i32_e32 v7, 0, v0
-; GFX10-NEXT: v_min_i32_e32 v8, 0, v1
-; GFX10-NEXT: v_min_i32_e32 v9, 0, v2
-; GFX10-NEXT: s_brev_b32 s5, 1
-; GFX10-NEXT: v_max_i32_e32 v6, 0, v0
-; GFX10-NEXT: v_sub_nc_u32_e32 v14, s5, v7
-; GFX10-NEXT: v_sub_nc_u32_e32 v15, s5, v8
-; GFX10-NEXT: v_sub_nc_u32_e32 v19, s5, v9
-; GFX10-NEXT: v_max_i32_e32 v10, 0, v1
-; GFX10-NEXT: v_max_i32_e32 v11, 0, v2
-; GFX10-NEXT: s_brev_b32 s4, -2
-; GFX10-NEXT: v_max_i32_e32 v3, v14, v3
-; GFX10-NEXT: v_sub_nc_u32_e32 v6, s4, v6
-; GFX10-NEXT: v_sub_nc_u32_e32 v7, s4, v10
-; GFX10-NEXT: v_max_i32_e32 v4, v15, v4
-; GFX10-NEXT: v_sub_nc_u32_e32 v8, s4, v11
-; GFX10-NEXT: v_max_i32_e32 v5, v19, v5
-; GFX10-NEXT: v_min_i32_e32 v3, v3, v6
+; GFX10-NEXT: v_add_nc_i32 v0, v0, v3 clamp
+; GFX10-NEXT: v_add_nc_i32 v1, v1, v4 clamp
+; GFX10-NEXT: v_add_nc_i32 v2, v2, v5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_i32_e32 v4, v4, v7
-; GFX10-NEXT: v_min_i32_e32 v5, v5, v8
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v3
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v4
-; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i32> @llvm.sadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
@@ -2125,81 +1551,26 @@ define amdgpu_ps <3 x i32> @s_saddsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inre
;
; GFX9-LABEL: s_saddsat_v3i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_gt_i32 s0, 0
-; GFX9-NEXT: s_brev_b32 s6, -2
-; GFX9-NEXT: s_cselect_b32 s8, s0, 0
-; GFX9-NEXT: s_sub_i32 s8, s6, s8
-; GFX9-NEXT: s_cmp_lt_i32 s0, 0
-; GFX9-NEXT: s_brev_b32 s7, 1
-; GFX9-NEXT: s_cselect_b32 s9, s0, 0
-; GFX9-NEXT: s_sub_i32 s9, s7, s9
-; GFX9-NEXT: s_cmp_gt_i32 s9, s3
-; GFX9-NEXT: s_cselect_b32 s3, s9, s3
-; GFX9-NEXT: s_cmp_lt_i32 s3, s8
-; GFX9-NEXT: s_cselect_b32 s3, s3, s8
-; GFX9-NEXT: s_add_i32 s0, s0, s3
-; GFX9-NEXT: s_cmp_gt_i32 s1, 0
-; GFX9-NEXT: s_cselect_b32 s3, s1, 0
-; GFX9-NEXT: s_sub_i32 s3, s6, s3
-; GFX9-NEXT: s_cmp_lt_i32 s1, 0
-; GFX9-NEXT: s_cselect_b32 s8, s1, 0
-; GFX9-NEXT: s_sub_i32 s8, s7, s8
-; GFX9-NEXT: s_cmp_gt_i32 s8, s4
-; GFX9-NEXT: s_cselect_b32 s4, s8, s4
-; GFX9-NEXT: s_cmp_lt_i32 s4, s3
-; GFX9-NEXT: s_cselect_b32 s3, s4, s3
-; GFX9-NEXT: s_add_i32 s1, s1, s3
-; GFX9-NEXT: s_cmp_gt_i32 s2, 0
-; GFX9-NEXT: s_cselect_b32 s3, s2, 0
-; GFX9-NEXT: s_sub_i32 s3, s6, s3
-; GFX9-NEXT: s_cmp_lt_i32 s2, 0
-; GFX9-NEXT: s_cselect_b32 s4, s2, 0
-; GFX9-NEXT: s_sub_i32 s4, s7, s4
-; GFX9-NEXT: s_cmp_gt_i32 s4, s5
-; GFX9-NEXT: s_cselect_b32 s4, s4, s5
-; GFX9-NEXT: s_cmp_lt_i32 s4, s3
-; GFX9-NEXT: s_cselect_b32 s3, s4, s3
-; GFX9-NEXT: s_add_i32 s2, s2, s3
+; GFX9-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
+; GFX9-NEXT: v_add_i32 v1, s1, v1 clamp
+; GFX9-NEXT: v_add_i32 v2, s2, v2 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_v3i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_gt_i32 s0, 0
-; GFX10-NEXT: s_brev_b32 s6, -2
-; GFX10-NEXT: s_cselect_b32 s7, s0, 0
-; GFX10-NEXT: s_brev_b32 s8, 1
-; GFX10-NEXT: s_sub_i32 s7, s6, s7
-; GFX10-NEXT: s_cmp_lt_i32 s0, 0
+; GFX10-NEXT: v_add_nc_i32 v0, s0, s3 clamp
+; GFX10-NEXT: v_add_nc_i32 v1, s1, s4 clamp
+; GFX10-NEXT: v_add_nc_i32 v2, s2, s5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s9, s0, 0
-; GFX10-NEXT: s_sub_i32 s9, s8, s9
-; GFX10-NEXT: s_cmp_gt_i32 s9, s3
-; GFX10-NEXT: s_cselect_b32 s3, s9, s3
-; GFX10-NEXT: s_cmp_lt_i32 s3, s7
-; GFX10-NEXT: s_cselect_b32 s3, s3, s7
-; GFX10-NEXT: s_add_i32 s0, s0, s3
-; GFX10-NEXT: s_cmp_gt_i32 s1, 0
-; GFX10-NEXT: s_cselect_b32 s3, s1, 0
-; GFX10-NEXT: s_sub_i32 s3, s6, s3
-; GFX10-NEXT: s_cmp_lt_i32 s1, 0
-; GFX10-NEXT: s_cselect_b32 s7, s1, 0
-; GFX10-NEXT: s_sub_i32 s7, s8, s7
-; GFX10-NEXT: s_cmp_gt_i32 s7, s4
-; GFX10-NEXT: s_cselect_b32 s4, s7, s4
-; GFX10-NEXT: s_cmp_lt_i32 s4, s3
-; GFX10-NEXT: s_cselect_b32 s3, s4, s3
-; GFX10-NEXT: s_add_i32 s1, s1, s3
-; GFX10-NEXT: s_cmp_gt_i32 s2, 0
-; GFX10-NEXT: s_cselect_b32 s3, s2, 0
-; GFX10-NEXT: s_sub_i32 s3, s6, s3
-; GFX10-NEXT: s_cmp_lt_i32 s2, 0
-; GFX10-NEXT: s_cselect_b32 s4, s2, 0
-; GFX10-NEXT: s_sub_i32 s4, s8, s4
-; GFX10-NEXT: s_cmp_gt_i32 s4, s5
-; GFX10-NEXT: s_cselect_b32 s4, s4, s5
-; GFX10-NEXT: s_cmp_lt_i32 s4, s3
-; GFX10-NEXT: s_cselect_b32 s3, s4, s3
-; GFX10-NEXT: s_add_i32 s2, s2, s3
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: ; return to shader part epilog
%result = call <3 x i32> @llvm.sadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
@@ -2279,73 +1650,21 @@ define <4 x i32> @v_saddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX9-LABEL: v_saddsat_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_brev_b32 s5, 1
-; GFX9-NEXT: v_min_i32_e32 v9, 0, v0
-; GFX9-NEXT: v_sub_u32_e32 v9, s5, v9
-; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: v_max_i32_e32 v8, 0, v0
-; GFX9-NEXT: v_sub_u32_e32 v8, s4, v8
-; GFX9-NEXT: v_max_i32_e32 v4, v9, v4
-; GFX9-NEXT: v_min_i32_e32 v4, v4, v8
-; GFX9-NEXT: v_min_i32_e32 v8, 0, v1
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v4
-; GFX9-NEXT: v_max_i32_e32 v4, 0, v1
-; GFX9-NEXT: v_sub_u32_e32 v8, s5, v8
-; GFX9-NEXT: v_sub_u32_e32 v4, s4, v4
-; GFX9-NEXT: v_max_i32_e32 v5, v8, v5
-; GFX9-NEXT: v_min_i32_e32 v4, v5, v4
-; GFX9-NEXT: v_min_i32_e32 v5, 0, v2
-; GFX9-NEXT: v_sub_u32_e32 v5, s5, v5
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v4
-; GFX9-NEXT: v_max_i32_e32 v4, 0, v2
-; GFX9-NEXT: v_sub_u32_e32 v4, s4, v4
-; GFX9-NEXT: v_max_i32_e32 v5, v5, v6
-; GFX9-NEXT: v_min_i32_e32 v4, v5, v4
-; GFX9-NEXT: v_min_i32_e32 v5, 0, v3
-; GFX9-NEXT: v_sub_u32_e32 v5, 0x80000000, v5
-; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
-; GFX9-NEXT: v_max_i32_e32 v4, 0, v3
-; GFX9-NEXT: v_sub_u32_e32 v4, 0x7fffffff, v4
-; GFX9-NEXT: v_max_i32_e32 v5, v5, v7
-; GFX9-NEXT: v_min_i32_e32 v4, v5, v4
-; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_i32 v0, v0, v4 clamp
+; GFX9-NEXT: v_add_i32 v1, v1, v5 clamp
+; GFX9-NEXT: v_add_i32 v2, v2, v6 clamp
+; GFX9-NEXT: v_add_i32 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_saddsat_v4i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_min_i32_e32 v8, 0, v0
-; GFX10-NEXT: s_brev_b32 s4, 1
-; GFX10-NEXT: v_min_i32_e32 v11, 0, v1
-; GFX10-NEXT: v_min_i32_e32 v12, 0, v3
-; GFX10-NEXT: v_max_i32_e32 v9, 0, v0
-; GFX10-NEXT: v_sub_nc_u32_e32 v15, s4, v8
-; GFX10-NEXT: v_min_i32_e32 v8, 0, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v11, s4, v11
-; GFX10-NEXT: v_sub_nc_u32_e32 v12, 0x80000000, v12
-; GFX10-NEXT: v_max_i32_e32 v10, 0, v1
-; GFX10-NEXT: v_max_i32_e32 v13, 0, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v8, s4, v8
-; GFX10-NEXT: v_max_i32_e32 v14, 0, v3
-; GFX10-NEXT: s_brev_b32 s5, -2
-; GFX10-NEXT: v_max_i32_e32 v5, v11, v5
-; GFX10-NEXT: v_sub_nc_u32_e32 v10, s5, v10
-; GFX10-NEXT: v_max_i32_e32 v6, v8, v6
-; GFX10-NEXT: v_sub_nc_u32_e32 v11, s5, v13
-; GFX10-NEXT: v_sub_nc_u32_e32 v9, s5, v9
-; GFX10-NEXT: v_max_i32_e32 v4, v15, v4
-; GFX10-NEXT: v_sub_nc_u32_e32 v8, 0x7fffffff, v14
-; GFX10-NEXT: v_max_i32_e32 v7, v12, v7
-; GFX10-NEXT: v_min_i32_e32 v11, v6, v11
-; GFX10-NEXT: v_min_i32_e32 v19, v5, v10
-; GFX10-NEXT: v_min_i32_e32 v15, v4, v9
+; GFX10-NEXT: v_add_nc_i32 v0, v0, v4 clamp
+; GFX10-NEXT: v_add_nc_i32 v1, v1, v5 clamp
+; GFX10-NEXT: v_add_nc_i32 v2, v2, v6 clamp
+; GFX10-NEXT: v_add_nc_i32 v3, v3, v7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_i32_e32 v6, v7, v8
-; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v11
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v19
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v15
-; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v6
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
@@ -2454,103 +1773,31 @@ define amdgpu_ps <4 x i32> @s_saddsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inre
;
; GFX9-LABEL: s_saddsat_v4i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_gt_i32 s0, 0
-; GFX9-NEXT: s_brev_b32 s8, -2
-; GFX9-NEXT: s_cselect_b32 s10, s0, 0
-; GFX9-NEXT: s_sub_i32 s10, s8, s10
-; GFX9-NEXT: s_cmp_lt_i32 s0, 0
-; GFX9-NEXT: s_brev_b32 s9, 1
-; GFX9-NEXT: s_cselect_b32 s11, s0, 0
-; GFX9-NEXT: s_sub_i32 s11, s9, s11
-; GFX9-NEXT: s_cmp_gt_i32 s11, s4
-; GFX9-NEXT: s_cselect_b32 s4, s11, s4
-; GFX9-NEXT: s_cmp_lt_i32 s4, s10
-; GFX9-NEXT: s_cselect_b32 s4, s4, s10
-; GFX9-NEXT: s_add_i32 s0, s0, s4
-; GFX9-NEXT: s_cmp_gt_i32 s1, 0
-; GFX9-NEXT: s_cselect_b32 s4, s1, 0
-; GFX9-NEXT: s_sub_i32 s4, s8, s4
-; GFX9-NEXT: s_cmp_lt_i32 s1, 0
-; GFX9-NEXT: s_cselect_b32 s10, s1, 0
-; GFX9-NEXT: s_sub_i32 s10, s9, s10
-; GFX9-NEXT: s_cmp_gt_i32 s10, s5
-; GFX9-NEXT: s_cselect_b32 s5, s10, s5
-; GFX9-NEXT: s_cmp_lt_i32 s5, s4
-; GFX9-NEXT: s_cselect_b32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s1, s1, s4
-; GFX9-NEXT: s_cmp_gt_i32 s2, 0
-; GFX9-NEXT: s_cselect_b32 s4, s2, 0
-; GFX9-NEXT: s_sub_i32 s4, s8, s4
-; GFX9-NEXT: s_cmp_lt_i32 s2, 0
-; GFX9-NEXT: s_cselect_b32 s5, s2, 0
-; GFX9-NEXT: s_sub_i32 s5, s9, s5
-; GFX9-NEXT: s_cmp_gt_i32 s5, s6
-; GFX9-NEXT: s_cselect_b32 s5, s5, s6
-; GFX9-NEXT: s_cmp_lt_i32 s5, s4
-; GFX9-NEXT: s_cselect_b32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s2, s2, s4
-; GFX9-NEXT: s_cmp_gt_i32 s3, 0
-; GFX9-NEXT: s_cselect_b32 s4, s3, 0
-; GFX9-NEXT: s_sub_i32 s4, s8, s4
-; GFX9-NEXT: s_cmp_lt_i32 s3, 0
-; GFX9-NEXT: s_cselect_b32 s5, s3, 0
-; GFX9-NEXT: s_sub_i32 s5, s9, s5
-; GFX9-NEXT: s_cmp_gt_i32 s5, s7
-; GFX9-NEXT: s_cselect_b32 s5, s5, s7
-; GFX9-NEXT: s_cmp_lt_i32 s5, s4
-; GFX9-NEXT: s_cselect_b32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s3, s3, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
+; GFX9-NEXT: v_add_i32 v1, s1, v1 clamp
+; GFX9-NEXT: v_add_i32 v2, s2, v2 clamp
+; GFX9-NEXT: v_add_i32 v3, s3, v3 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_v4i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_gt_i32 s0, 0
-; GFX10-NEXT: s_brev_b32 s8, -2
-; GFX10-NEXT: s_cselect_b32 s9, s0, 0
-; GFX10-NEXT: s_brev_b32 s10, 1
-; GFX10-NEXT: s_sub_i32 s9, s8, s9
-; GFX10-NEXT: s_cmp_lt_i32 s0, 0
+; GFX10-NEXT: v_add_nc_i32 v0, s0, s4 clamp
+; GFX10-NEXT: v_add_nc_i32 v1, s1, s5 clamp
+; GFX10-NEXT: v_add_nc_i32 v2, s2, s6 clamp
+; GFX10-NEXT: v_add_nc_i32 v3, s3, s7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s11, s0, 0
-; GFX10-NEXT: s_sub_i32 s11, s10, s11
-; GFX10-NEXT: s_cmp_gt_i32 s11, s4
-; GFX10-NEXT: s_cselect_b32 s4, s11, s4
-; GFX10-NEXT: s_cmp_lt_i32 s4, s9
-; GFX10-NEXT: s_cselect_b32 s4, s4, s9
-; GFX10-NEXT: s_add_i32 s0, s0, s4
-; GFX10-NEXT: s_cmp_gt_i32 s1, 0
-; GFX10-NEXT: s_cselect_b32 s4, s1, 0
-; GFX10-NEXT: s_sub_i32 s4, s8, s4
-; GFX10-NEXT: s_cmp_lt_i32 s1, 0
-; GFX10-NEXT: s_cselect_b32 s9, s1, 0
-; GFX10-NEXT: s_sub_i32 s9, s10, s9
-; GFX10-NEXT: s_cmp_gt_i32 s9, s5
-; GFX10-NEXT: s_cselect_b32 s5, s9, s5
-; GFX10-NEXT: s_cmp_lt_i32 s5, s4
-; GFX10-NEXT: s_cselect_b32 s4, s5, s4
-; GFX10-NEXT: s_add_i32 s1, s1, s4
-; GFX10-NEXT: s_cmp_gt_i32 s2, 0
-; GFX10-NEXT: s_cselect_b32 s4, s2, 0
-; GFX10-NEXT: s_sub_i32 s4, s8, s4
-; GFX10-NEXT: s_cmp_lt_i32 s2, 0
-; GFX10-NEXT: s_cselect_b32 s5, s2, 0
-; GFX10-NEXT: s_sub_i32 s5, s10, s5
-; GFX10-NEXT: s_cmp_gt_i32 s5, s6
-; GFX10-NEXT: s_cselect_b32 s5, s5, s6
-; GFX10-NEXT: s_cmp_lt_i32 s5, s4
-; GFX10-NEXT: s_cselect_b32 s4, s5, s4
-; GFX10-NEXT: s_add_i32 s2, s2, s4
-; GFX10-NEXT: s_cmp_gt_i32 s3, 0
-; GFX10-NEXT: s_cselect_b32 s4, s3, 0
-; GFX10-NEXT: s_sub_i32 s4, s8, s4
-; GFX10-NEXT: s_cmp_lt_i32 s3, 0
-; GFX10-NEXT: s_cselect_b32 s5, s3, 0
-; GFX10-NEXT: s_sub_i32 s5, s10, s5
-; GFX10-NEXT: s_cmp_gt_i32 s5, s7
-; GFX10-NEXT: s_cselect_b32 s5, s5, s7
-; GFX10-NEXT: s_cmp_lt_i32 s5, s4
-; GFX10-NEXT: s_cselect_b32 s4, s5, s4
-; GFX10-NEXT: s_add_i32 s3, s3, s4
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: ; return to shader part epilog
%result = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
@@ -2648,90 +1895,22 @@ define <5 x i32> @v_saddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX9-LABEL: v_saddsat_v5i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_brev_b32 s5, 1
-; GFX9-NEXT: v_min_i32_e32 v12, 0, v0
-; GFX9-NEXT: v_sub_u32_e32 v12, s5, v12
-; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: v_max_i32_e32 v10, 0, v0
-; GFX9-NEXT: v_sub_u32_e32 v10, s4, v10
-; GFX9-NEXT: v_max_i32_e32 v5, v12, v5
-; GFX9-NEXT: v_min_i32_e32 v5, v5, v10
-; GFX9-NEXT: v_min_i32_e32 v10, 0, v1
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v5
-; GFX9-NEXT: v_max_i32_e32 v5, 0, v1
-; GFX9-NEXT: v_sub_u32_e32 v10, s5, v10
-; GFX9-NEXT: v_sub_u32_e32 v5, s4, v5
-; GFX9-NEXT: v_max_i32_e32 v6, v10, v6
-; GFX9-NEXT: v_min_i32_e32 v5, v6, v5
-; GFX9-NEXT: v_min_i32_e32 v6, 0, v2
-; GFX9-NEXT: v_sub_u32_e32 v6, s5, v6
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v5
-; GFX9-NEXT: v_max_i32_e32 v5, 0, v2
-; GFX9-NEXT: v_sub_u32_e32 v5, s4, v5
-; GFX9-NEXT: v_max_i32_e32 v6, v6, v7
-; GFX9-NEXT: v_min_i32_e32 v5, v6, v5
-; GFX9-NEXT: v_bfrev_b32_e32 v13, 1
-; GFX9-NEXT: v_min_i32_e32 v6, 0, v3
-; GFX9-NEXT: v_sub_u32_e32 v6, v13, v6
-; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
-; GFX9-NEXT: v_bfrev_b32_e32 v11, -2
-; GFX9-NEXT: v_max_i32_e32 v5, 0, v3
-; GFX9-NEXT: v_sub_u32_e32 v5, v11, v5
-; GFX9-NEXT: v_max_i32_e32 v6, v6, v8
-; GFX9-NEXT: v_min_i32_e32 v5, v6, v5
-; GFX9-NEXT: v_min_i32_e32 v6, 0, v4
-; GFX9-NEXT: v_sub_u32_e32 v6, v13, v6
-; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
-; GFX9-NEXT: v_max_i32_e32 v5, 0, v4
-; GFX9-NEXT: v_sub_u32_e32 v5, v11, v5
-; GFX9-NEXT: v_max_i32_e32 v6, v6, v9
-; GFX9-NEXT: v_min_i32_e32 v5, v6, v5
-; GFX9-NEXT: v_add_u32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_i32 v0, v0, v5 clamp
+; GFX9-NEXT: v_add_i32 v1, v1, v6 clamp
+; GFX9-NEXT: v_add_i32 v2, v2, v7 clamp
+; GFX9-NEXT: v_add_i32 v3, v3, v8 clamp
+; GFX9-NEXT: v_add_i32 v4, v4, v9 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_saddsat_v5i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_min_i32_e32 v13, 0, v1
-; GFX10-NEXT: s_brev_b32 s5, 1
-; GFX10-NEXT: v_min_i32_e32 v10, 0, v0
-; GFX10-NEXT: v_min_i32_e32 v16, 0, v2
-; GFX10-NEXT: v_bfrev_b32_e32 v15, 1
-; GFX10-NEXT: v_sub_nc_u32_e32 v13, s5, v13
-; GFX10-NEXT: v_min_i32_e32 v17, 0, v4
-; GFX10-NEXT: v_sub_nc_u32_e32 v10, s5, v10
-; GFX10-NEXT: v_sub_nc_u32_e32 v16, s5, v16
-; GFX10-NEXT: v_max_i32_e32 v11, 0, v0
-; GFX10-NEXT: v_max_i32_e32 v23, v13, v6
-; GFX10-NEXT: v_min_i32_e32 v13, 0, v3
-; GFX10-NEXT: v_max_i32_e32 v5, v10, v5
-; GFX10-NEXT: v_bfrev_b32_e32 v12, -2
-; GFX10-NEXT: v_max_i32_e32 v14, 0, v1
-; GFX10-NEXT: v_max_i32_e32 v10, 0, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v13, v15, v13
-; GFX10-NEXT: v_sub_nc_u32_e32 v15, v15, v17
-; GFX10-NEXT: v_max_i32_e32 v18, 0, v3
-; GFX10-NEXT: v_max_i32_e32 v19, 0, v4
-; GFX10-NEXT: s_brev_b32 s4, -2
-; GFX10-NEXT: v_max_i32_e32 v7, v16, v7
-; GFX10-NEXT: v_sub_nc_u32_e32 v11, s4, v11
-; GFX10-NEXT: v_sub_nc_u32_e32 v14, s4, v14
-; GFX10-NEXT: v_sub_nc_u32_e32 v10, s4, v10
-; GFX10-NEXT: v_sub_nc_u32_e32 v16, v12, v18
-; GFX10-NEXT: v_max_i32_e32 v27, v13, v8
-; GFX10-NEXT: v_sub_nc_u32_e32 v12, v12, v19
-; GFX10-NEXT: v_max_i32_e32 v9, v15, v9
-; GFX10-NEXT: v_min_i32_e32 v5, v5, v11
-; GFX10-NEXT: v_min_i32_e32 v6, v23, v14
-; GFX10-NEXT: v_min_i32_e32 v7, v7, v10
-; GFX10-NEXT: v_min_i32_e32 v8, v27, v16
-; GFX10-NEXT: v_min_i32_e32 v9, v9, v12
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v5
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v6
-; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v7
-; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v8
-; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v9
+; GFX10-NEXT: v_add_nc_i32 v0, v0, v5 clamp
+; GFX10-NEXT: v_add_nc_i32 v1, v1, v6 clamp
+; GFX10-NEXT: v_add_nc_i32 v2, v2, v7 clamp
+; GFX10-NEXT: v_add_nc_i32 v3, v3, v8 clamp
+; GFX10-NEXT: v_add_nc_i32 v4, v4, v9 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
@@ -2863,125 +2042,36 @@ define amdgpu_ps <5 x i32> @s_saddsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inre
;
; GFX9-LABEL: s_saddsat_v5i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_gt_i32 s0, 0
-; GFX9-NEXT: s_brev_b32 s10, -2
-; GFX9-NEXT: s_cselect_b32 s12, s0, 0
-; GFX9-NEXT: s_sub_i32 s12, s10, s12
-; GFX9-NEXT: s_cmp_lt_i32 s0, 0
-; GFX9-NEXT: s_brev_b32 s11, 1
-; GFX9-NEXT: s_cselect_b32 s13, s0, 0
-; GFX9-NEXT: s_sub_i32 s13, s11, s13
-; GFX9-NEXT: s_cmp_gt_i32 s13, s5
-; GFX9-NEXT: s_cselect_b32 s5, s13, s5
-; GFX9-NEXT: s_cmp_lt_i32 s5, s12
-; GFX9-NEXT: s_cselect_b32 s5, s5, s12
-; GFX9-NEXT: s_add_i32 s0, s0, s5
-; GFX9-NEXT: s_cmp_gt_i32 s1, 0
-; GFX9-NEXT: s_cselect_b32 s5, s1, 0
-; GFX9-NEXT: s_sub_i32 s5, s10, s5
-; GFX9-NEXT: s_cmp_lt_i32 s1, 0
-; GFX9-NEXT: s_cselect_b32 s12, s1, 0
-; GFX9-NEXT: s_sub_i32 s12, s11, s12
-; GFX9-NEXT: s_cmp_gt_i32 s12, s6
-; GFX9-NEXT: s_cselect_b32 s6, s12, s6
-; GFX9-NEXT: s_cmp_lt_i32 s6, s5
-; GFX9-NEXT: s_cselect_b32 s5, s6, s5
-; GFX9-NEXT: s_add_i32 s1, s1, s5
-; GFX9-NEXT: s_cmp_gt_i32 s2, 0
-; GFX9-NEXT: s_cselect_b32 s5, s2, 0
-; GFX9-NEXT: s_sub_i32 s5, s10, s5
-; GFX9-NEXT: s_cmp_lt_i32 s2, 0
-; GFX9-NEXT: s_cselect_b32 s6, s2, 0
-; GFX9-NEXT: s_sub_i32 s6, s11, s6
-; GFX9-NEXT: s_cmp_gt_i32 s6, s7
-; GFX9-NEXT: s_cselect_b32 s6, s6, s7
-; GFX9-NEXT: s_cmp_lt_i32 s6, s5
-; GFX9-NEXT: s_cselect_b32 s5, s6, s5
-; GFX9-NEXT: s_add_i32 s2, s2, s5
-; GFX9-NEXT: s_cmp_gt_i32 s3, 0
-; GFX9-NEXT: s_cselect_b32 s5, s3, 0
-; GFX9-NEXT: s_sub_i32 s5, s10, s5
-; GFX9-NEXT: s_cmp_lt_i32 s3, 0
-; GFX9-NEXT: s_cselect_b32 s6, s3, 0
-; GFX9-NEXT: s_sub_i32 s6, s11, s6
-; GFX9-NEXT: s_cmp_gt_i32 s6, s8
-; GFX9-NEXT: s_cselect_b32 s6, s6, s8
-; GFX9-NEXT: s_cmp_lt_i32 s6, s5
-; GFX9-NEXT: s_cselect_b32 s5, s6, s5
-; GFX9-NEXT: s_add_i32 s3, s3, s5
-; GFX9-NEXT: s_cmp_gt_i32 s4, 0
-; GFX9-NEXT: s_cselect_b32 s5, s4, 0
-; GFX9-NEXT: s_sub_i32 s5, s10, s5
-; GFX9-NEXT: s_cmp_lt_i32 s4, 0
-; GFX9-NEXT: s_cselect_b32 s6, s4, 0
-; GFX9-NEXT: s_sub_i32 s6, s11, s6
-; GFX9-NEXT: s_cmp_gt_i32 s6, s9
-; GFX9-NEXT: s_cselect_b32 s6, s6, s9
-; GFX9-NEXT: s_cmp_lt_i32 s6, s5
-; GFX9-NEXT: s_cselect_b32 s5, s6, s5
-; GFX9-NEXT: s_add_i32 s4, s4, s5
+; GFX9-NEXT: v_mov_b32_e32 v0, s5
+; GFX9-NEXT: v_mov_b32_e32 v1, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s7
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
+; GFX9-NEXT: v_mov_b32_e32 v4, s9
+; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
+; GFX9-NEXT: v_add_i32 v1, s1, v1 clamp
+; GFX9-NEXT: v_add_i32 v2, s2, v2 clamp
+; GFX9-NEXT: v_add_i32 v3, s3, v3 clamp
+; GFX9-NEXT: v_add_i32 v4, s4, v4 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
+; GFX9-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_v5i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_gt_i32 s0, 0
-; GFX10-NEXT: s_brev_b32 s10, -2
-; GFX10-NEXT: s_cselect_b32 s11, s0, 0
-; GFX10-NEXT: s_brev_b32 s12, 1
-; GFX10-NEXT: s_sub_i32 s11, s10, s11
-; GFX10-NEXT: s_cmp_lt_i32 s0, 0
+; GFX10-NEXT: v_add_nc_i32 v0, s0, s5 clamp
+; GFX10-NEXT: v_add_nc_i32 v1, s1, s6 clamp
+; GFX10-NEXT: v_add_nc_i32 v2, s2, s7 clamp
+; GFX10-NEXT: v_add_nc_i32 v3, s3, s8 clamp
+; GFX10-NEXT: v_add_nc_i32 v4, s4, s9 clamp
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10-NEXT: v_readfirstlane_b32 s4, v4
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s13, s0, 0
-; GFX10-NEXT: s_sub_i32 s13, s12, s13
-; GFX10-NEXT: s_cmp_gt_i32 s13, s5
-; GFX10-NEXT: s_cselect_b32 s5, s13, s5
-; GFX10-NEXT: s_cmp_lt_i32 s5, s11
-; GFX10-NEXT: s_cselect_b32 s5, s5, s11
-; GFX10-NEXT: s_add_i32 s0, s0, s5
-; GFX10-NEXT: s_cmp_gt_i32 s1, 0
-; GFX10-NEXT: s_cselect_b32 s5, s1, 0
-; GFX10-NEXT: s_sub_i32 s5, s10, s5
-; GFX10-NEXT: s_cmp_lt_i32 s1, 0
-; GFX10-NEXT: s_cselect_b32 s11, s1, 0
-; GFX10-NEXT: s_sub_i32 s11, s12, s11
-; GFX10-NEXT: s_cmp_gt_i32 s11, s6
-; GFX10-NEXT: s_cselect_b32 s6, s11, s6
-; GFX10-NEXT: s_cmp_lt_i32 s6, s5
-; GFX10-NEXT: s_cselect_b32 s5, s6, s5
-; GFX10-NEXT: s_add_i32 s1, s1, s5
-; GFX10-NEXT: s_cmp_gt_i32 s2, 0
-; GFX10-NEXT: s_cselect_b32 s5, s2, 0
-; GFX10-NEXT: s_sub_i32 s5, s10, s5
-; GFX10-NEXT: s_cmp_lt_i32 s2, 0
-; GFX10-NEXT: s_cselect_b32 s6, s2, 0
-; GFX10-NEXT: s_sub_i32 s6, s12, s6
-; GFX10-NEXT: s_cmp_gt_i32 s6, s7
-; GFX10-NEXT: s_cselect_b32 s6, s6, s7
-; GFX10-NEXT: s_cmp_lt_i32 s6, s5
-; GFX10-NEXT: s_cselect_b32 s5, s6, s5
-; GFX10-NEXT: s_add_i32 s2, s2, s5
-; GFX10-NEXT: s_cmp_gt_i32 s3, 0
-; GFX10-NEXT: s_cselect_b32 s5, s3, 0
-; GFX10-NEXT: s_sub_i32 s5, s10, s5
-; GFX10-NEXT: s_cmp_lt_i32 s3, 0
-; GFX10-NEXT: s_cselect_b32 s6, s3, 0
-; GFX10-NEXT: s_sub_i32 s6, s12, s6
-; GFX10-NEXT: s_cmp_gt_i32 s6, s8
-; GFX10-NEXT: s_cselect_b32 s6, s6, s8
-; GFX10-NEXT: s_cmp_lt_i32 s6, s5
-; GFX10-NEXT: s_cselect_b32 s5, s6, s5
-; GFX10-NEXT: s_add_i32 s3, s3, s5
-; GFX10-NEXT: s_cmp_gt_i32 s4, 0
-; GFX10-NEXT: s_cselect_b32 s5, s4, 0
-; GFX10-NEXT: s_sub_i32 s5, s10, s5
-; GFX10-NEXT: s_cmp_lt_i32 s4, 0
-; GFX10-NEXT: s_cselect_b32 s6, s4, 0
-; GFX10-NEXT: s_sub_i32 s6, s12, s6
-; GFX10-NEXT: s_cmp_gt_i32 s6, s9
-; GFX10-NEXT: s_cselect_b32 s6, s6, s9
-; GFX10-NEXT: s_cmp_lt_i32 s6, s5
-; GFX10-NEXT: s_cselect_b32 s5, s6, s5
-; GFX10-NEXT: s_add_i32 s4, s4, s5
; GFX10-NEXT: ; return to shader part epilog
%result = call <5 x i32> @llvm.sadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result
@@ -3233,244 +2323,44 @@ define <16 x i32> @v_saddsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
; GFX9-LABEL: v_saddsat_v16i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_brev_b32 s4, 1
-; GFX9-NEXT: v_min_i32_e32 v32, 0, v0
-; GFX9-NEXT: v_sub_u32_e32 v32, s4, v32
-; GFX9-NEXT: v_max_i32_e32 v16, v32, v16
-; GFX9-NEXT: s_brev_b32 s5, -2
-; GFX9-NEXT: v_max_i32_e32 v32, 0, v0
-; GFX9-NEXT: v_sub_u32_e32 v32, s5, v32
-; GFX9-NEXT: v_min_i32_e32 v16, v16, v32
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v16
-; GFX9-NEXT: v_min_i32_e32 v16, 0, v1
-; GFX9-NEXT: v_sub_u32_e32 v16, s4, v16
-; GFX9-NEXT: v_max_i32_e32 v16, v16, v17
-; GFX9-NEXT: v_max_i32_e32 v17, 0, v1
-; GFX9-NEXT: v_sub_u32_e32 v17, s5, v17
-; GFX9-NEXT: v_min_i32_e32 v16, v16, v17
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v16
-; GFX9-NEXT: v_min_i32_e32 v16, 0, v2
-; GFX9-NEXT: v_sub_u32_e32 v16, s4, v16
-; GFX9-NEXT: v_max_i32_e32 v17, 0, v2
-; GFX9-NEXT: v_max_i32_e32 v16, v16, v18
-; GFX9-NEXT: v_sub_u32_e32 v17, s5, v17
-; GFX9-NEXT: v_min_i32_e32 v16, v16, v17
-; GFX9-NEXT: v_add_u32_e32 v2, v2, v16
-; GFX9-NEXT: v_bfrev_b32_e32 v16, 1
-; GFX9-NEXT: v_min_i32_e32 v17, 0, v3
-; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_bfrev_b32_e32 v18, -2
-; GFX9-NEXT: v_max_i32_e32 v19, 0, v3
-; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_add_u32_e32 v3, v3, v17
-; GFX9-NEXT: v_min_i32_e32 v17, 0, v4
-; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17
-; GFX9-NEXT: v_max_i32_e32 v19, 0, v4
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v20
-; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_add_u32_e32 v4, v4, v17
-; GFX9-NEXT: v_min_i32_e32 v17, 0, v5
-; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17
-; GFX9-NEXT: v_max_i32_e32 v19, 0, v5
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v21
-; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v17
-; GFX9-NEXT: v_min_i32_e32 v17, 0, v6
-; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17
-; GFX9-NEXT: v_max_i32_e32 v19, 0, v6
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v22
-; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_add_u32_e32 v6, v6, v17
-; GFX9-NEXT: v_min_i32_e32 v17, 0, v7
-; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17
-; GFX9-NEXT: v_max_i32_e32 v19, 0, v7
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v23
-; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_add_u32_e32 v7, v7, v17
-; GFX9-NEXT: v_min_i32_e32 v17, 0, v8
-; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17
-; GFX9-NEXT: v_max_i32_e32 v19, 0, v8
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v24
-; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v17
-; GFX9-NEXT: v_min_i32_e32 v17, 0, v9
-; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17
-; GFX9-NEXT: v_max_i32_e32 v19, 0, v9
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v25
-; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_add_u32_e32 v9, v9, v17
-; GFX9-NEXT: v_min_i32_e32 v17, 0, v10
-; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17
-; GFX9-NEXT: v_max_i32_e32 v19, 0, v10
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v26
-; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_add_u32_e32 v10, v10, v17
-; GFX9-NEXT: v_min_i32_e32 v17, 0, v11
-; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17
-; GFX9-NEXT: v_max_i32_e32 v19, 0, v11
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v27
-; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_add_u32_e32 v11, v11, v17
-; GFX9-NEXT: v_min_i32_e32 v17, 0, v12
-; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17
-; GFX9-NEXT: v_max_i32_e32 v19, 0, v12
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v28
-; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_add_u32_e32 v12, v12, v17
-; GFX9-NEXT: v_min_i32_e32 v17, 0, v13
-; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17
-; GFX9-NEXT: v_max_i32_e32 v19, 0, v13
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v29
-; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_add_u32_e32 v13, v13, v17
-; GFX9-NEXT: v_min_i32_e32 v17, 0, v14
-; GFX9-NEXT: v_sub_u32_e32 v17, v16, v17
-; GFX9-NEXT: v_max_i32_e32 v19, 0, v14
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v30
-; GFX9-NEXT: v_sub_u32_e32 v19, v18, v19
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_add_u32_e32 v14, v14, v17
-; GFX9-NEXT: v_max_i32_e32 v17, 0, v15
-; GFX9-NEXT: v_sub_u32_e32 v17, v18, v17
-; GFX9-NEXT: v_min_i32_e32 v18, 0, v15
-; GFX9-NEXT: v_sub_u32_e32 v16, v16, v18
-; GFX9-NEXT: v_max_i32_e32 v16, v16, v31
-; GFX9-NEXT: v_min_i32_e32 v16, v16, v17
-; GFX9-NEXT: v_add_u32_e32 v15, v15, v16
+; GFX9-NEXT: v_add_i32 v0, v0, v16 clamp
+; GFX9-NEXT: v_add_i32 v1, v1, v17 clamp
+; GFX9-NEXT: v_add_i32 v2, v2, v18 clamp
+; GFX9-NEXT: v_add_i32 v3, v3, v19 clamp
+; GFX9-NEXT: v_add_i32 v4, v4, v20 clamp
+; GFX9-NEXT: v_add_i32 v5, v5, v21 clamp
+; GFX9-NEXT: v_add_i32 v6, v6, v22 clamp
+; GFX9-NEXT: v_add_i32 v7, v7, v23 clamp
+; GFX9-NEXT: v_add_i32 v8, v8, v24 clamp
+; GFX9-NEXT: v_add_i32 v9, v9, v25 clamp
+; GFX9-NEXT: v_add_i32 v10, v10, v26 clamp
+; GFX9-NEXT: v_add_i32 v11, v11, v27 clamp
+; GFX9-NEXT: v_add_i32 v12, v12, v28 clamp
+; GFX9-NEXT: v_add_i32 v13, v13, v29 clamp
+; GFX9-NEXT: v_add_i32 v14, v14, v30 clamp
+; GFX9-NEXT: v_add_i32 v15, v15, v31 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_saddsat_v16i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_min_i32_e32 v32, 0, v0
-; GFX10-NEXT: s_brev_b32 s4, 1
-; GFX10-NEXT: v_max_i32_e32 v33, 0, v0
-; GFX10-NEXT: s_brev_b32 s5, -2
-; GFX10-NEXT: v_min_i32_e32 v36, 0, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v35, s4, v32
-; GFX10-NEXT: v_min_i32_e32 v32, 0, v1
-; GFX10-NEXT: v_sub_nc_u32_e32 v33, s5, v33
-; GFX10-NEXT: v_max_i32_e32 v37, 0, v1
-; GFX10-NEXT: v_sub_nc_u32_e32 v36, s4, v36
-; GFX10-NEXT: v_max_i32_e32 v16, v35, v16
-; GFX10-NEXT: v_sub_nc_u32_e32 v32, s4, v32
-; GFX10-NEXT: v_bfrev_b32_e32 v35, 1
-; GFX10-NEXT: v_min_i32_e32 v38, 0, v3
-; GFX10-NEXT: v_max_i32_e32 v18, v36, v18
-; GFX10-NEXT: v_min_i32_e32 v16, v16, v33
-; GFX10-NEXT: v_max_i32_e32 v33, 0, v2
-; GFX10-NEXT: v_max_i32_e32 v39, v32, v17
-; GFX10-NEXT: v_sub_nc_u32_e32 v36, v35, v38
-; GFX10-NEXT: v_sub_nc_u32_e32 v37, s5, v37
-; GFX10-NEXT: v_bfrev_b32_e32 v34, -2
-; GFX10-NEXT: v_sub_nc_u32_e32 v32, s5, v33
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v16
-; GFX10-NEXT: v_max_i32_e32 v33, 0, v3
-; GFX10-NEXT: v_min_i32_e32 v39, v39, v37
-; GFX10-NEXT: v_max_i32_e32 v19, v36, v19
-; GFX10-NEXT: v_min_i32_e32 v16, v18, v32
-; GFX10-NEXT: v_min_i32_e32 v32, 0, v6
-; GFX10-NEXT: v_sub_nc_u32_e32 v18, v34, v33
-; GFX10-NEXT: v_min_i32_e32 v38, 0, v5
-; GFX10-NEXT: v_max_i32_e32 v17, 0, v4
-; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v16
-; GFX10-NEXT: v_min_i32_e32 v16, 0, v4
-; GFX10-NEXT: v_min_i32_e32 v18, v19, v18
-; GFX10-NEXT: v_sub_nc_u32_e32 v19, v35, v38
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v39
-; GFX10-NEXT: v_sub_nc_u32_e32 v32, v35, v32
-; GFX10-NEXT: v_sub_nc_u32_e32 v39, v35, v16
-; GFX10-NEXT: v_max_i32_e32 v33, 0, v5
-; GFX10-NEXT: v_max_i32_e32 v36, 0, v6
-; GFX10-NEXT: v_max_i32_e32 v19, v19, v21
-; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v18
-; GFX10-NEXT: v_max_i32_e32 v16, v39, v20
-; GFX10-NEXT: v_sub_nc_u32_e32 v17, v34, v17
-; GFX10-NEXT: v_sub_nc_u32_e32 v20, v34, v33
-; GFX10-NEXT: v_sub_nc_u32_e32 v21, v34, v36
-; GFX10-NEXT: v_max_i32_e32 v22, v32, v22
-; GFX10-NEXT: v_min_i32_e32 v18, 0, v7
-; GFX10-NEXT: v_min_i32_e32 v39, v16, v17
-; GFX10-NEXT: v_min_i32_e32 v38, v19, v20
-; GFX10-NEXT: v_max_i32_e32 v16, 0, v7
-; GFX10-NEXT: v_min_i32_e32 v19, v22, v21
-; GFX10-NEXT: v_sub_nc_u32_e32 v17, v35, v18
-; GFX10-NEXT: v_min_i32_e32 v18, 0, v8
-; GFX10-NEXT: v_min_i32_e32 v20, 0, v9
-; GFX10-NEXT: v_sub_nc_u32_e32 v16, v34, v16
-; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v19
-; GFX10-NEXT: v_max_i32_e32 v19, 0, v8
-; GFX10-NEXT: v_max_i32_e32 v17, v17, v23
-; GFX10-NEXT: v_sub_nc_u32_e32 v18, v35, v18
-; GFX10-NEXT: v_min_i32_e32 v22, 0, v10
-; GFX10-NEXT: v_max_i32_e32 v21, 0, v9
-; GFX10-NEXT: v_sub_nc_u32_e32 v20, v35, v20
-; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v39
-; GFX10-NEXT: v_max_i32_e32 v18, v18, v24
-; GFX10-NEXT: v_sub_nc_u32_e32 v39, v35, v22
-; GFX10-NEXT: v_min_i32_e32 v16, v17, v16
-; GFX10-NEXT: v_sub_nc_u32_e32 v19, v34, v19
-; GFX10-NEXT: v_max_i32_e32 v23, 0, v10
-; GFX10-NEXT: v_max_i32_e32 v20, v20, v25
-; GFX10-NEXT: v_sub_nc_u32_e32 v21, v34, v21
-; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v16
-; GFX10-NEXT: v_min_i32_e32 v17, v18, v19
-; GFX10-NEXT: v_min_i32_e32 v16, 0, v11
-; GFX10-NEXT: v_sub_nc_u32_e32 v18, v34, v23
-; GFX10-NEXT: v_max_i32_e32 v19, v39, v26
-; GFX10-NEXT: v_min_i32_e32 v22, 0, v12
-; GFX10-NEXT: v_min_i32_e32 v20, v20, v21
-; GFX10-NEXT: v_sub_nc_u32_e32 v16, v35, v16
-; GFX10-NEXT: v_min_i32_e32 v26, 0, v15
-; GFX10-NEXT: v_add_nc_u32_e32 v8, v8, v17
-; GFX10-NEXT: v_min_i32_e32 v17, v19, v18
-; GFX10-NEXT: v_sub_nc_u32_e32 v19, v35, v22
-; GFX10-NEXT: v_min_i32_e32 v22, 0, v14
-; GFX10-NEXT: v_min_i32_e32 v21, 0, v13
-; GFX10-NEXT: v_max_i32_e32 v24, 0, v14
-; GFX10-NEXT: v_max_i32_e32 v25, 0, v15
-; GFX10-NEXT: v_add_nc_u32_e32 v9, v9, v20
-; GFX10-NEXT: v_max_i32_e32 v20, 0, v13
-; GFX10-NEXT: v_sub_nc_u32_e32 v39, v35, v22
-; GFX10-NEXT: v_max_i32_e32 v23, 0, v11
-; GFX10-NEXT: v_add_nc_u32_e32 v10, v10, v17
-; GFX10-NEXT: v_max_i32_e32 v17, 0, v12
-; GFX10-NEXT: v_max_i32_e32 v16, v16, v27
-; GFX10-NEXT: v_sub_nc_u32_e32 v27, v35, v21
-; GFX10-NEXT: v_sub_nc_u32_e32 v26, v35, v26
-; GFX10-NEXT: v_sub_nc_u32_e32 v18, v34, v23
-; GFX10-NEXT: v_sub_nc_u32_e32 v17, v34, v17
-; GFX10-NEXT: v_max_i32_e32 v19, v19, v28
-; GFX10-NEXT: v_sub_nc_u32_e32 v20, v34, v20
-; GFX10-NEXT: v_max_i32_e32 v21, v27, v29
-; GFX10-NEXT: v_sub_nc_u32_e32 v24, v34, v24
-; GFX10-NEXT: v_max_i32_e32 v22, v39, v30
-; GFX10-NEXT: v_sub_nc_u32_e32 v25, v34, v25
-; GFX10-NEXT: v_max_i32_e32 v23, v26, v31
-; GFX10-NEXT: v_min_i32_e32 v16, v16, v18
-; GFX10-NEXT: v_min_i32_e32 v17, v19, v17
-; GFX10-NEXT: v_min_i32_e32 v18, v21, v20
-; GFX10-NEXT: v_min_i32_e32 v19, v22, v24
-; GFX10-NEXT: v_min_i32_e32 v20, v23, v25
-; GFX10-NEXT: v_add_nc_u32_e32 v5, v5, v38
-; GFX10-NEXT: v_add_nc_u32_e32 v11, v11, v16
-; GFX10-NEXT: v_add_nc_u32_e32 v12, v12, v17
-; GFX10-NEXT: v_add_nc_u32_e32 v13, v13, v18
-; GFX10-NEXT: v_add_nc_u32_e32 v14, v14, v19
-; GFX10-NEXT: v_add_nc_u32_e32 v15, v15, v20
+; GFX10-NEXT: v_add_nc_i32 v0, v0, v16 clamp
+; GFX10-NEXT: v_add_nc_i32 v1, v1, v17 clamp
+; GFX10-NEXT: v_add_nc_i32 v2, v2, v18 clamp
+; GFX10-NEXT: v_add_nc_i32 v3, v3, v19 clamp
+; GFX10-NEXT: v_add_nc_i32 v4, v4, v20 clamp
+; GFX10-NEXT: v_add_nc_i32 v5, v5, v21 clamp
+; GFX10-NEXT: v_add_nc_i32 v6, v6, v22 clamp
+; GFX10-NEXT: v_add_nc_i32 v7, v7, v23 clamp
+; GFX10-NEXT: v_add_nc_i32 v8, v8, v24 clamp
+; GFX10-NEXT: v_add_nc_i32 v9, v9, v25 clamp
+; GFX10-NEXT: v_add_nc_i32 v10, v10, v26 clamp
+; GFX10-NEXT: v_add_nc_i32 v11, v11, v27 clamp
+; GFX10-NEXT: v_add_nc_i32 v12, v12, v28 clamp
+; GFX10-NEXT: v_add_nc_i32 v13, v13, v29 clamp
+; GFX10-NEXT: v_add_nc_i32 v14, v14, v30 clamp
+; GFX10-NEXT: v_add_nc_i32 v15, v15, v31 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
@@ -3844,367 +2734,91 @@ define amdgpu_ps <16 x i32> @s_saddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32>
;
; GFX9-LABEL: s_saddsat_v16i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_gt_i32 s0, 0
-; GFX9-NEXT: s_brev_b32 s32, -2
-; GFX9-NEXT: s_cselect_b32 s34, s0, 0
-; GFX9-NEXT: s_sub_i32 s34, s32, s34
-; GFX9-NEXT: s_cmp_lt_i32 s0, 0
-; GFX9-NEXT: s_brev_b32 s33, 1
-; GFX9-NEXT: s_cselect_b32 s35, s0, 0
-; GFX9-NEXT: s_sub_i32 s35, s33, s35
-; GFX9-NEXT: s_cmp_gt_i32 s35, s16
-; GFX9-NEXT: s_cselect_b32 s16, s35, s16
-; GFX9-NEXT: s_cmp_lt_i32 s16, s34
-; GFX9-NEXT: s_cselect_b32 s16, s16, s34
-; GFX9-NEXT: s_add_i32 s0, s0, s16
-; GFX9-NEXT: s_cmp_gt_i32 s1, 0
-; GFX9-NEXT: s_cselect_b32 s16, s1, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s1, 0
-; GFX9-NEXT: s_cselect_b32 s34, s1, 0
-; GFX9-NEXT: s_sub_i32 s34, s33, s34
-; GFX9-NEXT: s_cmp_gt_i32 s34, s17
-; GFX9-NEXT: s_cselect_b32 s17, s34, s17
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s1, s1, s16
-; GFX9-NEXT: s_cmp_gt_i32 s2, 0
-; GFX9-NEXT: s_cselect_b32 s16, s2, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s2, 0
-; GFX9-NEXT: s_cselect_b32 s17, s2, 0
-; GFX9-NEXT: s_sub_i32 s17, s33, s17
-; GFX9-NEXT: s_cmp_gt_i32 s17, s18
-; GFX9-NEXT: s_cselect_b32 s17, s17, s18
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s2, s2, s16
-; GFX9-NEXT: s_cmp_gt_i32 s3, 0
-; GFX9-NEXT: s_cselect_b32 s16, s3, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s3, 0
-; GFX9-NEXT: s_cselect_b32 s17, s3, 0
-; GFX9-NEXT: s_sub_i32 s17, s33, s17
-; GFX9-NEXT: s_cmp_gt_i32 s17, s19
-; GFX9-NEXT: s_cselect_b32 s17, s17, s19
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s3, s3, s16
-; GFX9-NEXT: s_cmp_gt_i32 s4, 0
-; GFX9-NEXT: s_cselect_b32 s16, s4, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s4, 0
-; GFX9-NEXT: s_cselect_b32 s17, s4, 0
-; GFX9-NEXT: s_sub_i32 s17, s33, s17
-; GFX9-NEXT: s_cmp_gt_i32 s17, s20
-; GFX9-NEXT: s_cselect_b32 s17, s17, s20
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s4, s4, s16
-; GFX9-NEXT: s_cmp_gt_i32 s5, 0
-; GFX9-NEXT: s_cselect_b32 s16, s5, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s5, 0
-; GFX9-NEXT: s_cselect_b32 s17, s5, 0
-; GFX9-NEXT: s_sub_i32 s17, s33, s17
-; GFX9-NEXT: s_cmp_gt_i32 s17, s21
-; GFX9-NEXT: s_cselect_b32 s17, s17, s21
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s5, s5, s16
-; GFX9-NEXT: s_cmp_gt_i32 s6, 0
-; GFX9-NEXT: s_cselect_b32 s16, s6, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s6, 0
-; GFX9-NEXT: s_cselect_b32 s17, s6, 0
-; GFX9-NEXT: s_sub_i32 s17, s33, s17
-; GFX9-NEXT: s_cmp_gt_i32 s17, s22
-; GFX9-NEXT: s_cselect_b32 s17, s17, s22
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s6, s6, s16
-; GFX9-NEXT: s_cmp_gt_i32 s7, 0
-; GFX9-NEXT: s_cselect_b32 s16, s7, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s7, 0
-; GFX9-NEXT: s_cselect_b32 s17, s7, 0
-; GFX9-NEXT: s_sub_i32 s17, s33, s17
-; GFX9-NEXT: s_cmp_gt_i32 s17, s23
-; GFX9-NEXT: s_cselect_b32 s17, s17, s23
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s7, s7, s16
-; GFX9-NEXT: s_cmp_gt_i32 s8, 0
-; GFX9-NEXT: s_cselect_b32 s16, s8, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s8, 0
-; GFX9-NEXT: s_cselect_b32 s17, s8, 0
-; GFX9-NEXT: s_sub_i32 s17, s33, s17
-; GFX9-NEXT: s_cmp_gt_i32 s17, s24
-; GFX9-NEXT: s_cselect_b32 s17, s17, s24
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s8, s8, s16
-; GFX9-NEXT: s_cmp_gt_i32 s9, 0
-; GFX9-NEXT: s_cselect_b32 s16, s9, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s9, 0
-; GFX9-NEXT: s_cselect_b32 s17, s9, 0
-; GFX9-NEXT: s_sub_i32 s17, s33, s17
-; GFX9-NEXT: s_cmp_gt_i32 s17, s25
-; GFX9-NEXT: s_cselect_b32 s17, s17, s25
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s9, s9, s16
-; GFX9-NEXT: s_cmp_gt_i32 s10, 0
-; GFX9-NEXT: s_cselect_b32 s16, s10, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s10, 0
-; GFX9-NEXT: s_cselect_b32 s17, s10, 0
-; GFX9-NEXT: s_sub_i32 s17, s33, s17
-; GFX9-NEXT: s_cmp_gt_i32 s17, s26
-; GFX9-NEXT: s_cselect_b32 s17, s17, s26
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s10, s10, s16
-; GFX9-NEXT: s_cmp_gt_i32 s11, 0
-; GFX9-NEXT: s_cselect_b32 s16, s11, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s11, 0
-; GFX9-NEXT: s_cselect_b32 s17, s11, 0
-; GFX9-NEXT: s_sub_i32 s17, s33, s17
-; GFX9-NEXT: s_cmp_gt_i32 s17, s27
-; GFX9-NEXT: s_cselect_b32 s17, s17, s27
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s11, s11, s16
-; GFX9-NEXT: s_cmp_gt_i32 s12, 0
-; GFX9-NEXT: s_cselect_b32 s16, s12, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s12, 0
-; GFX9-NEXT: s_cselect_b32 s17, s12, 0
-; GFX9-NEXT: s_sub_i32 s17, s33, s17
-; GFX9-NEXT: s_cmp_gt_i32 s17, s28
-; GFX9-NEXT: s_cselect_b32 s17, s17, s28
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s12, s12, s16
-; GFX9-NEXT: s_cmp_gt_i32 s13, 0
-; GFX9-NEXT: s_cselect_b32 s16, s13, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s13, 0
-; GFX9-NEXT: s_cselect_b32 s17, s13, 0
-; GFX9-NEXT: s_sub_i32 s17, s33, s17
-; GFX9-NEXT: s_cmp_gt_i32 s17, s29
-; GFX9-NEXT: s_cselect_b32 s17, s17, s29
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s13, s13, s16
-; GFX9-NEXT: s_cmp_gt_i32 s14, 0
-; GFX9-NEXT: s_cselect_b32 s16, s14, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s14, 0
-; GFX9-NEXT: s_cselect_b32 s17, s14, 0
-; GFX9-NEXT: s_sub_i32 s17, s33, s17
-; GFX9-NEXT: s_cmp_gt_i32 s17, s30
-; GFX9-NEXT: s_cselect_b32 s17, s17, s30
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s14, s14, s16
-; GFX9-NEXT: s_cmp_gt_i32 s15, 0
-; GFX9-NEXT: s_cselect_b32 s16, s15, 0
-; GFX9-NEXT: s_sub_i32 s16, s32, s16
-; GFX9-NEXT: s_cmp_lt_i32 s15, 0
-; GFX9-NEXT: s_cselect_b32 s17, s15, 0
-; GFX9-NEXT: s_sub_i32 s17, s33, s17
-; GFX9-NEXT: s_cmp_gt_i32 s17, s31
-; GFX9-NEXT: s_cselect_b32 s17, s17, s31
-; GFX9-NEXT: s_cmp_lt_i32 s17, s16
-; GFX9-NEXT: s_cselect_b32 s16, s17, s16
-; GFX9-NEXT: s_add_i32 s15, s15, s16
+; GFX9-NEXT: v_mov_b32_e32 v0, s16
+; GFX9-NEXT: v_mov_b32_e32 v1, s17
+; GFX9-NEXT: v_mov_b32_e32 v2, s18
+; GFX9-NEXT: v_mov_b32_e32 v3, s19
+; GFX9-NEXT: v_mov_b32_e32 v4, s20
+; GFX9-NEXT: v_mov_b32_e32 v5, s21
+; GFX9-NEXT: v_mov_b32_e32 v6, s22
+; GFX9-NEXT: v_mov_b32_e32 v7, s23
+; GFX9-NEXT: v_mov_b32_e32 v8, s24
+; GFX9-NEXT: v_mov_b32_e32 v9, s25
+; GFX9-NEXT: v_mov_b32_e32 v10, s26
+; GFX9-NEXT: v_mov_b32_e32 v11, s27
+; GFX9-NEXT: v_mov_b32_e32 v12, s28
+; GFX9-NEXT: v_mov_b32_e32 v13, s29
+; GFX9-NEXT: v_mov_b32_e32 v14, s30
+; GFX9-NEXT: v_mov_b32_e32 v15, s31
+; GFX9-NEXT: v_add_i32 v0, s0, v0 clamp
+; GFX9-NEXT: v_add_i32 v1, s1, v1 clamp
+; GFX9-NEXT: v_add_i32 v2, s2, v2 clamp
+; GFX9-NEXT: v_add_i32 v3, s3, v3 clamp
+; GFX9-NEXT: v_add_i32 v4, s4, v4 clamp
+; GFX9-NEXT: v_add_i32 v5, s5, v5 clamp
+; GFX9-NEXT: v_add_i32 v6, s6, v6 clamp
+; GFX9-NEXT: v_add_i32 v7, s7, v7 clamp
+; GFX9-NEXT: v_add_i32 v8, s8, v8 clamp
+; GFX9-NEXT: v_add_i32 v9, s9, v9 clamp
+; GFX9-NEXT: v_add_i32 v10, s10, v10 clamp
+; GFX9-NEXT: v_add_i32 v11, s11, v11 clamp
+; GFX9-NEXT: v_add_i32 v12, s12, v12 clamp
+; GFX9-NEXT: v_add_i32 v13, s13, v13 clamp
+; GFX9-NEXT: v_add_i32 v14, s14, v14 clamp
+; GFX9-NEXT: v_add_i32 v15, s15, v15 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
+; GFX9-NEXT: v_readfirstlane_b32 s4, v4
+; GFX9-NEXT: v_readfirstlane_b32 s5, v5
+; GFX9-NEXT: v_readfirstlane_b32 s6, v6
+; GFX9-NEXT: v_readfirstlane_b32 s7, v7
+; GFX9-NEXT: v_readfirstlane_b32 s8, v8
+; GFX9-NEXT: v_readfirstlane_b32 s9, v9
+; GFX9-NEXT: v_readfirstlane_b32 s10, v10
+; GFX9-NEXT: v_readfirstlane_b32 s11, v11
+; GFX9-NEXT: v_readfirstlane_b32 s12, v12
+; GFX9-NEXT: v_readfirstlane_b32 s13, v13
+; GFX9-NEXT: v_readfirstlane_b32 s14, v14
+; GFX9-NEXT: v_readfirstlane_b32 s15, v15
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_v16i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_gt_i32 s0, 0
-; GFX10-NEXT: s_brev_b32 s32, -2
-; GFX10-NEXT: s_cselect_b32 s33, s0, 0
-; GFX10-NEXT: s_brev_b32 s34, 1
-; GFX10-NEXT: s_sub_i32 s46, s32, s33
-; GFX10-NEXT: s_cmp_lt_i32 s0, 0
+; GFX10-NEXT: v_add_nc_i32 v0, s0, s16 clamp
+; GFX10-NEXT: v_add_nc_i32 v1, s1, s17 clamp
+; GFX10-NEXT: v_add_nc_i32 v2, s2, s18 clamp
+; GFX10-NEXT: v_add_nc_i32 v3, s3, s19 clamp
+; GFX10-NEXT: v_add_nc_i32 v4, s4, s20 clamp
+; GFX10-NEXT: v_add_nc_i32 v5, s5, s21 clamp
+; GFX10-NEXT: v_add_nc_i32 v6, s6, s22 clamp
+; GFX10-NEXT: v_add_nc_i32 v7, s7, s23 clamp
+; GFX10-NEXT: v_add_nc_i32 v8, s8, s24 clamp
+; GFX10-NEXT: v_add_nc_i32 v9, s9, s25 clamp
+; GFX10-NEXT: v_add_nc_i32 v10, s10, s26 clamp
+; GFX10-NEXT: v_add_nc_i32 v11, s11, s27 clamp
+; GFX10-NEXT: v_add_nc_i32 v12, s12, s28 clamp
+; GFX10-NEXT: v_add_nc_i32 v13, s13, s29 clamp
+; GFX10-NEXT: v_add_nc_i32 v14, s14, s30 clamp
+; GFX10-NEXT: v_add_nc_i32 v15, s15, s31 clamp
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10-NEXT: v_readfirstlane_b32 s8, v8
+; GFX10-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10-NEXT: v_readfirstlane_b32 s10, v10
+; GFX10-NEXT: v_readfirstlane_b32 s11, v11
+; GFX10-NEXT: v_readfirstlane_b32 s12, v12
+; GFX10-NEXT: v_readfirstlane_b32 s13, v13
+; GFX10-NEXT: v_readfirstlane_b32 s14, v14
+; GFX10-NEXT: v_readfirstlane_b32 s15, v15
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s35, s0, 0
-; GFX10-NEXT: s_sub_i32 s35, s34, s35
-; GFX10-NEXT: s_cmp_gt_i32 s35, s16
-; GFX10-NEXT: s_cselect_b32 s16, s35, s16
-; GFX10-NEXT: s_cmp_lt_i32 s16, s46
-; GFX10-NEXT: s_cselect_b32 s46, s16, s46
-; GFX10-NEXT: s_add_i32 s0, s0, s46
-; GFX10-NEXT: s_cmp_gt_i32 s1, 0
-; GFX10-NEXT: s_cselect_b32 s46, s1, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s46
-; GFX10-NEXT: s_cmp_lt_i32 s1, 0
-; GFX10-NEXT: s_cselect_b32 s33, s1, 0
-; GFX10-NEXT: s_sub_i32 s46, s34, s33
-; GFX10-NEXT: s_cmp_gt_i32 s46, s17
-; GFX10-NEXT: s_cselect_b32 s17, s46, s17
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s46, s17, s16
-; GFX10-NEXT: s_add_i32 s1, s1, s46
-; GFX10-NEXT: s_cmp_gt_i32 s2, 0
-; GFX10-NEXT: s_cselect_b32 s46, s2, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s46
-; GFX10-NEXT: s_cmp_lt_i32 s2, 0
-; GFX10-NEXT: s_cselect_b32 s17, s2, 0
-; GFX10-NEXT: s_sub_i32 s17, s34, s17
-; GFX10-NEXT: s_cmp_gt_i32 s17, s18
-; GFX10-NEXT: s_cselect_b32 s17, s17, s18
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s16, s17, s16
-; GFX10-NEXT: s_add_i32 s2, s2, s16
-; GFX10-NEXT: s_cmp_gt_i32 s3, 0
-; GFX10-NEXT: s_cselect_b32 s46, s3, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s46
-; GFX10-NEXT: s_cmp_lt_i32 s3, 0
-; GFX10-NEXT: s_cselect_b32 s17, s3, 0
-; GFX10-NEXT: s_sub_i32 s17, s34, s17
-; GFX10-NEXT: s_cmp_gt_i32 s17, s19
-; GFX10-NEXT: s_cselect_b32 s17, s17, s19
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s16, s17, s16
-; GFX10-NEXT: s_add_i32 s3, s3, s16
-; GFX10-NEXT: s_cmp_gt_i32 s4, 0
-; GFX10-NEXT: s_cselect_b32 s46, s4, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s46
-; GFX10-NEXT: s_cmp_lt_i32 s4, 0
-; GFX10-NEXT: s_cselect_b32 s17, s4, 0
-; GFX10-NEXT: s_sub_i32 s17, s34, s17
-; GFX10-NEXT: s_cmp_gt_i32 s17, s20
-; GFX10-NEXT: s_cselect_b32 s17, s17, s20
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s16, s17, s16
-; GFX10-NEXT: s_add_i32 s4, s4, s16
-; GFX10-NEXT: s_cmp_gt_i32 s5, 0
-; GFX10-NEXT: s_cselect_b32 s46, s5, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s46
-; GFX10-NEXT: s_cmp_lt_i32 s5, 0
-; GFX10-NEXT: s_cselect_b32 s17, s5, 0
-; GFX10-NEXT: s_sub_i32 s17, s34, s17
-; GFX10-NEXT: s_cmp_gt_i32 s17, s21
-; GFX10-NEXT: s_cselect_b32 s17, s17, s21
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s16, s17, s16
-; GFX10-NEXT: s_add_i32 s5, s5, s16
-; GFX10-NEXT: s_cmp_gt_i32 s6, 0
-; GFX10-NEXT: s_cselect_b32 s46, s6, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s46
-; GFX10-NEXT: s_cmp_lt_i32 s6, 0
-; GFX10-NEXT: s_cselect_b32 s17, s6, 0
-; GFX10-NEXT: s_sub_i32 s17, s34, s17
-; GFX10-NEXT: s_cmp_gt_i32 s17, s22
-; GFX10-NEXT: s_cselect_b32 s17, s17, s22
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s16, s17, s16
-; GFX10-NEXT: s_add_i32 s6, s6, s16
-; GFX10-NEXT: s_cmp_gt_i32 s7, 0
-; GFX10-NEXT: s_cselect_b32 s46, s7, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s46
-; GFX10-NEXT: s_cmp_lt_i32 s7, 0
-; GFX10-NEXT: s_cselect_b32 s17, s7, 0
-; GFX10-NEXT: s_sub_i32 s17, s34, s17
-; GFX10-NEXT: s_cmp_gt_i32 s17, s23
-; GFX10-NEXT: s_cselect_b32 s17, s17, s23
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s16, s17, s16
-; GFX10-NEXT: s_add_i32 s7, s7, s16
-; GFX10-NEXT: s_cmp_gt_i32 s8, 0
-; GFX10-NEXT: s_cselect_b32 s46, s8, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s46
-; GFX10-NEXT: s_cmp_lt_i32 s8, 0
-; GFX10-NEXT: s_cselect_b32 s17, s8, 0
-; GFX10-NEXT: s_sub_i32 s17, s34, s17
-; GFX10-NEXT: s_cmp_gt_i32 s17, s24
-; GFX10-NEXT: s_cselect_b32 s17, s17, s24
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s16, s17, s16
-; GFX10-NEXT: s_add_i32 s8, s8, s16
-; GFX10-NEXT: s_cmp_gt_i32 s9, 0
-; GFX10-NEXT: s_cselect_b32 s46, s9, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s46
-; GFX10-NEXT: s_cmp_lt_i32 s9, 0
-; GFX10-NEXT: s_cselect_b32 s17, s9, 0
-; GFX10-NEXT: s_sub_i32 s17, s34, s17
-; GFX10-NEXT: s_cmp_gt_i32 s17, s25
-; GFX10-NEXT: s_cselect_b32 s17, s17, s25
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s16, s17, s16
-; GFX10-NEXT: s_add_i32 s9, s9, s16
-; GFX10-NEXT: s_cmp_gt_i32 s10, 0
-; GFX10-NEXT: s_cselect_b32 s46, s10, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s46
-; GFX10-NEXT: s_cmp_lt_i32 s10, 0
-; GFX10-NEXT: s_cselect_b32 s17, s10, 0
-; GFX10-NEXT: s_sub_i32 s17, s34, s17
-; GFX10-NEXT: s_cmp_gt_i32 s17, s26
-; GFX10-NEXT: s_cselect_b32 s17, s17, s26
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s16, s17, s16
-; GFX10-NEXT: s_add_i32 s10, s10, s16
-; GFX10-NEXT: s_cmp_gt_i32 s11, 0
-; GFX10-NEXT: s_cselect_b32 s46, s11, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s46
-; GFX10-NEXT: s_cmp_lt_i32 s11, 0
-; GFX10-NEXT: s_cselect_b32 s17, s11, 0
-; GFX10-NEXT: s_sub_i32 s17, s34, s17
-; GFX10-NEXT: s_cmp_gt_i32 s17, s27
-; GFX10-NEXT: s_cselect_b32 s17, s17, s27
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s16, s17, s16
-; GFX10-NEXT: s_add_i32 s11, s11, s16
-; GFX10-NEXT: s_cmp_gt_i32 s12, 0
-; GFX10-NEXT: s_cselect_b32 s46, s12, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s46
-; GFX10-NEXT: s_cmp_lt_i32 s12, 0
-; GFX10-NEXT: s_cselect_b32 s17, s12, 0
-; GFX10-NEXT: s_sub_i32 s17, s34, s17
-; GFX10-NEXT: s_cmp_gt_i32 s17, s28
-; GFX10-NEXT: s_cselect_b32 s17, s17, s28
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s16, s17, s16
-; GFX10-NEXT: s_add_i32 s12, s12, s16
-; GFX10-NEXT: s_cmp_gt_i32 s13, 0
-; GFX10-NEXT: s_cselect_b32 s46, s13, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s46
-; GFX10-NEXT: s_cmp_lt_i32 s13, 0
-; GFX10-NEXT: s_cselect_b32 s17, s13, 0
-; GFX10-NEXT: s_sub_i32 s17, s34, s17
-; GFX10-NEXT: s_cmp_gt_i32 s17, s29
-; GFX10-NEXT: s_cselect_b32 s17, s17, s29
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s16, s17, s16
-; GFX10-NEXT: s_add_i32 s13, s13, s16
-; GFX10-NEXT: s_cmp_gt_i32 s14, 0
-; GFX10-NEXT: s_cselect_b32 s46, s14, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s46
-; GFX10-NEXT: s_cmp_lt_i32 s14, 0
-; GFX10-NEXT: s_cselect_b32 s17, s14, 0
-; GFX10-NEXT: s_sub_i32 s17, s34, s17
-; GFX10-NEXT: s_cmp_gt_i32 s17, s30
-; GFX10-NEXT: s_cselect_b32 s17, s17, s30
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s16, s17, s16
-; GFX10-NEXT: s_add_i32 s14, s14, s16
-; GFX10-NEXT: s_cmp_gt_i32 s15, 0
-; GFX10-NEXT: s_cselect_b32 s30, s15, 0
-; GFX10-NEXT: s_sub_i32 s16, s32, s30
-; GFX10-NEXT: s_cmp_lt_i32 s15, 0
-; GFX10-NEXT: s_cselect_b32 s17, s15, 0
-; GFX10-NEXT: s_sub_i32 s17, s34, s17
-; GFX10-NEXT: s_cmp_gt_i32 s17, s31
-; GFX10-NEXT: s_cselect_b32 s17, s17, s31
-; GFX10-NEXT: s_cmp_lt_i32 s17, s16
-; GFX10-NEXT: s_cselect_b32 s16, s17, s16
-; GFX10-NEXT: s_add_i32 s15, s15, s16
; GFX10-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
@@ -4241,27 +2855,15 @@ define i16 @v_saddsat_i16(i16 %lhs, i16 %rhs) {
; GFX9-LABEL: v_saddsat_i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_i16_e32 v3, 0, v0
-; GFX9-NEXT: v_max_i16_e32 v2, 0, v0
-; GFX9-NEXT: v_sub_u16_e32 v3, 0x8000, v3
-; GFX9-NEXT: v_sub_u16_e32 v2, 0x7fff, v2
-; GFX9-NEXT: v_max_i16_e32 v1, v3, v1
-; GFX9-NEXT: v_min_i16_e32 v1, v1, v2
-; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_saddsat_i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_min_i16_e64 v2, v0, 0
-; GFX10-NEXT: v_max_i16_e64 v3, v0, 0
+; GFX10-NEXT: v_add_nc_i16 v0, v0, v1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u16_e64 v2, 0x8000, v2
-; GFX10-NEXT: v_sub_nc_u16_e64 v3, 0x7fff, v3
-; GFX10-NEXT: v_max_i16_e64 v1, v2, v1
-; GFX10-NEXT: v_min_i16_e64 v1, v1, v3
-; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
@@ -4309,45 +2911,16 @@ define amdgpu_ps i16 @s_saddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
;
; GFX9-LABEL: s_saddsat_i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sext_i32_i16 s2, s0
-; GFX9-NEXT: s_sext_i32_i16 s3, 0
-; GFX9-NEXT: s_cmp_gt_i32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s4, s2, s3
-; GFX9-NEXT: s_sub_i32 s4, 0x7fff, s4
-; GFX9-NEXT: s_cmp_lt_i32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s2, s3
-; GFX9-NEXT: s_sub_i32 s2, 0xffff8000, s2
-; GFX9-NEXT: s_sext_i32_i16 s2, s2
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_cmp_gt_i32 s2, s1
-; GFX9-NEXT: s_cselect_b32 s1, s2, s1
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_sext_i32_i16 s2, s4
-; GFX9-NEXT: s_cmp_lt_i32 s1, s2
-; GFX9-NEXT: s_cselect_b32 s1, s1, s2
-; GFX9-NEXT: s_add_i32 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sext_i32_i16 s2, 0
-; GFX10-NEXT: s_sext_i32_i16 s3, s0
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_gt_i32 s3, s2
+; GFX10-NEXT: v_add_nc_i16 v0, s0, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s4, s3, s2
-; GFX10-NEXT: s_sub_i32 s4, 0x7fff, s4
-; GFX10-NEXT: s_cmp_lt_i32 s3, s2
-; GFX10-NEXT: s_cselect_b32 s2, s3, s2
-; GFX10-NEXT: s_sub_i32 s2, 0xffff8000, s2
-; GFX10-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-NEXT: s_cmp_gt_i32 s2, s1
-; GFX10-NEXT: s_cselect_b32 s1, s2, s1
-; GFX10-NEXT: s_sext_i32_i16 s2, s4
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s2
-; GFX10-NEXT: s_cselect_b32 s1, s1, s2
-; GFX10-NEXT: s_add_i32 s0, s0, s1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
@@ -4387,33 +2960,13 @@ define amdgpu_ps half @saddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
;
; GFX9-LABEL: saddsat_i16_sv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sext_i32_i16 s1, s0
-; GFX9-NEXT: s_sext_i32_i16 s2, 0
-; GFX9-NEXT: s_cmp_gt_i32 s1, s2
-; GFX9-NEXT: s_cselect_b32 s3, s1, s2
-; GFX9-NEXT: s_sub_i32 s3, 0x7fff, s3
-; GFX9-NEXT: s_cmp_lt_i32 s1, s2
-; GFX9-NEXT: s_cselect_b32 s1, s1, s2
-; GFX9-NEXT: s_sub_i32 s1, 0xffff8000, s1
-; GFX9-NEXT: v_max_i16_e32 v0, s1, v0
-; GFX9-NEXT: v_min_i16_e32 v0, s3, v0
-; GFX9-NEXT: v_add_u16_e32 v0, s0, v0
+; GFX9-NEXT: v_add_i16 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: saddsat_i16_sv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sext_i32_i16 s1, s0
-; GFX10-NEXT: s_sext_i32_i16 s2, 0
+; GFX10-NEXT: v_add_nc_i16 v0, s0, v0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cmp_gt_i32 s1, s2
-; GFX10-NEXT: s_cselect_b32 s3, s1, s2
-; GFX10-NEXT: s_sub_i32 s3, 0x7fff, s3
-; GFX10-NEXT: s_cmp_lt_i32 s1, s2
-; GFX10-NEXT: s_cselect_b32 s1, s1, s2
-; GFX10-NEXT: s_sub_i32 s1, 0xffff8000, s1
-; GFX10-NEXT: v_max_i16_e64 v0, s1, v0
-; GFX10-NEXT: v_min_i16_e64 v0, v0, s3
-; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
@@ -4448,25 +3001,13 @@ define amdgpu_ps half @saddsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
;
; GFX9-LABEL: saddsat_i16_vs:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_min_i16_e32 v2, 0, v0
-; GFX9-NEXT: v_max_i16_e32 v1, 0, v0
-; GFX9-NEXT: v_sub_u16_e32 v2, 0x8000, v2
-; GFX9-NEXT: v_sub_u16_e32 v1, 0x7fff, v1
-; GFX9-NEXT: v_max_i16_e32 v2, s0, v2
-; GFX9-NEXT: v_min_i16_e32 v1, v2, v1
-; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_add_i16 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: saddsat_i16_vs:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_min_i16_e64 v1, v0, 0
-; GFX10-NEXT: v_max_i16_e64 v2, v0, 0
+; GFX10-NEXT: v_add_nc_i16 v0, v0, s0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u16_e64 v1, 0x8000, v1
-; GFX10-NEXT: v_sub_nc_u16_e64 v2, 0x7fff, v2
-; GFX10-NEXT: v_max_i16_e64 v1, v1, s0
-; GFX10-NEXT: v_min_i16_e64 v1, v1, v2
-; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
@@ -4527,29 +3068,15 @@ define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX9-LABEL: v_saddsat_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_max_i16 v2, v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fff7fff
-; GFX9-NEXT: v_pk_sub_i16 v2, v3, v2
-; GFX9-NEXT: v_pk_min_i16 v3, v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v4, 0x80008000
-; GFX9-NEXT: v_pk_sub_i16 v3, v4, v3
-; GFX9-NEXT: v_pk_max_i16 v1, v3, v1
-; GFX9-NEXT: v_pk_min_i16 v1, v1, v2
-; GFX9-NEXT: v_pk_add_u16 v0, v0, v1
+; GFX9-NEXT: v_pk_add_i16 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_saddsat_v2i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_min_i16 v2, v0, 0
-; GFX10-NEXT: v_pk_max_i16 v3, v0, 0
+; GFX10-NEXT: v_pk_add_i16 v0, v0, v1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_sub_i16 v2, 0x80008000, v2
-; GFX10-NEXT: v_pk_sub_i16 v3, 0x7fff7fff, v3
-; GFX10-NEXT: v_pk_max_i16 v1, v2, v1
-; GFX10-NEXT: v_pk_min_i16 v1, v1, v3
-; GFX10-NEXT: v_pk_add_u16 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result
@@ -4642,99 +3169,16 @@ define amdgpu_ps i32 @s_saddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs
;
; GFX9-LABEL: s_saddsat_v2i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sext_i32_i16 s2, s0
-; GFX9-NEXT: s_ashr_i32 s3, s0, 16
-; GFX9-NEXT: s_sext_i32_i16 s4, 0
-; GFX9-NEXT: s_cmp_gt_i32 s2, s4
-; GFX9-NEXT: s_cselect_b32 s5, s2, s4
-; GFX9-NEXT: s_cmp_gt_i32 s3, 0
-; GFX9-NEXT: s_cselect_b32 s6, s3, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s6
-; GFX9-NEXT: s_lshr_b32 s6, s5, 16
-; GFX9-NEXT: s_sub_i32 s5, 0x7fff7fff, s5
-; GFX9-NEXT: s_sub_i32 s6, 0x7fff, s6
-; GFX9-NEXT: s_cmp_lt_i32 s2, s4
-; GFX9-NEXT: s_cselect_b32 s2, s2, s4
-; GFX9-NEXT: s_cmp_lt_i32 s3, 0
-; GFX9-NEXT: s_cselect_b32 s3, s3, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3
-; GFX9-NEXT: s_lshr_b32 s3, s2, 16
-; GFX9-NEXT: s_sub_i32 s2, 0x80008000, s2
-; GFX9-NEXT: s_sub_i32 s3, 0x8000, s3
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3
-; GFX9-NEXT: s_sext_i32_i16 s3, s2
-; GFX9-NEXT: s_sext_i32_i16 s4, s1
-; GFX9-NEXT: s_ashr_i32 s2, s2, 16
-; GFX9-NEXT: s_ashr_i32 s1, s1, 16
-; GFX9-NEXT: s_cmp_gt_i32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s3, s3, s4
-; GFX9-NEXT: s_cmp_gt_i32 s2, s1
-; GFX9-NEXT: s_cselect_b32 s1, s2, s1
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s3, s1
-; GFX9-NEXT: s_sext_i32_i16 s2, s1
-; GFX9-NEXT: s_ashr_i32 s1, s1, 16
-; GFX9-NEXT: s_sext_i32_i16 s3, s5
-; GFX9-NEXT: s_ashr_i32 s4, s5, 16
-; GFX9-NEXT: s_cmp_lt_i32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s2, s3
-; GFX9-NEXT: s_cmp_lt_i32 s1, s4
-; GFX9-NEXT: s_cselect_b32 s1, s1, s4
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s2, s1
-; GFX9-NEXT: s_lshr_b32 s2, s0, 16
-; GFX9-NEXT: s_lshr_b32 s3, s1, 16
-; GFX9-NEXT: s_add_i32 s0, s0, s1
-; GFX9-NEXT: s_add_i32 s2, s2, s3
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_pk_add_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_v2i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sext_i32_i16 s2, s0
-; GFX10-NEXT: s_sext_i32_i16 s3, 0
-; GFX10-NEXT: s_ashr_i32 s4, s0, 16
-; GFX10-NEXT: s_cmp_gt_i32 s2, s3
+; GFX10-NEXT: v_pk_add_i16 v0, s0, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s5, s2, s3
-; GFX10-NEXT: s_cmp_gt_i32 s4, 0
-; GFX10-NEXT: s_cselect_b32 s6, s4, 0
-; GFX10-NEXT: s_pack_ll_b32_b16 s5, s5, s6
-; GFX10-NEXT: s_lshr_b32 s6, s5, 16
-; GFX10-NEXT: s_sub_i32 s5, 0x7fff7fff, s5
-; GFX10-NEXT: s_sub_i32 s6, 0x7fff, s6
-; GFX10-NEXT: s_cmp_lt_i32 s2, s3
-; GFX10-NEXT: s_cselect_b32 s2, s2, s3
-; GFX10-NEXT: s_cmp_lt_i32 s4, 0
-; GFX10-NEXT: s_cselect_b32 s3, s4, 0
-; GFX10-NEXT: s_sext_i32_i16 s4, s1
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s3
-; GFX10-NEXT: s_ashr_i32 s1, s1, 16
-; GFX10-NEXT: s_lshr_b32 s3, s2, 16
-; GFX10-NEXT: s_sub_i32 s2, 0x80008000, s2
-; GFX10-NEXT: s_sub_i32 s3, 0x8000, s3
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s3
-; GFX10-NEXT: s_sext_i32_i16 s3, s2
-; GFX10-NEXT: s_ashr_i32 s2, s2, 16
-; GFX10-NEXT: s_cmp_gt_i32 s3, s4
-; GFX10-NEXT: s_cselect_b32 s3, s3, s4
-; GFX10-NEXT: s_cmp_gt_i32 s2, s1
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s5, s6
-; GFX10-NEXT: s_cselect_b32 s1, s2, s1
-; GFX10-NEXT: s_sext_i32_i16 s2, s4
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s3, s1
-; GFX10-NEXT: s_ashr_i32 s3, s4, 16
-; GFX10-NEXT: s_sext_i32_i16 s4, s1
-; GFX10-NEXT: s_ashr_i32 s1, s1, 16
-; GFX10-NEXT: s_cmp_lt_i32 s4, s2
-; GFX10-NEXT: s_cselect_b32 s2, s4, s2
-; GFX10-NEXT: s_cmp_lt_i32 s1, s3
-; GFX10-NEXT: s_cselect_b32 s1, s1, s3
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s2, s1
-; GFX10-NEXT: s_lshr_b32 s2, s0, 16
-; GFX10-NEXT: s_lshr_b32 s3, s1, 16
-; GFX10-NEXT: s_add_i32 s0, s0, s1
-; GFX10-NEXT: s_add_i32 s2, s2, s3
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to i32
@@ -4810,59 +3254,13 @@ define amdgpu_ps float @saddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
;
; GFX9-LABEL: saddsat_v2i16_sv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sext_i32_i16 s1, s0
-; GFX9-NEXT: s_ashr_i32 s2, s0, 16
-; GFX9-NEXT: s_sext_i32_i16 s3, 0
-; GFX9-NEXT: s_cmp_gt_i32 s1, s3
-; GFX9-NEXT: s_cselect_b32 s4, s1, s3
-; GFX9-NEXT: s_cmp_gt_i32 s2, 0
-; GFX9-NEXT: s_cselect_b32 s5, s2, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_lshr_b32 s5, s4, 16
-; GFX9-NEXT: s_sub_i32 s4, 0x7fff7fff, s4
-; GFX9-NEXT: s_sub_i32 s5, 0x7fff, s5
-; GFX9-NEXT: s_cmp_lt_i32 s1, s3
-; GFX9-NEXT: s_cselect_b32 s1, s1, s3
-; GFX9-NEXT: s_cmp_lt_i32 s2, 0
-; GFX9-NEXT: s_cselect_b32 s2, s2, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2
-; GFX9-NEXT: s_lshr_b32 s2, s1, 16
-; GFX9-NEXT: s_sub_i32 s1, 0x80008000, s1
-; GFX9-NEXT: s_sub_i32 s2, 0x8000, s2
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: v_pk_max_i16 v0, s1, v0
-; GFX9-NEXT: v_pk_min_i16 v0, v0, s4
-; GFX9-NEXT: v_pk_add_u16 v0, s0, v0
+; GFX9-NEXT: v_pk_add_i16 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: saddsat_v2i16_sv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sext_i32_i16 s1, s0
-; GFX10-NEXT: s_sext_i32_i16 s2, 0
-; GFX10-NEXT: s_ashr_i32 s3, s0, 16
-; GFX10-NEXT: s_cmp_gt_i32 s1, s2
+; GFX10-NEXT: v_pk_add_i16 v0, s0, v0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s4, s1, s2
-; GFX10-NEXT: s_cmp_gt_i32 s3, 0
-; GFX10-NEXT: s_cselect_b32 s5, s3, 0
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX10-NEXT: s_lshr_b32 s5, s4, 16
-; GFX10-NEXT: s_sub_i32 s4, 0x7fff7fff, s4
-; GFX10-NEXT: s_sub_i32 s5, 0x7fff, s5
-; GFX10-NEXT: s_cmp_lt_i32 s1, s2
-; GFX10-NEXT: s_cselect_b32 s1, s1, s2
-; GFX10-NEXT: s_cmp_lt_i32 s3, 0
-; GFX10-NEXT: s_cselect_b32 s2, s3, 0
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s2
-; GFX10-NEXT: s_lshr_b32 s2, s1, 16
-; GFX10-NEXT: s_sub_i32 s1, 0x80008000, s1
-; GFX10-NEXT: s_sub_i32 s2, 0x8000, s2
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s2
-; GFX10-NEXT: v_pk_max_i16 v0, s1, v0
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s4, s5
-; GFX10-NEXT: v_pk_min_i16 v0, v0, s1
-; GFX10-NEXT: v_pk_add_u16 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
@@ -4926,27 +3324,13 @@ define amdgpu_ps float @saddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
;
; GFX9-LABEL: saddsat_v2i16_vs:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_pk_max_i16 v1, v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fff7fff
-; GFX9-NEXT: v_pk_sub_i16 v1, v2, v1
-; GFX9-NEXT: v_pk_min_i16 v2, v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x80008000
-; GFX9-NEXT: v_pk_sub_i16 v2, v3, v2
-; GFX9-NEXT: v_pk_max_i16 v2, v2, s0
-; GFX9-NEXT: v_pk_min_i16 v1, v2, v1
-; GFX9-NEXT: v_pk_add_u16 v0, v0, v1
+; GFX9-NEXT: v_pk_add_i16 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: saddsat_v2i16_vs:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_min_i16 v1, v0, 0
-; GFX10-NEXT: v_pk_max_i16 v2, v0, 0
+; GFX10-NEXT: v_pk_add_i16 v0, v0, s0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_sub_i16 v1, 0x80008000, v1
-; GFX10-NEXT: v_pk_sub_i16 v2, 0x7fff7fff, v2
-; GFX10-NEXT: v_pk_max_i16 v1, v1, s0
-; GFX10-NEXT: v_pk_min_i16 v1, v1, v2
-; GFX10-NEXT: v_pk_add_u16 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
@@ -5065,43 +3449,17 @@ define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX9-LABEL: v_saddsat_v4i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_min_i16 v6, v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v7, 0x80008000
-; GFX9-NEXT: v_pk_sub_i16 v6, v7, v6
-; GFX9-NEXT: v_pk_max_i16 v4, v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v5, 0x7fff7fff
-; GFX9-NEXT: v_pk_sub_i16 v4, v5, v4
-; GFX9-NEXT: v_pk_max_i16 v2, v6, v2
-; GFX9-NEXT: v_pk_min_i16 v2, v2, v4
-; GFX9-NEXT: v_pk_min_i16 v4, v1, 0
-; GFX9-NEXT: v_pk_add_u16 v0, v0, v2
-; GFX9-NEXT: v_pk_max_i16 v2, v1, 0
-; GFX9-NEXT: v_pk_sub_i16 v4, v7, v4
-; GFX9-NEXT: v_pk_sub_i16 v2, v5, v2
-; GFX9-NEXT: v_pk_max_i16 v3, v4, v3
-; GFX9-NEXT: v_pk_min_i16 v2, v3, v2
-; GFX9-NEXT: v_pk_add_u16 v1, v1, v2
+; GFX9-NEXT: v_pk_add_i16 v0, v0, v2 clamp
+; GFX9-NEXT: v_pk_add_i16 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_saddsat_v4i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_min_i16 v4, v0, 0
-; GFX10-NEXT: v_pk_min_i16 v5, v1, 0
-; GFX10-NEXT: v_pk_max_i16 v6, v0, 0
-; GFX10-NEXT: v_pk_max_i16 v7, v1, 0
+; GFX10-NEXT: v_pk_add_i16 v0, v0, v2 clamp
+; GFX10-NEXT: v_pk_add_i16 v1, v1, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_sub_i16 v4, 0x80008000, v4
-; GFX10-NEXT: v_pk_sub_i16 v5, 0x80008000, v5
-; GFX10-NEXT: v_pk_sub_i16 v6, 0x7fff7fff, v6
-; GFX10-NEXT: v_pk_sub_i16 v7, 0x7fff7fff, v7
-; GFX10-NEXT: v_pk_max_i16 v11, v4, v2
-; GFX10-NEXT: v_pk_max_i16 v10, v5, v3
-; GFX10-NEXT: v_pk_min_i16 v2, v11, v6
-; GFX10-NEXT: v_pk_min_i16 v3, v10, v7
-; GFX10-NEXT: v_pk_add_u16 v0, v0, v2
-; GFX10-NEXT: v_pk_add_u16 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x float>
@@ -5265,193 +3623,21 @@ define amdgpu_ps <2 x i32> @s_saddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inre
;
; GFX9-LABEL: s_saddsat_v4i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sext_i32_i16 s6, s0
-; GFX9-NEXT: s_ashr_i32 s7, s0, 16
-; GFX9-NEXT: s_sext_i32_i16 s8, 0
-; GFX9-NEXT: s_cmp_gt_i32 s6, s8
-; GFX9-NEXT: s_cselect_b32 s9, s6, s8
-; GFX9-NEXT: s_cmp_gt_i32 s7, 0
-; GFX9-NEXT: s_cselect_b32 s10, s7, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s10
-; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff
-; GFX9-NEXT: s_lshr_b32 s11, s9, 16
-; GFX9-NEXT: s_movk_i32 s10, 0x7fff
-; GFX9-NEXT: s_sub_i32 s9, s4, s9
-; GFX9-NEXT: s_sub_i32 s11, s10, s11
-; GFX9-NEXT: s_cmp_lt_i32 s6, s8
-; GFX9-NEXT: s_cselect_b32 s6, s6, s8
-; GFX9-NEXT: s_cmp_lt_i32 s7, 0
-; GFX9-NEXT: s_cselect_b32 s7, s7, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s7
-; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s11
-; GFX9-NEXT: s_mov_b32 s5, 0x80008000
-; GFX9-NEXT: s_lshr_b32 s11, s6, 16
-; GFX9-NEXT: s_mov_b32 s7, 0x8000
-; GFX9-NEXT: s_sub_i32 s6, s5, s6
-; GFX9-NEXT: s_sub_i32 s11, s7, s11
-; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s11
-; GFX9-NEXT: s_sext_i32_i16 s11, s6
-; GFX9-NEXT: s_sext_i32_i16 s12, s2
-; GFX9-NEXT: s_ashr_i32 s6, s6, 16
-; GFX9-NEXT: s_ashr_i32 s2, s2, 16
-; GFX9-NEXT: s_cmp_gt_i32 s11, s12
-; GFX9-NEXT: s_cselect_b32 s11, s11, s12
-; GFX9-NEXT: s_cmp_gt_i32 s6, s2
-; GFX9-NEXT: s_cselect_b32 s2, s6, s2
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s11, s2
-; GFX9-NEXT: s_sext_i32_i16 s6, s2
-; GFX9-NEXT: s_sext_i32_i16 s11, s9
-; GFX9-NEXT: s_ashr_i32 s2, s2, 16
-; GFX9-NEXT: s_ashr_i32 s9, s9, 16
-; GFX9-NEXT: s_cmp_lt_i32 s6, s11
-; GFX9-NEXT: s_cselect_b32 s6, s6, s11
-; GFX9-NEXT: s_cmp_lt_i32 s2, s9
-; GFX9-NEXT: s_cselect_b32 s2, s2, s9
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s6, s2
-; GFX9-NEXT: s_lshr_b32 s6, s0, 16
-; GFX9-NEXT: s_lshr_b32 s9, s2, 16
-; GFX9-NEXT: s_add_i32 s0, s0, s2
-; GFX9-NEXT: s_add_i32 s6, s6, s9
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s6
-; GFX9-NEXT: s_sext_i32_i16 s2, s1
-; GFX9-NEXT: s_ashr_i32 s6, s1, 16
-; GFX9-NEXT: s_cmp_gt_i32 s2, s8
-; GFX9-NEXT: s_cselect_b32 s9, s2, s8
-; GFX9-NEXT: s_cmp_gt_i32 s6, 0
-; GFX9-NEXT: s_cselect_b32 s11, s6, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s11
-; GFX9-NEXT: s_lshr_b32 s11, s9, 16
-; GFX9-NEXT: s_sub_i32 s4, s4, s9
-; GFX9-NEXT: s_sub_i32 s9, s10, s11
-; GFX9-NEXT: s_cmp_lt_i32 s2, s8
-; GFX9-NEXT: s_cselect_b32 s2, s2, s8
-; GFX9-NEXT: s_cmp_lt_i32 s6, 0
-; GFX9-NEXT: s_cselect_b32 s6, s6, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s6
-; GFX9-NEXT: s_lshr_b32 s6, s2, 16
-; GFX9-NEXT: s_sub_i32 s2, s5, s2
-; GFX9-NEXT: s_sub_i32 s5, s7, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s5
-; GFX9-NEXT: s_sext_i32_i16 s5, s2
-; GFX9-NEXT: s_sext_i32_i16 s6, s3
-; GFX9-NEXT: s_ashr_i32 s2, s2, 16
-; GFX9-NEXT: s_ashr_i32 s3, s3, 16
-; GFX9-NEXT: s_cmp_gt_i32 s5, s6
-; GFX9-NEXT: s_cselect_b32 s5, s5, s6
-; GFX9-NEXT: s_cmp_gt_i32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s2, s3
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s5, s2
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s9
-; GFX9-NEXT: s_sext_i32_i16 s3, s2
-; GFX9-NEXT: s_sext_i32_i16 s5, s4
-; GFX9-NEXT: s_ashr_i32 s2, s2, 16
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_cmp_lt_i32 s3, s5
-; GFX9-NEXT: s_cselect_b32 s3, s3, s5
-; GFX9-NEXT: s_cmp_lt_i32 s2, s4
-; GFX9-NEXT: s_cselect_b32 s2, s2, s4
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s3, s2
-; GFX9-NEXT: s_lshr_b32 s3, s1, 16
-; GFX9-NEXT: s_lshr_b32 s4, s2, 16
-; GFX9-NEXT: s_add_i32 s1, s1, s2
-; GFX9-NEXT: s_add_i32 s3, s3, s4
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_pk_add_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_pk_add_i16 v1, s1, v1 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_v4i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sext_i32_i16 s4, s0
-; GFX10-NEXT: s_sext_i32_i16 s5, 0
-; GFX10-NEXT: s_ashr_i32 s6, s0, 16
-; GFX10-NEXT: s_cmp_gt_i32 s4, s5
-; GFX10-NEXT: s_mov_b32 s9, 0x7fff7fff
-; GFX10-NEXT: s_cselect_b32 s7, s4, s5
-; GFX10-NEXT: s_cmp_gt_i32 s6, 0
-; GFX10-NEXT: s_mov_b32 s11, 0x80008000
-; GFX10-NEXT: s_cselect_b32 s8, s6, 0
-; GFX10-NEXT: s_sext_i32_i16 s13, s2
-; GFX10-NEXT: s_pack_ll_b32_b16 s7, s7, s8
-; GFX10-NEXT: s_movk_i32 s8, 0x7fff
-; GFX10-NEXT: s_lshr_b32 s10, s7, 16
-; GFX10-NEXT: s_sub_i32 s7, s9, s7
-; GFX10-NEXT: s_sub_i32 s10, s8, s10
-; GFX10-NEXT: s_cmp_lt_i32 s4, s5
+; GFX10-NEXT: v_pk_add_i16 v0, s0, s2 clamp
+; GFX10-NEXT: v_pk_add_i16 v1, s1, s3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s4, s4, s5
-; GFX10-NEXT: s_cmp_lt_i32 s6, 0
-; GFX10-NEXT: s_cselect_b32 s6, s6, 0
-; GFX10-NEXT: s_ashr_i32 s2, s2, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s6
-; GFX10-NEXT: s_mov_b32 s6, 0x8000
-; GFX10-NEXT: s_lshr_b32 s12, s4, 16
-; GFX10-NEXT: s_sub_i32 s4, s11, s4
-; GFX10-NEXT: s_sub_i32 s12, s6, s12
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s12
-; GFX10-NEXT: s_sext_i32_i16 s12, s4
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_cmp_gt_i32 s12, s13
-; GFX10-NEXT: s_cselect_b32 s12, s12, s13
-; GFX10-NEXT: s_cmp_gt_i32 s4, s2
-; GFX10-NEXT: s_cselect_b32 s2, s4, s2
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s7, s10
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s12, s2
-; GFX10-NEXT: s_sext_i32_i16 s10, s4
-; GFX10-NEXT: s_sext_i32_i16 s7, s2
-; GFX10-NEXT: s_ashr_i32 s2, s2, 16
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_cmp_lt_i32 s7, s10
-; GFX10-NEXT: s_cselect_b32 s7, s7, s10
-; GFX10-NEXT: s_cmp_lt_i32 s2, s4
-; GFX10-NEXT: s_cselect_b32 s2, s2, s4
-; GFX10-NEXT: s_sext_i32_i16 s4, s1
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s7, s2
-; GFX10-NEXT: s_lshr_b32 s7, s0, 16
-; GFX10-NEXT: s_lshr_b32 s10, s2, 16
-; GFX10-NEXT: s_add_i32 s0, s0, s2
-; GFX10-NEXT: s_add_i32 s7, s7, s10
-; GFX10-NEXT: s_ashr_i32 s2, s1, 16
-; GFX10-NEXT: s_cmp_gt_i32 s4, s5
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s7
-; GFX10-NEXT: s_cselect_b32 s10, s4, s5
-; GFX10-NEXT: s_cmp_gt_i32 s2, 0
-; GFX10-NEXT: s_cselect_b32 s12, s2, 0
-; GFX10-NEXT: s_pack_ll_b32_b16 s10, s10, s12
-; GFX10-NEXT: s_lshr_b32 s12, s10, 16
-; GFX10-NEXT: s_sub_i32 s9, s9, s10
-; GFX10-NEXT: s_sub_i32 s8, s8, s12
-; GFX10-NEXT: s_cmp_lt_i32 s4, s5
-; GFX10-NEXT: s_cselect_b32 s4, s4, s5
-; GFX10-NEXT: s_cmp_lt_i32 s2, 0
-; GFX10-NEXT: s_sext_i32_i16 s5, s3
-; GFX10-NEXT: s_cselect_b32 s2, s2, 0
-; GFX10-NEXT: s_ashr_i32 s3, s3, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s4, s2
-; GFX10-NEXT: s_lshr_b32 s4, s2, 16
-; GFX10-NEXT: s_sub_i32 s2, s11, s2
-; GFX10-NEXT: s_sub_i32 s4, s6, s4
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4
-; GFX10-NEXT: s_sext_i32_i16 s4, s2
-; GFX10-NEXT: s_ashr_i32 s2, s2, 16
-; GFX10-NEXT: s_cmp_gt_i32 s4, s5
-; GFX10-NEXT: s_cselect_b32 s4, s4, s5
-; GFX10-NEXT: s_cmp_gt_i32 s2, s3
-; GFX10-NEXT: s_pack_ll_b32_b16 s5, s9, s8
-; GFX10-NEXT: s_cselect_b32 s2, s2, s3
-; GFX10-NEXT: s_sext_i32_i16 s3, s5
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s4, s2
-; GFX10-NEXT: s_ashr_i32 s4, s5, 16
-; GFX10-NEXT: s_sext_i32_i16 s5, s2
-; GFX10-NEXT: s_ashr_i32 s2, s2, 16
-; GFX10-NEXT: s_cmp_lt_i32 s5, s3
-; GFX10-NEXT: s_cselect_b32 s3, s5, s3
-; GFX10-NEXT: s_cmp_lt_i32 s2, s4
-; GFX10-NEXT: s_cselect_b32 s2, s2, s4
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s3, s2
-; GFX10-NEXT: s_lshr_b32 s3, s1, 16
-; GFX10-NEXT: s_lshr_b32 s4, s2, 16
-; GFX10-NEXT: s_add_i32 s1, s1, s2
-; GFX10-NEXT: s_add_i32 s3, s3, s4
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x i32>
@@ -5612,57 +3798,19 @@ define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX9-LABEL: v_saddsat_v6i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_min_i16 v8, v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v9, 0x80008000
-; GFX9-NEXT: v_pk_sub_i16 v8, v9, v8
-; GFX9-NEXT: v_pk_max_i16 v6, v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v7, 0x7fff7fff
-; GFX9-NEXT: v_pk_sub_i16 v6, v7, v6
-; GFX9-NEXT: v_pk_max_i16 v3, v8, v3
-; GFX9-NEXT: v_pk_min_i16 v3, v3, v6
-; GFX9-NEXT: v_pk_min_i16 v6, v1, 0
-; GFX9-NEXT: v_pk_add_u16 v0, v0, v3
-; GFX9-NEXT: v_pk_max_i16 v3, v1, 0
-; GFX9-NEXT: v_pk_sub_i16 v6, v9, v6
-; GFX9-NEXT: v_pk_sub_i16 v3, v7, v3
-; GFX9-NEXT: v_pk_max_i16 v4, v6, v4
-; GFX9-NEXT: v_pk_min_i16 v3, v4, v3
-; GFX9-NEXT: v_pk_min_i16 v4, v2, 0
-; GFX9-NEXT: v_pk_sub_i16 v4, v9, v4
-; GFX9-NEXT: v_pk_add_u16 v1, v1, v3
-; GFX9-NEXT: v_pk_max_i16 v3, v2, 0
-; GFX9-NEXT: v_pk_sub_i16 v3, v7, v3
-; GFX9-NEXT: v_pk_max_i16 v4, v4, v5
-; GFX9-NEXT: v_pk_min_i16 v3, v4, v3
-; GFX9-NEXT: v_pk_add_u16 v2, v2, v3
+; GFX9-NEXT: v_pk_add_i16 v0, v0, v3 clamp
+; GFX9-NEXT: v_pk_add_i16 v1, v1, v4 clamp
+; GFX9-NEXT: v_pk_add_i16 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_saddsat_v6i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_min_i16 v7, v0, 0
-; GFX10-NEXT: v_pk_min_i16 v8, v1, 0
-; GFX10-NEXT: v_pk_min_i16 v9, v2, 0
-; GFX10-NEXT: v_pk_max_i16 v6, v0, 0
-; GFX10-NEXT: v_pk_max_i16 v10, v1, 0
-; GFX10-NEXT: v_pk_sub_i16 v14, 0x80008000, v7
-; GFX10-NEXT: v_pk_sub_i16 v15, 0x80008000, v8
-; GFX10-NEXT: v_pk_max_i16 v11, v2, 0
-; GFX10-NEXT: v_pk_sub_i16 v19, 0x80008000, v9
-; GFX10-NEXT: v_pk_sub_i16 v6, 0x7fff7fff, v6
-; GFX10-NEXT: v_pk_max_i16 v3, v14, v3
-; GFX10-NEXT: v_pk_sub_i16 v7, 0x7fff7fff, v10
-; GFX10-NEXT: v_pk_max_i16 v4, v15, v4
-; GFX10-NEXT: v_pk_sub_i16 v8, 0x7fff7fff, v11
-; GFX10-NEXT: v_pk_max_i16 v5, v19, v5
-; GFX10-NEXT: v_pk_min_i16 v3, v3, v6
+; GFX10-NEXT: v_pk_add_i16 v0, v0, v3 clamp
+; GFX10-NEXT: v_pk_add_i16 v1, v1, v4 clamp
+; GFX10-NEXT: v_pk_add_i16 v2, v2, v5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_min_i16 v4, v4, v7
-; GFX10-NEXT: v_pk_min_i16 v5, v5, v8
-; GFX10-NEXT: v_pk_add_u16 v0, v0, v3
-; GFX10-NEXT: v_pk_add_u16 v1, v1, v4
-; GFX10-NEXT: v_pk_add_u16 v2, v2, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x i16> @llvm.sadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x float>
@@ -5896,279 +4044,26 @@ define amdgpu_ps <3 x i32> @s_saddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inre
;
; GFX9-LABEL: s_saddsat_v6i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sext_i32_i16 s8, s0
-; GFX9-NEXT: s_ashr_i32 s9, s0, 16
-; GFX9-NEXT: s_sext_i32_i16 s10, 0
-; GFX9-NEXT: s_cmp_gt_i32 s8, s10
-; GFX9-NEXT: s_cselect_b32 s11, s8, s10
-; GFX9-NEXT: s_cmp_gt_i32 s9, 0
-; GFX9-NEXT: s_cselect_b32 s12, s9, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s12
-; GFX9-NEXT: s_mov_b32 s6, 0x7fff7fff
-; GFX9-NEXT: s_lshr_b32 s13, s11, 16
-; GFX9-NEXT: s_movk_i32 s12, 0x7fff
-; GFX9-NEXT: s_sub_i32 s11, s6, s11
-; GFX9-NEXT: s_sub_i32 s13, s12, s13
-; GFX9-NEXT: s_cmp_lt_i32 s8, s10
-; GFX9-NEXT: s_cselect_b32 s8, s8, s10
-; GFX9-NEXT: s_cmp_lt_i32 s9, 0
-; GFX9-NEXT: s_cselect_b32 s9, s9, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s9
-; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s13
-; GFX9-NEXT: s_mov_b32 s7, 0x80008000
-; GFX9-NEXT: s_lshr_b32 s13, s8, 16
-; GFX9-NEXT: s_mov_b32 s9, 0x8000
-; GFX9-NEXT: s_sub_i32 s8, s7, s8
-; GFX9-NEXT: s_sub_i32 s13, s9, s13
-; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s13
-; GFX9-NEXT: s_sext_i32_i16 s13, s8
-; GFX9-NEXT: s_sext_i32_i16 s14, s3
-; GFX9-NEXT: s_ashr_i32 s8, s8, 16
-; GFX9-NEXT: s_ashr_i32 s3, s3, 16
-; GFX9-NEXT: s_cmp_gt_i32 s13, s14
-; GFX9-NEXT: s_cselect_b32 s13, s13, s14
-; GFX9-NEXT: s_cmp_gt_i32 s8, s3
-; GFX9-NEXT: s_cselect_b32 s3, s8, s3
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s13, s3
-; GFX9-NEXT: s_sext_i32_i16 s8, s3
-; GFX9-NEXT: s_sext_i32_i16 s13, s11
-; GFX9-NEXT: s_ashr_i32 s3, s3, 16
-; GFX9-NEXT: s_ashr_i32 s11, s11, 16
-; GFX9-NEXT: s_cmp_lt_i32 s8, s13
-; GFX9-NEXT: s_cselect_b32 s8, s8, s13
-; GFX9-NEXT: s_cmp_lt_i32 s3, s11
-; GFX9-NEXT: s_cselect_b32 s3, s3, s11
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s8, s3
-; GFX9-NEXT: s_lshr_b32 s8, s0, 16
-; GFX9-NEXT: s_lshr_b32 s11, s3, 16
-; GFX9-NEXT: s_add_i32 s0, s0, s3
-; GFX9-NEXT: s_add_i32 s8, s8, s11
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s8
-; GFX9-NEXT: s_sext_i32_i16 s3, s1
-; GFX9-NEXT: s_ashr_i32 s8, s1, 16
-; GFX9-NEXT: s_cmp_gt_i32 s3, s10
-; GFX9-NEXT: s_cselect_b32 s11, s3, s10
-; GFX9-NEXT: s_cmp_gt_i32 s8, 0
-; GFX9-NEXT: s_cselect_b32 s13, s8, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s13
-; GFX9-NEXT: s_lshr_b32 s13, s11, 16
-; GFX9-NEXT: s_sub_i32 s11, s6, s11
-; GFX9-NEXT: s_sub_i32 s13, s12, s13
-; GFX9-NEXT: s_cmp_lt_i32 s3, s10
-; GFX9-NEXT: s_cselect_b32 s3, s3, s10
-; GFX9-NEXT: s_cmp_lt_i32 s8, 0
-; GFX9-NEXT: s_cselect_b32 s8, s8, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s8
-; GFX9-NEXT: s_lshr_b32 s8, s3, 16
-; GFX9-NEXT: s_sub_i32 s3, s7, s3
-; GFX9-NEXT: s_sub_i32 s8, s9, s8
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s8
-; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s13
-; GFX9-NEXT: s_sext_i32_i16 s8, s3
-; GFX9-NEXT: s_sext_i32_i16 s13, s4
-; GFX9-NEXT: s_ashr_i32 s3, s3, 16
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_cmp_gt_i32 s8, s13
-; GFX9-NEXT: s_cselect_b32 s8, s8, s13
-; GFX9-NEXT: s_cmp_gt_i32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s3, s3, s4
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s8, s3
-; GFX9-NEXT: s_sext_i32_i16 s4, s3
-; GFX9-NEXT: s_sext_i32_i16 s8, s11
-; GFX9-NEXT: s_ashr_i32 s3, s3, 16
-; GFX9-NEXT: s_ashr_i32 s11, s11, 16
-; GFX9-NEXT: s_cmp_lt_i32 s4, s8
-; GFX9-NEXT: s_cselect_b32 s4, s4, s8
-; GFX9-NEXT: s_cmp_lt_i32 s3, s11
-; GFX9-NEXT: s_cselect_b32 s3, s3, s11
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s3
-; GFX9-NEXT: s_lshr_b32 s4, s1, 16
-; GFX9-NEXT: s_lshr_b32 s8, s3, 16
-; GFX9-NEXT: s_add_i32 s1, s1, s3
-; GFX9-NEXT: s_add_i32 s4, s4, s8
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4
-; GFX9-NEXT: s_sext_i32_i16 s3, s2
-; GFX9-NEXT: s_ashr_i32 s4, s2, 16
-; GFX9-NEXT: s_cmp_gt_i32 s3, s10
-; GFX9-NEXT: s_cselect_b32 s8, s3, s10
-; GFX9-NEXT: s_cmp_gt_i32 s4, 0
-; GFX9-NEXT: s_cselect_b32 s11, s4, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s11
-; GFX9-NEXT: s_lshr_b32 s11, s8, 16
-; GFX9-NEXT: s_sub_i32 s6, s6, s8
-; GFX9-NEXT: s_sub_i32 s8, s12, s11
-; GFX9-NEXT: s_cmp_lt_i32 s3, s10
-; GFX9-NEXT: s_cselect_b32 s3, s3, s10
-; GFX9-NEXT: s_cmp_lt_i32 s4, 0
-; GFX9-NEXT: s_cselect_b32 s4, s4, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4
-; GFX9-NEXT: s_lshr_b32 s4, s3, 16
-; GFX9-NEXT: s_sub_i32 s3, s7, s3
-; GFX9-NEXT: s_sub_i32 s4, s9, s4
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4
-; GFX9-NEXT: s_sext_i32_i16 s4, s3
-; GFX9-NEXT: s_sext_i32_i16 s7, s5
-; GFX9-NEXT: s_ashr_i32 s3, s3, 16
-; GFX9-NEXT: s_ashr_i32 s5, s5, 16
-; GFX9-NEXT: s_cmp_gt_i32 s4, s7
-; GFX9-NEXT: s_cselect_b32 s4, s4, s7
-; GFX9-NEXT: s_cmp_gt_i32 s3, s5
-; GFX9-NEXT: s_cselect_b32 s3, s3, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s3
-; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s8
-; GFX9-NEXT: s_sext_i32_i16 s4, s3
-; GFX9-NEXT: s_sext_i32_i16 s5, s6
-; GFX9-NEXT: s_ashr_i32 s3, s3, 16
-; GFX9-NEXT: s_ashr_i32 s6, s6, 16
-; GFX9-NEXT: s_cmp_lt_i32 s4, s5
-; GFX9-NEXT: s_cselect_b32 s4, s4, s5
-; GFX9-NEXT: s_cmp_lt_i32 s3, s6
-; GFX9-NEXT: s_cselect_b32 s3, s3, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s3
-; GFX9-NEXT: s_lshr_b32 s4, s2, 16
-; GFX9-NEXT: s_lshr_b32 s5, s3, 16
-; GFX9-NEXT: s_add_i32 s2, s2, s3
-; GFX9-NEXT: s_add_i32 s4, s4, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-NEXT: v_pk_add_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_pk_add_i16 v1, s1, v1 clamp
+; GFX9-NEXT: v_pk_add_i16 v2, s2, v2 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_v6i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sext_i32_i16 s6, s0
-; GFX10-NEXT: s_sext_i32_i16 s7, 0
-; GFX10-NEXT: s_ashr_i32 s8, s0, 16
-; GFX10-NEXT: s_cmp_gt_i32 s6, s7
-; GFX10-NEXT: s_mov_b32 s11, 0x7fff7fff
-; GFX10-NEXT: s_cselect_b32 s9, s6, s7
-; GFX10-NEXT: s_cmp_gt_i32 s8, 0
-; GFX10-NEXT: s_mov_b32 s13, 0x80008000
-; GFX10-NEXT: s_cselect_b32 s10, s8, 0
-; GFX10-NEXT: s_sext_i32_i16 s15, s3
-; GFX10-NEXT: s_pack_ll_b32_b16 s9, s9, s10
-; GFX10-NEXT: s_movk_i32 s10, 0x7fff
-; GFX10-NEXT: s_lshr_b32 s12, s9, 16
-; GFX10-NEXT: s_sub_i32 s9, s11, s9
-; GFX10-NEXT: s_sub_i32 s12, s10, s12
-; GFX10-NEXT: s_cmp_lt_i32 s6, s7
+; GFX10-NEXT: v_pk_add_i16 v0, s0, s3 clamp
+; GFX10-NEXT: v_pk_add_i16 v1, s1, s4 clamp
+; GFX10-NEXT: v_pk_add_i16 v2, s2, s5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s6, s6, s7
-; GFX10-NEXT: s_cmp_lt_i32 s8, 0
-; GFX10-NEXT: s_cselect_b32 s8, s8, 0
-; GFX10-NEXT: s_ashr_i32 s3, s3, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s8
-; GFX10-NEXT: s_mov_b32 s8, 0x8000
-; GFX10-NEXT: s_lshr_b32 s14, s6, 16
-; GFX10-NEXT: s_sub_i32 s6, s13, s6
-; GFX10-NEXT: s_sub_i32 s14, s8, s14
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s14
-; GFX10-NEXT: s_sext_i32_i16 s14, s6
-; GFX10-NEXT: s_ashr_i32 s6, s6, 16
-; GFX10-NEXT: s_cmp_gt_i32 s14, s15
-; GFX10-NEXT: s_cselect_b32 s14, s14, s15
-; GFX10-NEXT: s_cmp_gt_i32 s6, s3
-; GFX10-NEXT: s_sext_i32_i16 s15, s4
-; GFX10-NEXT: s_cselect_b32 s3, s6, s3
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s9, s12
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s14, s3
-; GFX10-NEXT: s_sext_i32_i16 s12, s6
-; GFX10-NEXT: s_sext_i32_i16 s9, s3
-; GFX10-NEXT: s_ashr_i32 s3, s3, 16
-; GFX10-NEXT: s_ashr_i32 s6, s6, 16
-; GFX10-NEXT: s_cmp_lt_i32 s9, s12
-; GFX10-NEXT: s_cselect_b32 s9, s9, s12
-; GFX10-NEXT: s_cmp_lt_i32 s3, s6
-; GFX10-NEXT: s_cselect_b32 s3, s3, s6
-; GFX10-NEXT: s_lshr_b32 s6, s0, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s9, s3
-; GFX10-NEXT: s_lshr_b32 s9, s3, 16
-; GFX10-NEXT: s_add_i32 s0, s0, s3
-; GFX10-NEXT: s_sext_i32_i16 s3, s1
-; GFX10-NEXT: s_add_i32 s6, s6, s9
-; GFX10-NEXT: s_ashr_i32 s9, s1, 16
-; GFX10-NEXT: s_cmp_gt_i32 s3, s7
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s6
-; GFX10-NEXT: s_cselect_b32 s12, s3, s7
-; GFX10-NEXT: s_cmp_gt_i32 s9, 0
-; GFX10-NEXT: s_cselect_b32 s14, s9, 0
-; GFX10-NEXT: s_pack_ll_b32_b16 s12, s12, s14
-; GFX10-NEXT: s_lshr_b32 s14, s12, 16
-; GFX10-NEXT: s_sub_i32 s12, s11, s12
-; GFX10-NEXT: s_sub_i32 s14, s10, s14
-; GFX10-NEXT: s_cmp_lt_i32 s3, s7
-; GFX10-NEXT: s_pack_ll_b32_b16 s12, s12, s14
-; GFX10-NEXT: s_cselect_b32 s3, s3, s7
-; GFX10-NEXT: s_cmp_lt_i32 s9, 0
-; GFX10-NEXT: s_cselect_b32 s9, s9, 0
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s9
-; GFX10-NEXT: s_lshr_b32 s9, s3, 16
-; GFX10-NEXT: s_sub_i32 s3, s13, s3
-; GFX10-NEXT: s_sub_i32 s9, s8, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s9
-; GFX10-NEXT: s_sext_i32_i16 s9, s3
-; GFX10-NEXT: s_ashr_i32 s3, s3, 16
-; GFX10-NEXT: s_cmp_gt_i32 s9, s15
-; GFX10-NEXT: s_cselect_b32 s9, s9, s15
-; GFX10-NEXT: s_cmp_gt_i32 s3, s4
-; GFX10-NEXT: s_cselect_b32 s3, s3, s4
-; GFX10-NEXT: s_sext_i32_i16 s4, s12
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s9, s3
-; GFX10-NEXT: s_ashr_i32 s9, s12, 16
-; GFX10-NEXT: s_sext_i32_i16 s12, s3
-; GFX10-NEXT: s_ashr_i32 s3, s3, 16
-; GFX10-NEXT: s_cmp_lt_i32 s12, s4
-; GFX10-NEXT: s_cselect_b32 s4, s12, s4
-; GFX10-NEXT: s_cmp_lt_i32 s3, s9
-; GFX10-NEXT: s_sext_i32_i16 s12, s2
-; GFX10-NEXT: s_cselect_b32 s3, s3, s9
-; GFX10-NEXT: s_lshr_b32 s9, s1, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s4, s3
-; GFX10-NEXT: s_ashr_i32 s4, s2, 16
-; GFX10-NEXT: s_lshr_b32 s14, s3, 16
-; GFX10-NEXT: s_add_i32 s1, s1, s3
-; GFX10-NEXT: s_add_i32 s9, s9, s14
-; GFX10-NEXT: s_cmp_gt_i32 s12, s7
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s9
-; GFX10-NEXT: s_cselect_b32 s3, s12, s7
-; GFX10-NEXT: s_cmp_gt_i32 s4, 0
-; GFX10-NEXT: s_cselect_b32 s14, s4, 0
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s14
-; GFX10-NEXT: s_lshr_b32 s14, s3, 16
-; GFX10-NEXT: s_sub_i32 s3, s11, s3
-; GFX10-NEXT: s_sub_i32 s10, s10, s14
-; GFX10-NEXT: s_cmp_lt_i32 s12, s7
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s10
-; GFX10-NEXT: s_cselect_b32 s7, s12, s7
-; GFX10-NEXT: s_cmp_lt_i32 s4, 0
-; GFX10-NEXT: s_cselect_b32 s4, s4, 0
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s7, s4
-; GFX10-NEXT: s_lshr_b32 s7, s4, 16
-; GFX10-NEXT: s_sub_i32 s4, s13, s4
-; GFX10-NEXT: s_sub_i32 s7, s8, s7
-; GFX10-NEXT: s_sext_i32_i16 s8, s5
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s7
-; GFX10-NEXT: s_ashr_i32 s5, s5, 16
-; GFX10-NEXT: s_sext_i32_i16 s7, s4
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_cmp_gt_i32 s7, s8
-; GFX10-NEXT: s_cselect_b32 s7, s7, s8
-; GFX10-NEXT: s_cmp_gt_i32 s4, s5
-; GFX10-NEXT: s_cselect_b32 s4, s4, s5
-; GFX10-NEXT: s_sext_i32_i16 s5, s3
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s7, s4
-; GFX10-NEXT: s_ashr_i32 s3, s3, 16
-; GFX10-NEXT: s_sext_i32_i16 s7, s4
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_cmp_lt_i32 s7, s5
-; GFX10-NEXT: s_cselect_b32 s5, s7, s5
-; GFX10-NEXT: s_cmp_lt_i32 s4, s3
-; GFX10-NEXT: s_cselect_b32 s3, s4, s3
-; GFX10-NEXT: s_lshr_b32 s4, s2, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s5, s3
-; GFX10-NEXT: s_lshr_b32 s5, s3, 16
-; GFX10-NEXT: s_add_i32 s2, s2, s3
-; GFX10-NEXT: s_add_i32 s4, s4, s5
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: ; return to shader part epilog
%result = call <6 x i16> @llvm.sadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x i32>
@@ -6358,71 +4253,21 @@ define <4 x float> @v_saddsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX9-LABEL: v_saddsat_v8i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_min_i16 v10, v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v11, 0x80008000
-; GFX9-NEXT: v_pk_sub_i16 v10, v11, v10
-; GFX9-NEXT: v_pk_max_i16 v8, v0, 0
-; GFX9-NEXT: v_mov_b32_e32 v9, 0x7fff7fff
-; GFX9-NEXT: v_pk_sub_i16 v8, v9, v8
-; GFX9-NEXT: v_pk_max_i16 v4, v10, v4
-; GFX9-NEXT: v_pk_min_i16 v4, v4, v8
-; GFX9-NEXT: v_pk_min_i16 v8, v1, 0
-; GFX9-NEXT: v_pk_add_u16 v0, v0, v4
-; GFX9-NEXT: v_pk_max_i16 v4, v1, 0
-; GFX9-NEXT: v_pk_sub_i16 v8, v11, v8
-; GFX9-NEXT: v_pk_sub_i16 v4, v9, v4
-; GFX9-NEXT: v_pk_max_i16 v5, v8, v5
-; GFX9-NEXT: v_pk_min_i16 v4, v5, v4
-; GFX9-NEXT: v_pk_min_i16 v5, v2, 0
-; GFX9-NEXT: v_pk_sub_i16 v5, v11, v5
-; GFX9-NEXT: v_pk_add_u16 v1, v1, v4
-; GFX9-NEXT: v_pk_max_i16 v4, v2, 0
-; GFX9-NEXT: v_pk_sub_i16 v4, v9, v4
-; GFX9-NEXT: v_pk_max_i16 v5, v5, v6
-; GFX9-NEXT: v_pk_min_i16 v4, v5, v4
-; GFX9-NEXT: v_pk_min_i16 v5, v3, 0
-; GFX9-NEXT: v_pk_sub_i16 v5, v11, v5
-; GFX9-NEXT: v_pk_add_u16 v2, v2, v4
-; GFX9-NEXT: v_pk_max_i16 v4, v3, 0
-; GFX9-NEXT: v_pk_sub_i16 v4, v9, v4
-; GFX9-NEXT: v_pk_max_i16 v5, v5, v7
-; GFX9-NEXT: v_pk_min_i16 v4, v5, v4
-; GFX9-NEXT: v_pk_add_u16 v3, v3, v4
+; GFX9-NEXT: v_pk_add_i16 v0, v0, v4 clamp
+; GFX9-NEXT: v_pk_add_i16 v1, v1, v5 clamp
+; GFX9-NEXT: v_pk_add_i16 v2, v2, v6 clamp
+; GFX9-NEXT: v_pk_add_i16 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_saddsat_v8i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_min_i16 v8, v0, 0
-; GFX10-NEXT: v_pk_min_i16 v11, v1, 0
-; GFX10-NEXT: v_pk_min_i16 v12, v3, 0
-; GFX10-NEXT: v_pk_max_i16 v9, v0, 0
-; GFX10-NEXT: v_pk_max_i16 v10, v1, 0
-; GFX10-NEXT: v_pk_sub_i16 v15, 0x80008000, v8
-; GFX10-NEXT: v_pk_min_i16 v8, v2, 0
-; GFX10-NEXT: v_pk_sub_i16 v11, 0x80008000, v11
-; GFX10-NEXT: v_pk_sub_i16 v12, 0x80008000, v12
-; GFX10-NEXT: v_pk_max_i16 v13, v2, 0
-; GFX10-NEXT: v_pk_max_i16 v14, v3, 0
-; GFX10-NEXT: v_pk_sub_i16 v8, 0x80008000, v8
-; GFX10-NEXT: v_pk_max_i16 v5, v11, v5
-; GFX10-NEXT: v_pk_sub_i16 v10, 0x7fff7fff, v10
-; GFX10-NEXT: v_pk_sub_i16 v9, 0x7fff7fff, v9
-; GFX10-NEXT: v_pk_max_i16 v4, v15, v4
-; GFX10-NEXT: v_pk_max_i16 v6, v8, v6
-; GFX10-NEXT: v_pk_sub_i16 v11, 0x7fff7fff, v13
-; GFX10-NEXT: v_pk_sub_i16 v8, 0x7fff7fff, v14
-; GFX10-NEXT: v_pk_max_i16 v7, v12, v7
-; GFX10-NEXT: v_pk_min_i16 v15, v4, v9
-; GFX10-NEXT: v_pk_min_i16 v19, v5, v10
-; GFX10-NEXT: v_pk_min_i16 v11, v6, v11
+; GFX10-NEXT: v_pk_add_i16 v0, v0, v4 clamp
+; GFX10-NEXT: v_pk_add_i16 v1, v1, v5 clamp
+; GFX10-NEXT: v_pk_add_i16 v2, v2, v6 clamp
+; GFX10-NEXT: v_pk_add_i16 v3, v3, v7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_min_i16 v6, v7, v8
-; GFX10-NEXT: v_pk_add_u16 v0, v0, v15
-; GFX10-NEXT: v_pk_add_u16 v1, v1, v19
-; GFX10-NEXT: v_pk_add_u16 v2, v2, v11
-; GFX10-NEXT: v_pk_add_u16 v3, v3, v6
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x float>
@@ -6726,365 +4571,31 @@ define amdgpu_ps <4 x i32> @s_saddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inre
;
; GFX9-LABEL: s_saddsat_v8i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sext_i32_i16 s10, s0
-; GFX9-NEXT: s_ashr_i32 s11, s0, 16
-; GFX9-NEXT: s_sext_i32_i16 s12, 0
-; GFX9-NEXT: s_cmp_gt_i32 s10, s12
-; GFX9-NEXT: s_cselect_b32 s13, s10, s12
-; GFX9-NEXT: s_cmp_gt_i32 s11, 0
-; GFX9-NEXT: s_cselect_b32 s14, s11, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s14
-; GFX9-NEXT: s_mov_b32 s8, 0x7fff7fff
-; GFX9-NEXT: s_lshr_b32 s15, s13, 16
-; GFX9-NEXT: s_movk_i32 s14, 0x7fff
-; GFX9-NEXT: s_sub_i32 s13, s8, s13
-; GFX9-NEXT: s_sub_i32 s15, s14, s15
-; GFX9-NEXT: s_cmp_lt_i32 s10, s12
-; GFX9-NEXT: s_cselect_b32 s10, s10, s12
-; GFX9-NEXT: s_cmp_lt_i32 s11, 0
-; GFX9-NEXT: s_cselect_b32 s11, s11, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s11
-; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s15
-; GFX9-NEXT: s_mov_b32 s9, 0x80008000
-; GFX9-NEXT: s_lshr_b32 s15, s10, 16
-; GFX9-NEXT: s_mov_b32 s11, 0x8000
-; GFX9-NEXT: s_sub_i32 s10, s9, s10
-; GFX9-NEXT: s_sub_i32 s15, s11, s15
-; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s15
-; GFX9-NEXT: s_sext_i32_i16 s15, s10
-; GFX9-NEXT: s_sext_i32_i16 s16, s4
-; GFX9-NEXT: s_ashr_i32 s10, s10, 16
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_cmp_gt_i32 s15, s16
-; GFX9-NEXT: s_cselect_b32 s15, s15, s16
-; GFX9-NEXT: s_cmp_gt_i32 s10, s4
-; GFX9-NEXT: s_cselect_b32 s4, s10, s4
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s15, s4
-; GFX9-NEXT: s_sext_i32_i16 s10, s4
-; GFX9-NEXT: s_sext_i32_i16 s15, s13
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_ashr_i32 s13, s13, 16
-; GFX9-NEXT: s_cmp_lt_i32 s10, s15
-; GFX9-NEXT: s_cselect_b32 s10, s10, s15
-; GFX9-NEXT: s_cmp_lt_i32 s4, s13
-; GFX9-NEXT: s_cselect_b32 s4, s4, s13
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s10, s4
-; GFX9-NEXT: s_lshr_b32 s10, s0, 16
-; GFX9-NEXT: s_lshr_b32 s13, s4, 16
-; GFX9-NEXT: s_add_i32 s0, s0, s4
-; GFX9-NEXT: s_add_i32 s10, s10, s13
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s10
-; GFX9-NEXT: s_sext_i32_i16 s4, s1
-; GFX9-NEXT: s_ashr_i32 s10, s1, 16
-; GFX9-NEXT: s_cmp_gt_i32 s4, s12
-; GFX9-NEXT: s_cselect_b32 s13, s4, s12
-; GFX9-NEXT: s_cmp_gt_i32 s10, 0
-; GFX9-NEXT: s_cselect_b32 s15, s10, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s15
-; GFX9-NEXT: s_lshr_b32 s15, s13, 16
-; GFX9-NEXT: s_sub_i32 s13, s8, s13
-; GFX9-NEXT: s_sub_i32 s15, s14, s15
-; GFX9-NEXT: s_cmp_lt_i32 s4, s12
-; GFX9-NEXT: s_cselect_b32 s4, s4, s12
-; GFX9-NEXT: s_cmp_lt_i32 s10, 0
-; GFX9-NEXT: s_cselect_b32 s10, s10, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s10
-; GFX9-NEXT: s_lshr_b32 s10, s4, 16
-; GFX9-NEXT: s_sub_i32 s4, s9, s4
-; GFX9-NEXT: s_sub_i32 s10, s11, s10
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s10
-; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s15
-; GFX9-NEXT: s_sext_i32_i16 s10, s4
-; GFX9-NEXT: s_sext_i32_i16 s15, s5
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_ashr_i32 s5, s5, 16
-; GFX9-NEXT: s_cmp_gt_i32 s10, s15
-; GFX9-NEXT: s_cselect_b32 s10, s10, s15
-; GFX9-NEXT: s_cmp_gt_i32 s4, s5
-; GFX9-NEXT: s_cselect_b32 s4, s4, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s10, s4
-; GFX9-NEXT: s_sext_i32_i16 s5, s4
-; GFX9-NEXT: s_sext_i32_i16 s10, s13
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_ashr_i32 s13, s13, 16
-; GFX9-NEXT: s_cmp_lt_i32 s5, s10
-; GFX9-NEXT: s_cselect_b32 s5, s5, s10
-; GFX9-NEXT: s_cmp_lt_i32 s4, s13
-; GFX9-NEXT: s_cselect_b32 s4, s4, s13
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s4
-; GFX9-NEXT: s_lshr_b32 s5, s1, 16
-; GFX9-NEXT: s_lshr_b32 s10, s4, 16
-; GFX9-NEXT: s_add_i32 s1, s1, s4
-; GFX9-NEXT: s_add_i32 s5, s5, s10
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s5
-; GFX9-NEXT: s_sext_i32_i16 s4, s2
-; GFX9-NEXT: s_ashr_i32 s5, s2, 16
-; GFX9-NEXT: s_cmp_gt_i32 s4, s12
-; GFX9-NEXT: s_cselect_b32 s10, s4, s12
-; GFX9-NEXT: s_cmp_gt_i32 s5, 0
-; GFX9-NEXT: s_cselect_b32 s13, s5, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s13
-; GFX9-NEXT: s_lshr_b32 s13, s10, 16
-; GFX9-NEXT: s_sub_i32 s10, s8, s10
-; GFX9-NEXT: s_sub_i32 s13, s14, s13
-; GFX9-NEXT: s_cmp_lt_i32 s4, s12
-; GFX9-NEXT: s_cselect_b32 s4, s4, s12
-; GFX9-NEXT: s_cmp_lt_i32 s5, 0
-; GFX9-NEXT: s_cselect_b32 s5, s5, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_lshr_b32 s5, s4, 16
-; GFX9-NEXT: s_sub_i32 s4, s9, s4
-; GFX9-NEXT: s_sub_i32 s5, s11, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s13
-; GFX9-NEXT: s_sext_i32_i16 s5, s4
-; GFX9-NEXT: s_sext_i32_i16 s13, s6
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_ashr_i32 s6, s6, 16
-; GFX9-NEXT: s_cmp_gt_i32 s5, s13
-; GFX9-NEXT: s_cselect_b32 s5, s5, s13
-; GFX9-NEXT: s_cmp_gt_i32 s4, s6
-; GFX9-NEXT: s_cselect_b32 s4, s4, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s4
-; GFX9-NEXT: s_sext_i32_i16 s5, s4
-; GFX9-NEXT: s_sext_i32_i16 s6, s10
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_ashr_i32 s10, s10, 16
-; GFX9-NEXT: s_cmp_lt_i32 s5, s6
-; GFX9-NEXT: s_cselect_b32 s5, s5, s6
-; GFX9-NEXT: s_cmp_lt_i32 s4, s10
-; GFX9-NEXT: s_cselect_b32 s4, s4, s10
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s4
-; GFX9-NEXT: s_lshr_b32 s5, s2, 16
-; GFX9-NEXT: s_lshr_b32 s6, s4, 16
-; GFX9-NEXT: s_add_i32 s2, s2, s4
-; GFX9-NEXT: s_add_i32 s5, s5, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s5
-; GFX9-NEXT: s_sext_i32_i16 s4, s3
-; GFX9-NEXT: s_ashr_i32 s5, s3, 16
-; GFX9-NEXT: s_cmp_gt_i32 s4, s12
-; GFX9-NEXT: s_cselect_b32 s6, s4, s12
-; GFX9-NEXT: s_cmp_gt_i32 s5, 0
-; GFX9-NEXT: s_cselect_b32 s10, s5, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s10
-; GFX9-NEXT: s_lshr_b32 s10, s6, 16
-; GFX9-NEXT: s_sub_i32 s6, s8, s6
-; GFX9-NEXT: s_sub_i32 s8, s14, s10
-; GFX9-NEXT: s_cmp_lt_i32 s4, s12
-; GFX9-NEXT: s_cselect_b32 s4, s4, s12
-; GFX9-NEXT: s_cmp_lt_i32 s5, 0
-; GFX9-NEXT: s_cselect_b32 s5, s5, 0
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_lshr_b32 s5, s4, 16
-; GFX9-NEXT: s_sub_i32 s4, s9, s4
-; GFX9-NEXT: s_sub_i32 s5, s11, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s8
-; GFX9-NEXT: s_sext_i32_i16 s5, s4
-; GFX9-NEXT: s_sext_i32_i16 s8, s7
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_ashr_i32 s7, s7, 16
-; GFX9-NEXT: s_cmp_gt_i32 s5, s8
-; GFX9-NEXT: s_cselect_b32 s5, s5, s8
-; GFX9-NEXT: s_cmp_gt_i32 s4, s7
-; GFX9-NEXT: s_cselect_b32 s4, s4, s7
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s4
-; GFX9-NEXT: s_sext_i32_i16 s5, s4
-; GFX9-NEXT: s_sext_i32_i16 s7, s6
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_ashr_i32 s6, s6, 16
-; GFX9-NEXT: s_cmp_lt_i32 s5, s7
-; GFX9-NEXT: s_cselect_b32 s5, s5, s7
-; GFX9-NEXT: s_cmp_lt_i32 s4, s6
-; GFX9-NEXT: s_cselect_b32 s4, s4, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s4
-; GFX9-NEXT: s_lshr_b32 s5, s3, 16
-; GFX9-NEXT: s_lshr_b32 s6, s4, 16
-; GFX9-NEXT: s_add_i32 s3, s3, s4
-; GFX9-NEXT: s_add_i32 s5, s5, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s5
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-NEXT: v_pk_add_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_pk_add_i16 v1, s1, v1 clamp
+; GFX9-NEXT: v_pk_add_i16 v2, s2, v2 clamp
+; GFX9-NEXT: v_pk_add_i16 v3, s3, v3 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_saddsat_v8i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sext_i32_i16 s8, s0
-; GFX10-NEXT: s_sext_i32_i16 s9, 0
-; GFX10-NEXT: s_ashr_i32 s10, s0, 16
-; GFX10-NEXT: s_cmp_gt_i32 s8, s9
-; GFX10-NEXT: s_mov_b32 s13, 0x7fff7fff
-; GFX10-NEXT: s_cselect_b32 s11, s8, s9
-; GFX10-NEXT: s_cmp_gt_i32 s10, 0
-; GFX10-NEXT: s_mov_b32 s15, 0x80008000
-; GFX10-NEXT: s_cselect_b32 s12, s10, 0
-; GFX10-NEXT: s_sext_i32_i16 s17, s4
-; GFX10-NEXT: s_pack_ll_b32_b16 s11, s11, s12
-; GFX10-NEXT: s_movk_i32 s12, 0x7fff
-; GFX10-NEXT: s_lshr_b32 s14, s11, 16
-; GFX10-NEXT: s_sub_i32 s11, s13, s11
-; GFX10-NEXT: s_sub_i32 s14, s12, s14
-; GFX10-NEXT: s_cmp_lt_i32 s8, s9
+; GFX10-NEXT: v_pk_add_i16 v0, s0, s4 clamp
+; GFX10-NEXT: v_pk_add_i16 v1, s1, s5 clamp
+; GFX10-NEXT: v_pk_add_i16 v2, s2, s6 clamp
+; GFX10-NEXT: v_pk_add_i16 v3, s3, s7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s8, s8, s9
-; GFX10-NEXT: s_cmp_lt_i32 s10, 0
-; GFX10-NEXT: s_cselect_b32 s10, s10, 0
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s8, s8, s10
-; GFX10-NEXT: s_mov_b32 s10, 0x8000
-; GFX10-NEXT: s_lshr_b32 s16, s8, 16
-; GFX10-NEXT: s_sub_i32 s8, s15, s8
-; GFX10-NEXT: s_sub_i32 s16, s10, s16
-; GFX10-NEXT: s_pack_ll_b32_b16 s8, s8, s16
-; GFX10-NEXT: s_sext_i32_i16 s16, s8
-; GFX10-NEXT: s_ashr_i32 s8, s8, 16
-; GFX10-NEXT: s_cmp_gt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_cmp_gt_i32 s8, s4
-; GFX10-NEXT: s_sext_i32_i16 s17, s5
-; GFX10-NEXT: s_cselect_b32 s4, s8, s4
-; GFX10-NEXT: s_pack_ll_b32_b16 s8, s11, s14
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s16, s4
-; GFX10-NEXT: s_sext_i32_i16 s14, s8
-; GFX10-NEXT: s_sext_i32_i16 s11, s4
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_ashr_i32 s8, s8, 16
-; GFX10-NEXT: s_cmp_lt_i32 s11, s14
-; GFX10-NEXT: s_cselect_b32 s11, s11, s14
-; GFX10-NEXT: s_cmp_lt_i32 s4, s8
-; GFX10-NEXT: s_cselect_b32 s4, s4, s8
-; GFX10-NEXT: s_lshr_b32 s8, s0, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s11, s4
-; GFX10-NEXT: s_lshr_b32 s11, s4, 16
-; GFX10-NEXT: s_add_i32 s0, s0, s4
-; GFX10-NEXT: s_sext_i32_i16 s4, s1
-; GFX10-NEXT: s_add_i32 s8, s8, s11
-; GFX10-NEXT: s_ashr_i32 s11, s1, 16
-; GFX10-NEXT: s_cmp_gt_i32 s4, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s8
-; GFX10-NEXT: s_cselect_b32 s14, s4, s9
-; GFX10-NEXT: s_cmp_gt_i32 s11, 0
-; GFX10-NEXT: s_cselect_b32 s16, s11, 0
-; GFX10-NEXT: s_pack_ll_b32_b16 s14, s14, s16
-; GFX10-NEXT: s_lshr_b32 s16, s14, 16
-; GFX10-NEXT: s_sub_i32 s14, s13, s14
-; GFX10-NEXT: s_sub_i32 s16, s12, s16
-; GFX10-NEXT: s_cmp_lt_i32 s4, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s14, s14, s16
-; GFX10-NEXT: s_cselect_b32 s4, s4, s9
-; GFX10-NEXT: s_cmp_lt_i32 s11, 0
-; GFX10-NEXT: s_cselect_b32 s11, s11, 0
-; GFX10-NEXT: s_ashr_i32 s5, s5, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s11
-; GFX10-NEXT: s_lshr_b32 s11, s4, 16
-; GFX10-NEXT: s_sub_i32 s4, s15, s4
-; GFX10-NEXT: s_sub_i32 s11, s10, s11
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s11
-; GFX10-NEXT: s_sext_i32_i16 s11, s4
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_cmp_gt_i32 s11, s17
-; GFX10-NEXT: s_cselect_b32 s11, s11, s17
-; GFX10-NEXT: s_cmp_gt_i32 s4, s5
-; GFX10-NEXT: s_sext_i32_i16 s17, s6
-; GFX10-NEXT: s_cselect_b32 s4, s4, s5
-; GFX10-NEXT: s_sext_i32_i16 s5, s14
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s11, s4
-; GFX10-NEXT: s_ashr_i32 s11, s14, 16
-; GFX10-NEXT: s_sext_i32_i16 s14, s4
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_cmp_lt_i32 s14, s5
-; GFX10-NEXT: s_cselect_b32 s5, s14, s5
-; GFX10-NEXT: s_cmp_lt_i32 s4, s11
-; GFX10-NEXT: s_sext_i32_i16 s14, s2
-; GFX10-NEXT: s_cselect_b32 s4, s4, s11
-; GFX10-NEXT: s_lshr_b32 s11, s1, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s5, s4
-; GFX10-NEXT: s_ashr_i32 s5, s2, 16
-; GFX10-NEXT: s_lshr_b32 s16, s4, 16
-; GFX10-NEXT: s_add_i32 s1, s1, s4
-; GFX10-NEXT: s_add_i32 s11, s11, s16
-; GFX10-NEXT: s_cmp_gt_i32 s14, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s11
-; GFX10-NEXT: s_cselect_b32 s4, s14, s9
-; GFX10-NEXT: s_cmp_gt_i32 s5, 0
-; GFX10-NEXT: s_cselect_b32 s16, s5, 0
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s16
-; GFX10-NEXT: s_lshr_b32 s16, s4, 16
-; GFX10-NEXT: s_sub_i32 s4, s13, s4
-; GFX10-NEXT: s_sub_i32 s16, s12, s16
-; GFX10-NEXT: s_cmp_lt_i32 s14, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s16
-; GFX10-NEXT: s_cselect_b32 s14, s14, s9
-; GFX10-NEXT: s_cmp_lt_i32 s5, 0
-; GFX10-NEXT: s_cselect_b32 s5, s5, 0
-; GFX10-NEXT: s_ashr_i32 s6, s6, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s5, s14, s5
-; GFX10-NEXT: s_lshr_b32 s14, s5, 16
-; GFX10-NEXT: s_sub_i32 s5, s15, s5
-; GFX10-NEXT: s_sub_i32 s14, s10, s14
-; GFX10-NEXT: s_pack_ll_b32_b16 s5, s5, s14
-; GFX10-NEXT: s_sext_i32_i16 s14, s5
-; GFX10-NEXT: s_ashr_i32 s5, s5, 16
-; GFX10-NEXT: s_cmp_gt_i32 s14, s17
-; GFX10-NEXT: s_cselect_b32 s14, s14, s17
-; GFX10-NEXT: s_cmp_gt_i32 s5, s6
-; GFX10-NEXT: s_cselect_b32 s5, s5, s6
-; GFX10-NEXT: s_sext_i32_i16 s6, s4
-; GFX10-NEXT: s_pack_ll_b32_b16 s5, s14, s5
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_sext_i32_i16 s14, s5
-; GFX10-NEXT: s_ashr_i32 s5, s5, 16
-; GFX10-NEXT: s_cmp_lt_i32 s14, s6
-; GFX10-NEXT: s_cselect_b32 s6, s14, s6
-; GFX10-NEXT: s_cmp_lt_i32 s5, s4
-; GFX10-NEXT: s_sext_i32_i16 s14, s3
-; GFX10-NEXT: s_cselect_b32 s4, s5, s4
-; GFX10-NEXT: s_lshr_b32 s5, s2, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s6, s4
-; GFX10-NEXT: s_ashr_i32 s6, s3, 16
-; GFX10-NEXT: s_lshr_b32 s16, s4, 16
-; GFX10-NEXT: s_add_i32 s2, s2, s4
-; GFX10-NEXT: s_add_i32 s5, s5, s16
-; GFX10-NEXT: s_cmp_gt_i32 s14, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s5
-; GFX10-NEXT: s_cselect_b32 s4, s14, s9
-; GFX10-NEXT: s_cmp_gt_i32 s6, 0
-; GFX10-NEXT: s_cselect_b32 s16, s6, 0
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s16
-; GFX10-NEXT: s_lshr_b32 s16, s4, 16
-; GFX10-NEXT: s_sub_i32 s4, s13, s4
-; GFX10-NEXT: s_sub_i32 s12, s12, s16
-; GFX10-NEXT: s_cmp_lt_i32 s14, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s12
-; GFX10-NEXT: s_cselect_b32 s9, s14, s9
-; GFX10-NEXT: s_cmp_lt_i32 s6, 0
-; GFX10-NEXT: s_cselect_b32 s6, s6, 0
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s9, s6
-; GFX10-NEXT: s_lshr_b32 s9, s6, 16
-; GFX10-NEXT: s_sub_i32 s6, s15, s6
-; GFX10-NEXT: s_sub_i32 s9, s10, s9
-; GFX10-NEXT: s_sext_i32_i16 s10, s7
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s9
-; GFX10-NEXT: s_ashr_i32 s7, s7, 16
-; GFX10-NEXT: s_sext_i32_i16 s9, s6
-; GFX10-NEXT: s_ashr_i32 s6, s6, 16
-; GFX10-NEXT: s_cmp_gt_i32 s9, s10
-; GFX10-NEXT: s_cselect_b32 s9, s9, s10
-; GFX10-NEXT: s_cmp_gt_i32 s6, s7
-; GFX10-NEXT: s_cselect_b32 s6, s6, s7
-; GFX10-NEXT: s_sext_i32_i16 s7, s4
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s9, s6
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_sext_i32_i16 s9, s6
-; GFX10-NEXT: s_ashr_i32 s6, s6, 16
-; GFX10-NEXT: s_cmp_lt_i32 s9, s7
-; GFX10-NEXT: s_cselect_b32 s7, s9, s7
-; GFX10-NEXT: s_cmp_lt_i32 s6, s4
-; GFX10-NEXT: s_cselect_b32 s4, s6, s4
-; GFX10-NEXT: s_lshr_b32 s6, s3, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s7, s4
-; GFX10-NEXT: s_lshr_b32 s7, s4, 16
-; GFX10-NEXT: s_add_i32 s3, s3, s4
-; GFX10-NEXT: s_add_i32 s6, s6, s7
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s6
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: ; return to shader part epilog
%result = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x i32>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index ac2a75383cba..f9e4ccd03955 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -39,14 +39,8 @@ define i7 @v_ssubsat_i7(i7 %lhs, i7 %rhs) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 9, v0
-; GFX9-NEXT: v_max_i16_e32 v2, -1, v0
-; GFX9-NEXT: v_min_i16_e32 v3, -1, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 9, v1
-; GFX9-NEXT: v_subrev_u16_e32 v2, 0x7fff, v2
-; GFX9-NEXT: v_subrev_u16_e32 v3, 0x8000, v3
-; GFX9-NEXT: v_max_i16_e32 v1, v2, v1
-; GFX9-NEXT: v_min_i16_e32 v1, v1, v3
-; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 9, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -57,13 +51,7 @@ define i7 @v_ssubsat_i7(i7 %lhs, i7 %rhs) {
; GFX10-NEXT: v_lshlrev_b16_e64 v0, 9, v0
; GFX10-NEXT: v_lshlrev_b16_e64 v1, 9, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_max_i16_e64 v2, v0, -1
-; GFX10-NEXT: v_min_i16_e64 v3, v0, -1
-; GFX10-NEXT: v_sub_nc_u16_e64 v2, v2, 0x7fff
-; GFX10-NEXT: v_sub_nc_u16_e64 v3, v3, 0x8000
-; GFX10-NEXT: v_max_i16_e64 v1, v2, v1
-; GFX10-NEXT: v_min_i16_e64 v1, v1, v3
-; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1
+; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp
; GFX10-NEXT: v_ashrrev_i16_e64 v0, 9, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)
@@ -118,54 +106,23 @@ define amdgpu_ps i7 @s_ssubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX9-LABEL: s_ssubsat_i7:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s2, 9, 0x100000
-; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
-; GFX9-NEXT: s_sext_i32_i16 s3, s0
-; GFX9-NEXT: s_sext_i32_i16 s4, -1
-; GFX9-NEXT: s_cmp_gt_i32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s5, s3, s4
-; GFX9-NEXT: s_sub_i32 s5, s5, 0x7fff
-; GFX9-NEXT: s_cmp_lt_i32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s3, s3, s4
-; GFX9-NEXT: s_sub_i32 s3, s3, 0xffff8000
-; GFX9-NEXT: s_sext_i32_i16 s4, s5
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_cmp_gt_i32 s4, s1
-; GFX9-NEXT: s_cselect_b32 s1, s4, s1
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_sext_i32_i16 s3, s3
-; GFX9-NEXT: s_cmp_lt_i32 s1, s3
-; GFX9-NEXT: s_cselect_b32 s1, s1, s3
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
-; GFX9-NEXT: s_sext_i32_i16 s0, s0
-; GFX9-NEXT: s_ashr_i32 s0, s0, s2
+; GFX9-NEXT: s_lshl_b32 s0, s0, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_ashrrev_i16_e32 v0, 9, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_i7:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s2, 9, 0x100000
-; GFX10-NEXT: s_sext_i32_i16 s4, -1
+; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_lshl_b32 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: s_sext_i32_i16 s3, s0
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_gt_i32 s3, s4
-; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s5, s3, s4
-; GFX10-NEXT: s_sub_i32 s5, s5, 0x7fff
-; GFX10-NEXT: s_cmp_lt_i32 s3, s4
-; GFX10-NEXT: s_cselect_b32 s3, s3, s4
-; GFX10-NEXT: s_sext_i32_i16 s4, s5
-; GFX10-NEXT: s_sub_i32 s3, s3, 0xffff8000
-; GFX10-NEXT: s_cmp_gt_i32 s4, s1
-; GFX10-NEXT: s_sext_i32_i16 s3, s3
-; GFX10-NEXT: s_cselect_b32 s1, s4, s1
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s3
-; GFX10-NEXT: s_cselect_b32 s1, s1, s3
-; GFX10-NEXT: s_sub_i32 s0, s0, s1
-; GFX10-NEXT: s_sext_i32_i16 s0, s0
-; GFX10-NEXT: s_ashr_i32 s0, s0, s2
+; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp
+; GFX10-NEXT: v_ashrrev_i16_e64 v0, 9, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result
@@ -206,14 +163,8 @@ define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX9-NEXT: v_max_i16_e32 v2, -1, v0
-; GFX9-NEXT: v_min_i16_e32 v3, -1, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX9-NEXT: v_subrev_u16_e32 v2, 0x7fff, v2
-; GFX9-NEXT: v_subrev_u16_e32 v3, 0x8000, v3
-; GFX9-NEXT: v_max_i16_e32 v1, v2, v1
-; GFX9-NEXT: v_min_i16_e32 v1, v1, v3
-; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -224,13 +175,7 @@ define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) {
; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0
; GFX10-NEXT: v_lshlrev_b16_e64 v1, 8, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_max_i16_e64 v2, v0, -1
-; GFX10-NEXT: v_min_i16_e64 v3, v0, -1
-; GFX10-NEXT: v_sub_nc_u16_e64 v2, v2, 0x7fff
-; GFX10-NEXT: v_sub_nc_u16_e64 v3, v3, 0x8000
-; GFX10-NEXT: v_max_i16_e64 v1, v2, v1
-; GFX10-NEXT: v_min_i16_e64 v1, v1, v3
-; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1
+; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp
; GFX10-NEXT: v_ashrrev_i16_e64 v0, 8, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
@@ -285,54 +230,23 @@ define amdgpu_ps i8 @s_ssubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX9-LABEL: s_ssubsat_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s2, 8, 0x100000
-; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
-; GFX9-NEXT: s_sext_i32_i16 s3, s0
-; GFX9-NEXT: s_sext_i32_i16 s4, -1
-; GFX9-NEXT: s_cmp_gt_i32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s5, s3, s4
-; GFX9-NEXT: s_sub_i32 s5, s5, 0x7fff
-; GFX9-NEXT: s_cmp_lt_i32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s3, s3, s4
-; GFX9-NEXT: s_sub_i32 s3, s3, 0xffff8000
-; GFX9-NEXT: s_sext_i32_i16 s4, s5
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_cmp_gt_i32 s4, s1
-; GFX9-NEXT: s_cselect_b32 s1, s4, s1
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_sext_i32_i16 s3, s3
-; GFX9-NEXT: s_cmp_lt_i32 s1, s3
-; GFX9-NEXT: s_cselect_b32 s1, s1, s3
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
-; GFX9-NEXT: s_sext_i32_i16 s0, s0
-; GFX9-NEXT: s_ashr_i32 s0, s0, s2
+; GFX9-NEXT: s_lshl_b32 s0, s0, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000
-; GFX10-NEXT: s_sext_i32_i16 s4, -1
+; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_lshl_b32 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: s_sext_i32_i16 s3, s0
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_gt_i32 s3, s4
-; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s5, s3, s4
-; GFX10-NEXT: s_sub_i32 s5, s5, 0x7fff
-; GFX10-NEXT: s_cmp_lt_i32 s3, s4
-; GFX10-NEXT: s_cselect_b32 s3, s3, s4
-; GFX10-NEXT: s_sext_i32_i16 s4, s5
-; GFX10-NEXT: s_sub_i32 s3, s3, 0xffff8000
-; GFX10-NEXT: s_cmp_gt_i32 s4, s1
-; GFX10-NEXT: s_sext_i32_i16 s3, s3
-; GFX10-NEXT: s_cselect_b32 s1, s4, s1
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s3
-; GFX10-NEXT: s_cselect_b32 s1, s1, s3
-; GFX10-NEXT: s_sub_i32 s0, s0, s1
-; GFX10-NEXT: s_sext_i32_i16 s0, s0
-; GFX10-NEXT: s_ashr_i32 s0, s0, s2
+; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp
+; GFX10-NEXT: v_ashrrev_i16_e64 v0, 8, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result
@@ -408,26 +322,12 @@ define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: s_movk_i32 s4, 0x7fff
-; GFX9-NEXT: v_max_i16_e32 v4, -1, v0
+; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX9-NEXT: v_subrev_u16_e32 v4, s4, v4
-; GFX9-NEXT: s_movk_i32 s5, 0x8000
-; GFX9-NEXT: v_min_i16_e32 v5, -1, v0
-; GFX9-NEXT: v_max_i16_e32 v1, v4, v1
-; GFX9-NEXT: v_subrev_u16_e32 v5, s5, v5
-; GFX9-NEXT: v_min_i16_e32 v1, v1, v5
-; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1
-; GFX9-NEXT: v_max_i16_e32 v1, -1, v2
-; GFX9-NEXT: v_subrev_u16_e32 v1, s4, v1
-; GFX9-NEXT: v_min_i16_e32 v4, -1, v2
-; GFX9-NEXT: v_subrev_u16_e32 v4, s5, v4
-; GFX9-NEXT: v_max_i16_e32 v1, v1, v3
-; GFX9-NEXT: v_min_i16_e32 v1, v1, v4
+; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp
; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: v_sub_u16_e32 v1, v2, v1
+; GFX9-NEXT: v_sub_i16 v1, v2, v3 clamp
; GFX9-NEXT: v_and_b32_sdwa v0, sext(v0), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
@@ -438,31 +338,17 @@ define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8
-; GFX10-NEXT: v_lshlrev_b16_e64 v2, 8, v0
-; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: s_movk_i32 s5, 0x7fff
-; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_lshlrev_b16_e64 v1, 8, v1
-; GFX10-NEXT: v_max_i16_e64 v4, v2, -1
-; GFX10-NEXT: v_max_i16_e64 v5, v0, -1
-; GFX10-NEXT: v_min_i16_e64 v6, v2, -1
-; GFX10-NEXT: v_min_i16_e64 v7, v0, -1
-; GFX10-NEXT: s_movk_i32 s4, 0x8000
-; GFX10-NEXT: v_sub_nc_u16_e64 v4, v4, s5
-; GFX10-NEXT: v_sub_nc_u16_e64 v5, v5, s5
-; GFX10-NEXT: v_sub_nc_u16_e64 v6, v6, s4
-; GFX10-NEXT: v_sub_nc_u16_e64 v7, v7, s4
+; GFX10-NEXT: v_lshlrev_b16_e64 v3, 8, v1
+; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0
; GFX10-NEXT: s_movk_i32 s4, 0xff
-; GFX10-NEXT: v_max_i16_e64 v1, v4, v1
-; GFX10-NEXT: v_max_i16_e64 v10, v5, v3
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_i16_e64 v1, v1, v6
-; GFX10-NEXT: v_min_i16_e64 v3, v10, v7
-; GFX10-NEXT: v_sub_nc_u16_e64 v1, v2, v1
-; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v3
-; GFX10-NEXT: v_and_b32_sdwa v1, sext(v1), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX10-NEXT: v_sub_nc_i16 v1, v2, v1 clamp
+; GFX10-NEXT: v_sub_nc_i16 v0, v0, v3 clamp
+; GFX10-NEXT: v_and_b32_sdwa v1, sext(v1), s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
@@ -571,112 +457,40 @@ define amdgpu_ps i16 @s_ssubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX9-LABEL: s_ssubsat_v2i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s4, 8, 0x100000
-; GFX9-NEXT: s_lshr_b32 s2, s0, 8
-; GFX9-NEXT: s_lshl_b32 s0, s0, s4
; GFX9-NEXT: s_lshr_b32 s3, s1, 8
; GFX9-NEXT: s_lshl_b32 s1, s1, s4
-; GFX9-NEXT: s_sext_i32_i16 s7, s0
-; GFX9-NEXT: s_sext_i32_i16 s8, -1
-; GFX9-NEXT: s_cmp_gt_i32 s7, s8
-; GFX9-NEXT: s_movk_i32 s5, 0x7fff
-; GFX9-NEXT: s_cselect_b32 s9, s7, s8
-; GFX9-NEXT: s_sub_i32 s9, s9, s5
-; GFX9-NEXT: s_cmp_lt_i32 s7, s8
-; GFX9-NEXT: s_movk_i32 s6, 0x8000
-; GFX9-NEXT: s_cselect_b32 s7, s7, s8
-; GFX9-NEXT: s_sub_i32 s7, s7, s6
-; GFX9-NEXT: s_sext_i32_i16 s9, s9
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_cmp_gt_i32 s9, s1
-; GFX9-NEXT: s_cselect_b32 s1, s9, s1
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_sext_i32_i16 s7, s7
-; GFX9-NEXT: s_cmp_lt_i32 s1, s7
-; GFX9-NEXT: s_cselect_b32 s1, s1, s7
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
-; GFX9-NEXT: s_sext_i32_i16 s0, s0
-; GFX9-NEXT: s_lshl_b32 s1, s2, s4
-; GFX9-NEXT: s_lshl_b32 s2, s3, s4
-; GFX9-NEXT: s_ashr_i32 s0, s0, s4
-; GFX9-NEXT: s_sext_i32_i16 s3, s1
-; GFX9-NEXT: s_cmp_gt_i32 s3, s8
-; GFX9-NEXT: s_cselect_b32 s7, s3, s8
-; GFX9-NEXT: s_sub_i32 s5, s7, s5
-; GFX9-NEXT: s_cmp_lt_i32 s3, s8
-; GFX9-NEXT: s_cselect_b32 s3, s3, s8
-; GFX9-NEXT: s_sub_i32 s3, s3, s6
-; GFX9-NEXT: s_sext_i32_i16 s5, s5
-; GFX9-NEXT: s_sext_i32_i16 s2, s2
-; GFX9-NEXT: s_cmp_gt_i32 s5, s2
-; GFX9-NEXT: s_cselect_b32 s2, s5, s2
-; GFX9-NEXT: s_sext_i32_i16 s2, s2
-; GFX9-NEXT: s_sext_i32_i16 s3, s3
-; GFX9-NEXT: s_cmp_lt_i32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s2, s3
-; GFX9-NEXT: s_sub_i32 s1, s1, s2
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_movk_i32 s2, 0xff
-; GFX9-NEXT: s_ashr_i32 s1, s1, s4
-; GFX9-NEXT: s_and_b32 s1, s1, s2
-; GFX9-NEXT: s_and_b32 s0, s0, s2
-; GFX9-NEXT: s_lshl_b32 s1, s1, s4
-; GFX9-NEXT: s_or_b32 s0, s0, s1
+; GFX9-NEXT: s_lshr_b32 s2, s0, 8
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: s_lshl_b32 s0, s0, s4
+; GFX9-NEXT: s_lshl_b32 s1, s3, s4
+; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp
+; GFX9-NEXT: s_lshl_b32 s0, s2, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_sub_i16 v1, s0, v1 clamp
+; GFX9-NEXT: s_movk_i32 s0, 0xff
+; GFX9-NEXT: v_and_b32_sdwa v0, sext(v0), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v2i8:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000
-; GFX10-NEXT: s_lshr_b32 s3, s0, 8
-; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_sext_i32_i16 s6, -1
-; GFX10-NEXT: s_sext_i32_i16 s5, s0
+; GFX10-NEXT: s_lshr_b32 s2, s0, 8
+; GFX10-NEXT: s_bfe_u32 s3, 8, 0x100000
; GFX10-NEXT: s_lshr_b32 s4, s1, 8
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: s_cmp_gt_i32 s5, s6
-; GFX10-NEXT: s_movk_i32 s7, 0x7fff
-; GFX10-NEXT: s_cselect_b32 s8, s5, s6
-; GFX10-NEXT: s_movk_i32 s9, 0x8000
-; GFX10-NEXT: s_sub_i32 s8, s8, s7
-; GFX10-NEXT: s_cmp_lt_i32 s5, s6
-; GFX10-NEXT: s_sext_i32_i16 s8, s8
-; GFX10-NEXT: s_cselect_b32 s5, s5, s6
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_sub_i32 s5, s5, s9
-; GFX10-NEXT: s_cmp_gt_i32 s8, s1
-; GFX10-NEXT: s_sext_i32_i16 s5, s5
-; GFX10-NEXT: s_cselect_b32 s1, s8, s1
+; GFX10-NEXT: s_lshl_b32 s0, s0, s3
+; GFX10-NEXT: s_lshl_b32 s1, s1, s3
+; GFX10-NEXT: s_lshl_b32 s2, s2, s3
+; GFX10-NEXT: s_lshl_b32 s3, s4, s3
+; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp
+; GFX10-NEXT: v_sub_nc_i16 v1, s2, s3 clamp
+; GFX10-NEXT: s_movk_i32 s0, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s5
-; GFX10-NEXT: s_cselect_b32 s1, s1, s5
-; GFX10-NEXT: s_lshl_b32 s3, s3, s2
-; GFX10-NEXT: s_sub_i32 s0, s0, s1
-; GFX10-NEXT: s_lshl_b32 s1, s4, s2
-; GFX10-NEXT: s_sext_i32_i16 s0, s0
-; GFX10-NEXT: s_sext_i32_i16 s4, s3
-; GFX10-NEXT: s_ashr_i32 s0, s0, s2
-; GFX10-NEXT: s_cmp_gt_i32 s4, s6
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cselect_b32 s5, s4, s6
-; GFX10-NEXT: s_sub_i32 s5, s5, s7
-; GFX10-NEXT: s_cmp_lt_i32 s4, s6
-; GFX10-NEXT: s_sext_i32_i16 s5, s5
-; GFX10-NEXT: s_cselect_b32 s4, s4, s6
-; GFX10-NEXT: s_sub_i32 s4, s4, s9
-; GFX10-NEXT: s_cmp_gt_i32 s5, s1
-; GFX10-NEXT: s_sext_i32_i16 s4, s4
-; GFX10-NEXT: s_cselect_b32 s1, s5, s1
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s4
-; GFX10-NEXT: s_cselect_b32 s1, s1, s4
-; GFX10-NEXT: s_sub_i32 s1, s3, s1
-; GFX10-NEXT: s_movk_i32 s3, 0xff
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_and_b32 s0, s0, s3
-; GFX10-NEXT: s_ashr_i32 s1, s1, s2
-; GFX10-NEXT: s_and_b32 s1, s1, s3
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: s_or_b32 s0, s0, s1
+; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v1, sext(v1), s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
@@ -815,52 +629,25 @@ define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 24, v0
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: s_movk_i32 s4, 0x7fff
-; GFX9-NEXT: v_max_i16_e32 v8, -1, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX9-NEXT: v_subrev_u16_e32 v8, s4, v8
-; GFX9-NEXT: s_movk_i32 s5, 0x8000
-; GFX9-NEXT: v_min_i16_e32 v10, -1, v0
-; GFX9-NEXT: v_max_i16_e32 v1, v8, v1
-; GFX9-NEXT: v_subrev_u16_e32 v10, s5, v10
-; GFX9-NEXT: v_min_i16_e32 v1, v1, v10
-; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1
-; GFX9-NEXT: v_max_i16_e32 v1, -1, v2
-; GFX9-NEXT: v_subrev_u16_e32 v1, s4, v1
-; GFX9-NEXT: v_min_i16_e32 v8, -1, v2
-; GFX9-NEXT: v_subrev_u16_e32 v8, s5, v8
-; GFX9-NEXT: v_max_i16_e32 v1, v1, v5
-; GFX9-NEXT: v_min_i16_e32 v1, v1, v8
-; GFX9-NEXT: v_sub_u16_e32 v1, v2, v1
+; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp
+; GFX9-NEXT: v_sub_i16 v1, v2, v5 clamp
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
-; GFX9-NEXT: v_mov_b32_e32 v9, 0x7fff
-; GFX9-NEXT: v_max_i16_e32 v5, -1, v2
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v6
-; GFX9-NEXT: v_min_i16_e32 v6, -1, v2
-; GFX9-NEXT: v_sub_u16_e32 v5, v5, v9
-; GFX9-NEXT: v_subrev_u16_e32 v6, s5, v6
-; GFX9-NEXT: v_max_i16_e32 v3, v5, v3
-; GFX9-NEXT: v_min_i16_e32 v3, v3, v6
-; GFX9-NEXT: v_sub_u16_e32 v2, v2, v3
-; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v4
-; GFX9-NEXT: v_max_i16_e32 v5, -1, v3
-; GFX9-NEXT: v_min_i16_e32 v6, -1, v3
-; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v7
-; GFX9-NEXT: v_sub_u16_e32 v5, v5, v9
; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: v_subrev_u16_e32 v6, 0x8000, v6
-; GFX9-NEXT: v_max_i16_e32 v4, v5, v4
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX9-NEXT: v_min_i16_e32 v4, v4, v6
+; GFX9-NEXT: v_sub_i16 v2, v2, v3 clamp
+; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v4
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v7
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX9-NEXT: v_sub_u16_e32 v3, v3, v4
+; GFX9-NEXT: v_sub_i16 v3, v3, v4 clamp
; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v1
; GFX9-NEXT: v_and_b32_sdwa v1, sext(v2), s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v2, sext(v3), s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
@@ -871,57 +658,30 @@ define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_lshlrev_b16_e64 v4, 8, v0
; GFX10-NEXT: s_mov_b32 s4, 8
-; GFX10-NEXT: v_lshlrev_b16_e64 v7, 8, v1
+; GFX10-NEXT: v_lshlrev_b16_e64 v5, 8, v0
; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_max_i16_e64 v8, v4, -1
-; GFX10-NEXT: s_movk_i32 s4, 0x7fff
-; GFX10-NEXT: v_min_i16_e64 v10, v4, -1
-; GFX10-NEXT: v_max_i16_e64 v9, v2, -1
+; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshlrev_b16_e64 v6, 8, v1
; GFX10-NEXT: s_mov_b32 s5, 16
-; GFX10-NEXT: v_sub_nc_u16_e64 v8, v8, s4
-; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s5, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: s_mov_b32 s6, 24
-; GFX10-NEXT: v_lshrrev_b32_sdwa v6, s5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: s_movk_i32 s5, 0x8000
-; GFX10-NEXT: v_sub_nc_u16_e64 v15, v9, s4
-; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s6, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_min_i16_e64 v11, v2, -1
-; GFX10-NEXT: v_max_i16_e64 v7, v8, v7
-; GFX10-NEXT: v_sub_nc_u16_e64 v10, v10, s5
-; GFX10-NEXT: v_max_i16_e64 v5, v15, v5
-; GFX10-NEXT: v_mov_b32_e32 v9, 0x7fff
-; GFX10-NEXT: v_sub_nc_u16_e64 v8, v11, s5
-; GFX10-NEXT: v_max_i16_e64 v11, v3, -1
-; GFX10-NEXT: v_min_i16_e64 v7, v7, v10
-; GFX10-NEXT: v_max_i16_e64 v10, v0, -1
-; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s6, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_min_i16_e64 v5, v5, v8
-; GFX10-NEXT: v_sub_nc_u16_e64 v11, v11, v9
-; GFX10-NEXT: v_min_i16_e64 v8, v3, -1
-; GFX10-NEXT: v_sub_nc_u16_e64 v15, v10, v9
-; GFX10-NEXT: v_min_i16_e64 v12, v0, -1
-; GFX10-NEXT: v_sub_nc_u16_e64 v2, v2, v5
-; GFX10-NEXT: v_max_i16_e64 v6, v11, v6
-; GFX10-NEXT: v_sub_nc_u16_e64 v5, v8, s5
-; GFX10-NEXT: v_max_i16_e64 v1, v15, v1
-; GFX10-NEXT: v_sub_nc_u16_e64 v8, v12, 0x8000
-; GFX10-NEXT: s_movk_i32 s4, 0xff
-; GFX10-NEXT: v_sub_nc_u16_e64 v4, v4, v7
-; GFX10-NEXT: v_and_b32_sdwa v2, sext(v2), s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_min_i16_e64 v5, v6, v5
-; GFX10-NEXT: v_min_i16_e64 v1, v1, v8
+; GFX10-NEXT: s_mov_b32 s4, 24
+; GFX10-NEXT: v_lshrrev_b32_sdwa v4, s5, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_sub_nc_i16 v2, v2, v3 clamp
+; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: s_movk_i32 s5, 0xff
+; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v2, sext(v2), s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_sub_nc_i16 v5, v5, v6 clamp
+; GFX10-NEXT: v_sub_nc_i16 v3, v4, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_ashrrev_i16_e64 v4, 8, v4
+; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; GFX10-NEXT: v_sub_nc_u16_e64 v3, v3, v5
-; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1
-; GFX10-NEXT: v_and_or_b32 v1, v4, s4, v2
-; GFX10-NEXT: v_and_b32_sdwa v2, sext(v3), s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0
+; GFX10-NEXT: v_ashrrev_i16_e64 v4, 8, v5
+; GFX10-NEXT: v_and_b32_sdwa v1, sext(v3), s5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v0, sext(v0), s5 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_or_b32 v2, v4, s5, v2
+; GFX10-NEXT: v_or3_b32 v0, v2, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
@@ -1118,212 +878,70 @@ define amdgpu_ps i32 @s_ssubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX9-LABEL: s_ssubsat_v4i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s8, 8, 0x100000
-; GFX9-NEXT: s_lshr_b32 s2, s0, 8
-; GFX9-NEXT: s_lshr_b32 s3, s0, 16
-; GFX9-NEXT: s_lshr_b32 s4, s0, 24
-; GFX9-NEXT: s_lshl_b32 s0, s0, s8
; GFX9-NEXT: s_lshr_b32 s5, s1, 8
; GFX9-NEXT: s_lshr_b32 s6, s1, 16
; GFX9-NEXT: s_lshr_b32 s7, s1, 24
; GFX9-NEXT: s_lshl_b32 s1, s1, s8
-; GFX9-NEXT: s_sext_i32_i16 s11, s0
-; GFX9-NEXT: s_sext_i32_i16 s12, -1
-; GFX9-NEXT: s_cmp_gt_i32 s11, s12
-; GFX9-NEXT: s_movk_i32 s9, 0x7fff
-; GFX9-NEXT: s_cselect_b32 s13, s11, s12
-; GFX9-NEXT: s_sub_i32 s13, s13, s9
-; GFX9-NEXT: s_cmp_lt_i32 s11, s12
-; GFX9-NEXT: s_movk_i32 s10, 0x8000
-; GFX9-NEXT: s_cselect_b32 s11, s11, s12
-; GFX9-NEXT: s_sub_i32 s11, s11, s10
-; GFX9-NEXT: s_sext_i32_i16 s13, s13
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_cmp_gt_i32 s13, s1
-; GFX9-NEXT: s_cselect_b32 s1, s13, s1
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_sext_i32_i16 s11, s11
-; GFX9-NEXT: s_cmp_lt_i32 s1, s11
-; GFX9-NEXT: s_cselect_b32 s1, s1, s11
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
-; GFX9-NEXT: s_sext_i32_i16 s0, s0
-; GFX9-NEXT: s_lshl_b32 s1, s2, s8
-; GFX9-NEXT: s_lshl_b32 s2, s5, s8
-; GFX9-NEXT: s_ashr_i32 s0, s0, s8
-; GFX9-NEXT: s_sext_i32_i16 s5, s1
-; GFX9-NEXT: s_cmp_gt_i32 s5, s12
-; GFX9-NEXT: s_cselect_b32 s11, s5, s12
-; GFX9-NEXT: s_sub_i32 s11, s11, s9
-; GFX9-NEXT: s_cmp_lt_i32 s5, s12
-; GFX9-NEXT: s_cselect_b32 s5, s5, s12
-; GFX9-NEXT: s_sub_i32 s5, s5, s10
-; GFX9-NEXT: s_sext_i32_i16 s11, s11
-; GFX9-NEXT: s_sext_i32_i16 s2, s2
-; GFX9-NEXT: s_cmp_gt_i32 s11, s2
-; GFX9-NEXT: s_cselect_b32 s2, s11, s2
-; GFX9-NEXT: s_sext_i32_i16 s2, s2
-; GFX9-NEXT: s_sext_i32_i16 s5, s5
-; GFX9-NEXT: s_cmp_lt_i32 s2, s5
-; GFX9-NEXT: s_cselect_b32 s2, s2, s5
-; GFX9-NEXT: s_sub_i32 s1, s1, s2
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_lshl_b32 s2, s3, s8
-; GFX9-NEXT: s_lshl_b32 s3, s6, s8
-; GFX9-NEXT: s_ashr_i32 s1, s1, s8
-; GFX9-NEXT: s_sext_i32_i16 s5, s2
-; GFX9-NEXT: s_cmp_gt_i32 s5, s12
-; GFX9-NEXT: s_cselect_b32 s6, s5, s12
-; GFX9-NEXT: s_sub_i32 s6, s6, s9
-; GFX9-NEXT: s_cmp_lt_i32 s5, s12
-; GFX9-NEXT: s_cselect_b32 s5, s5, s12
-; GFX9-NEXT: s_sub_i32 s5, s5, s10
-; GFX9-NEXT: s_sext_i32_i16 s6, s6
-; GFX9-NEXT: s_sext_i32_i16 s3, s3
-; GFX9-NEXT: s_cmp_gt_i32 s6, s3
-; GFX9-NEXT: s_cselect_b32 s3, s6, s3
-; GFX9-NEXT: s_sext_i32_i16 s3, s3
-; GFX9-NEXT: s_sext_i32_i16 s5, s5
-; GFX9-NEXT: s_cmp_lt_i32 s3, s5
-; GFX9-NEXT: s_cselect_b32 s3, s3, s5
-; GFX9-NEXT: s_sub_i32 s2, s2, s3
-; GFX9-NEXT: s_sext_i32_i16 s2, s2
-; GFX9-NEXT: s_lshl_b32 s3, s4, s8
-; GFX9-NEXT: s_lshl_b32 s4, s7, s8
-; GFX9-NEXT: s_ashr_i32 s2, s2, s8
-; GFX9-NEXT: s_sext_i32_i16 s5, s3
-; GFX9-NEXT: s_cmp_gt_i32 s5, s12
-; GFX9-NEXT: s_cselect_b32 s6, s5, s12
-; GFX9-NEXT: s_sub_i32 s6, s6, s9
-; GFX9-NEXT: s_cmp_lt_i32 s5, s12
-; GFX9-NEXT: s_cselect_b32 s5, s5, s12
-; GFX9-NEXT: s_sub_i32 s5, s5, s10
-; GFX9-NEXT: s_sext_i32_i16 s6, s6
-; GFX9-NEXT: s_sext_i32_i16 s4, s4
-; GFX9-NEXT: s_cmp_gt_i32 s6, s4
-; GFX9-NEXT: s_cselect_b32 s4, s6, s4
-; GFX9-NEXT: s_sext_i32_i16 s4, s4
-; GFX9-NEXT: s_sext_i32_i16 s5, s5
-; GFX9-NEXT: s_cmp_lt_i32 s4, s5
-; GFX9-NEXT: s_cselect_b32 s4, s4, s5
-; GFX9-NEXT: s_sub_i32 s3, s3, s4
-; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: s_and_b32 s1, s1, s4
-; GFX9-NEXT: s_and_b32 s0, s0, s4
-; GFX9-NEXT: s_lshl_b32 s1, s1, 8
-; GFX9-NEXT: s_sext_i32_i16 s3, s3
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: s_and_b32 s1, s2, s4
-; GFX9-NEXT: s_lshl_b32 s1, s1, 16
-; GFX9-NEXT: s_ashr_i32 s3, s3, s8
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: s_and_b32 s1, s3, s4
-; GFX9-NEXT: s_lshl_b32 s1, s1, 24
-; GFX9-NEXT: s_or_b32 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: s_lshl_b32 s1, s5, s8
+; GFX9-NEXT: s_lshr_b32 s2, s0, 8
+; GFX9-NEXT: s_lshr_b32 s3, s0, 16
+; GFX9-NEXT: s_lshr_b32 s4, s0, 24
+; GFX9-NEXT: s_lshl_b32 s0, s0, s8
+; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: s_lshl_b32 s0, s2, s8
+; GFX9-NEXT: s_lshl_b32 s1, s6, s8
+; GFX9-NEXT: v_sub_i16 v1, s0, v1 clamp
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-NEXT: s_lshl_b32 s0, s3, s8
+; GFX9-NEXT: s_lshl_b32 s1, s7, s8
+; GFX9-NEXT: v_sub_i16 v2, s0, v2 clamp
+; GFX9-NEXT: s_lshl_b32 s0, s4, s8
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_sub_i16 v3, s0, v3 clamp
+; GFX9-NEXT: s_movk_i32 s0, 0xff
+; GFX9-NEXT: v_and_b32_sdwa v1, sext(v1), s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v1
+; GFX9-NEXT: v_and_b32_sdwa v1, sext(v2), s0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_sdwa v2, sext(v3), s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v4i8:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s6, 8, 0x100000
+; GFX10-NEXT: s_bfe_u32 s5, 8, 0x100000
; GFX10-NEXT: s_lshr_b32 s2, s0, 8
+; GFX10-NEXT: s_lshr_b32 s6, s1, 8
+; GFX10-NEXT: s_lshl_b32 s2, s2, s5
+; GFX10-NEXT: s_lshl_b32 s6, s6, s5
; GFX10-NEXT: s_lshr_b32 s3, s0, 16
+; GFX10-NEXT: v_sub_nc_i16 v1, s2, s6 clamp
; GFX10-NEXT: s_lshr_b32 s4, s0, 24
-; GFX10-NEXT: s_lshl_b32 s0, s0, s6
-; GFX10-NEXT: s_sext_i32_i16 s10, -1
-; GFX10-NEXT: s_sext_i32_i16 s9, s0
-; GFX10-NEXT: s_lshr_b32 s5, s1, 8
-; GFX10-NEXT: s_lshr_b32 s7, s1, 16
-; GFX10-NEXT: s_lshr_b32 s8, s1, 24
-; GFX10-NEXT: s_lshl_b32 s1, s1, s6
-; GFX10-NEXT: s_cmp_gt_i32 s9, s10
-; GFX10-NEXT: s_movk_i32 s11, 0x7fff
-; GFX10-NEXT: s_cselect_b32 s12, s9, s10
-; GFX10-NEXT: s_movk_i32 s13, 0x8000
-; GFX10-NEXT: s_sub_i32 s12, s12, s11
-; GFX10-NEXT: s_cmp_lt_i32 s9, s10
-; GFX10-NEXT: s_sext_i32_i16 s12, s12
-; GFX10-NEXT: s_cselect_b32 s9, s9, s10
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_sub_i32 s9, s9, s13
-; GFX10-NEXT: s_cmp_gt_i32 s12, s1
-; GFX10-NEXT: s_sext_i32_i16 s9, s9
-; GFX10-NEXT: s_cselect_b32 s1, s12, s1
+; GFX10-NEXT: s_movk_i32 s2, 0xff
+; GFX10-NEXT: s_lshl_b32 s0, s0, s5
+; GFX10-NEXT: s_lshl_b32 s7, s1, s5
+; GFX10-NEXT: v_and_b32_sdwa v1, sext(v1), s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_sub_nc_i16 v0, s0, s7 clamp
+; GFX10-NEXT: s_lshr_b32 s0, s1, 16
+; GFX10-NEXT: s_lshr_b32 s1, s1, 24
+; GFX10-NEXT: s_lshl_b32 s3, s3, s5
+; GFX10-NEXT: s_lshl_b32 s0, s0, s5
+; GFX10-NEXT: s_lshl_b32 s4, s4, s5
+; GFX10-NEXT: s_lshl_b32 s1, s1, s5
+; GFX10-NEXT: v_ashrrev_i16_e64 v0, 8, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX10-NEXT: v_sub_nc_i16 v2, s3, s0 clamp
+; GFX10-NEXT: v_sub_nc_i16 v3, s4, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s9
-; GFX10-NEXT: s_cselect_b32 s1, s1, s9
-; GFX10-NEXT: s_lshl_b32 s5, s5, s6
-; GFX10-NEXT: s_sub_i32 s0, s0, s1
-; GFX10-NEXT: s_lshl_b32 s1, s2, s6
-; GFX10-NEXT: s_sext_i32_i16 s0, s0
-; GFX10-NEXT: s_sext_i32_i16 s2, s1
-; GFX10-NEXT: s_ashr_i32 s0, s0, s6
-; GFX10-NEXT: s_cmp_gt_i32 s2, s10
-; GFX10-NEXT: s_sext_i32_i16 s5, s5
-; GFX10-NEXT: s_cselect_b32 s9, s2, s10
-; GFX10-NEXT: s_sub_i32 s9, s9, s11
-; GFX10-NEXT: s_cmp_lt_i32 s2, s10
-; GFX10-NEXT: s_sext_i32_i16 s9, s9
-; GFX10-NEXT: s_cselect_b32 s2, s2, s10
-; GFX10-NEXT: s_sub_i32 s2, s2, s13
-; GFX10-NEXT: s_cmp_gt_i32 s9, s5
-; GFX10-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-NEXT: s_cselect_b32 s5, s9, s5
-; GFX10-NEXT: s_sext_i32_i16 s5, s5
-; GFX10-NEXT: s_cmp_lt_i32 s5, s2
-; GFX10-NEXT: s_cselect_b32 s2, s5, s2
-; GFX10-NEXT: s_lshl_b32 s3, s3, s6
-; GFX10-NEXT: s_sub_i32 s1, s1, s2
-; GFX10-NEXT: s_sext_i32_i16 s5, s3
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_lshl_b32 s2, s7, s6
-; GFX10-NEXT: s_ashr_i32 s1, s1, s6
-; GFX10-NEXT: s_cmp_gt_i32 s5, s10
-; GFX10-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-NEXT: s_cselect_b32 s7, s5, s10
-; GFX10-NEXT: s_sub_i32 s7, s7, s11
-; GFX10-NEXT: s_cmp_lt_i32 s5, s10
-; GFX10-NEXT: s_sext_i32_i16 s7, s7
-; GFX10-NEXT: s_cselect_b32 s5, s5, s10
-; GFX10-NEXT: s_sub_i32 s5, s5, s13
-; GFX10-NEXT: s_cmp_gt_i32 s7, s2
-; GFX10-NEXT: s_sext_i32_i16 s5, s5
-; GFX10-NEXT: s_cselect_b32 s2, s7, s2
-; GFX10-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-NEXT: s_cmp_lt_i32 s2, s5
-; GFX10-NEXT: s_cselect_b32 s2, s2, s5
-; GFX10-NEXT: s_lshl_b32 s4, s4, s6
-; GFX10-NEXT: s_sub_i32 s2, s3, s2
-; GFX10-NEXT: s_sext_i32_i16 s5, s4
-; GFX10-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-NEXT: s_lshl_b32 s3, s8, s6
-; GFX10-NEXT: s_ashr_i32 s2, s2, s6
-; GFX10-NEXT: s_cmp_gt_i32 s5, s10
-; GFX10-NEXT: s_sext_i32_i16 s3, s3
-; GFX10-NEXT: s_cselect_b32 s7, s5, s10
-; GFX10-NEXT: s_sub_i32 s7, s7, s11
-; GFX10-NEXT: s_cmp_lt_i32 s5, s10
-; GFX10-NEXT: s_sext_i32_i16 s7, s7
-; GFX10-NEXT: s_cselect_b32 s5, s5, s10
-; GFX10-NEXT: s_sub_i32 s5, s5, s13
-; GFX10-NEXT: s_cmp_gt_i32 s7, s3
-; GFX10-NEXT: s_sext_i32_i16 s5, s5
-; GFX10-NEXT: s_cselect_b32 s3, s7, s3
-; GFX10-NEXT: s_movk_i32 s7, 0xff
-; GFX10-NEXT: s_sext_i32_i16 s3, s3
-; GFX10-NEXT: s_cmp_lt_i32 s3, s5
-; GFX10-NEXT: s_cselect_b32 s3, s3, s5
-; GFX10-NEXT: s_and_b32 s1, s1, s7
-; GFX10-NEXT: s_sub_i32 s3, s4, s3
-; GFX10-NEXT: s_and_b32 s0, s0, s7
-; GFX10-NEXT: s_sext_i32_i16 s3, s3
-; GFX10-NEXT: s_lshl_b32 s1, s1, 8
-; GFX10-NEXT: s_and_b32 s2, s2, s7
-; GFX10-NEXT: s_ashr_i32 s3, s3, s6
-; GFX10-NEXT: s_or_b32 s0, s0, s1
-; GFX10-NEXT: s_lshl_b32 s1, s2, 16
-; GFX10-NEXT: s_and_b32 s2, s3, s7
-; GFX10-NEXT: s_or_b32 s0, s0, s1
-; GFX10-NEXT: s_lshl_b32 s1, s2, 24
-; GFX10-NEXT: s_or_b32 s0, s0, s1
+; GFX10-NEXT: v_and_or_b32 v0, v0, s2, v1
+; GFX10-NEXT: v_and_b32_sdwa v1, sext(v2), s2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v2, sext(v3), s2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
@@ -1368,14 +986,8 @@ define i24 @v_ssubsat_i24(i24 %lhs, i24 %rhs) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX9-NEXT: v_max_i32_e32 v2, -1, v0
-; GFX9-NEXT: v_min_i32_e32 v3, -1, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX9-NEXT: v_subrev_u32_e32 v2, 0x7fffffff, v2
-; GFX9-NEXT: v_subrev_u32_e32 v3, 0x80000000, v3
-; GFX9-NEXT: v_max_i32_e32 v1, v2, v1
-; GFX9-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_sub_i32 v0, v0, v1 clamp
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -1386,13 +998,7 @@ define i24 @v_ssubsat_i24(i24 %lhs, i24 %rhs) {
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_max_i32_e32 v2, -1, v0
-; GFX10-NEXT: v_min_i32_e32 v3, -1, v0
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 0x7fffffff, v2
-; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 0x80000000, v3
-; GFX10-NEXT: v_max_i32_e32 v1, v2, v1
-; GFX10-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1
+; GFX10-NEXT: v_sub_nc_i32 v0, v0, v1 clamp
; GFX10-NEXT: v_ashrrev_i32_e32 v0, 8, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs)
@@ -1439,39 +1045,22 @@ define amdgpu_ps i24 @s_ssubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
;
; GFX9-LABEL: s_ssubsat_i24:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshl_b32 s0, s0, 8
; GFX9-NEXT: s_lshl_b32 s1, s1, 8
-; GFX9-NEXT: s_cmp_gt_i32 s0, -1
-; GFX9-NEXT: s_cselect_b32 s2, s0, -1
-; GFX9-NEXT: s_sub_i32 s2, s2, 0x7fffffff
-; GFX9-NEXT: s_cmp_lt_i32 s0, -1
-; GFX9-NEXT: s_cselect_b32 s3, s0, -1
-; GFX9-NEXT: s_sub_i32 s3, s3, 0x80000000
-; GFX9-NEXT: s_cmp_gt_i32 s2, s1
-; GFX9-NEXT: s_cselect_b32 s1, s2, s1
-; GFX9-NEXT: s_cmp_lt_i32 s1, s3
-; GFX9-NEXT: s_cselect_b32 s1, s1, s3
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
-; GFX9-NEXT: s_ashr_i32 s0, s0, 8
+; GFX9-NEXT: s_lshl_b32 s0, s0, 8
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
+; GFX9-NEXT: v_ashrrev_i32_e32 v0, 8, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshl_b32 s0, s0, 8
; GFX10-NEXT: s_lshl_b32 s1, s1, 8
-; GFX10-NEXT: s_cmp_gt_i32 s0, -1
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s2, s0, -1
-; GFX10-NEXT: s_sub_i32 s2, s2, 0x7fffffff
-; GFX10-NEXT: s_cmp_lt_i32 s0, -1
-; GFX10-NEXT: s_cselect_b32 s3, s0, -1
-; GFX10-NEXT: s_sub_i32 s3, s3, 0x80000000
-; GFX10-NEXT: s_cmp_gt_i32 s2, s1
-; GFX10-NEXT: s_cselect_b32 s1, s2, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s3
-; GFX10-NEXT: s_cselect_b32 s1, s1, s3
-; GFX10-NEXT: s_sub_i32 s0, s0, s1
-; GFX10-NEXT: s_ashr_i32 s0, s0, 8
+; GFX10-NEXT: v_sub_nc_i32 v0, s0, s1 clamp
+; GFX10-NEXT: v_ashrrev_i32_e32 v0, 8, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result
@@ -1505,27 +1094,15 @@ define i32 @v_ssubsat_i32(i32 %lhs, i32 %rhs) {
; GFX9-LABEL: v_ssubsat_i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_max_i32_e32 v2, -1, v0
-; GFX9-NEXT: v_min_i32_e32 v3, -1, v0
-; GFX9-NEXT: v_subrev_u32_e32 v2, 0x7fffffff, v2
-; GFX9-NEXT: v_subrev_u32_e32 v3, 0x80000000, v3
-; GFX9-NEXT: v_max_i32_e32 v1, v2, v1
-; GFX9-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_sub_i32 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_max_i32_e32 v2, -1, v0
-; GFX10-NEXT: v_min_i32_e32 v3, -1, v0
+; GFX10-NEXT: v_sub_nc_i32 v0, v0, v1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 0x7fffffff, v2
-; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 0x80000000, v3
-; GFX10-NEXT: v_max_i32_e32 v1, v2, v1
-; GFX10-NEXT: v_min_i32_e32 v1, v1, v3
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
@@ -1564,33 +1141,16 @@ define amdgpu_ps i32 @s_ssubsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
;
; GFX9-LABEL: s_ssubsat_i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_gt_i32 s0, -1
-; GFX9-NEXT: s_cselect_b32 s2, s0, -1
-; GFX9-NEXT: s_sub_i32 s2, s2, 0x7fffffff
-; GFX9-NEXT: s_cmp_lt_i32 s0, -1
-; GFX9-NEXT: s_cselect_b32 s3, s0, -1
-; GFX9-NEXT: s_sub_i32 s3, s3, 0x80000000
-; GFX9-NEXT: s_cmp_gt_i32 s2, s1
-; GFX9-NEXT: s_cselect_b32 s1, s2, s1
-; GFX9-NEXT: s_cmp_lt_i32 s1, s3
-; GFX9-NEXT: s_cselect_b32 s1, s1, s3
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_gt_i32 s0, -1
+; GFX10-NEXT: v_sub_nc_i32 v0, s0, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s2, s0, -1
-; GFX10-NEXT: s_sub_i32 s2, s2, 0x7fffffff
-; GFX10-NEXT: s_cmp_lt_i32 s0, -1
-; GFX10-NEXT: s_cselect_b32 s3, s0, -1
-; GFX10-NEXT: s_sub_i32 s3, s3, 0x80000000
-; GFX10-NEXT: s_cmp_gt_i32 s2, s1
-; GFX10-NEXT: s_cselect_b32 s1, s2, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s3
-; GFX10-NEXT: s_cselect_b32 s1, s1, s3
-; GFX10-NEXT: s_sub_i32 s0, s0, s1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
@@ -1625,29 +1185,13 @@ define amdgpu_ps float @ssubsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
;
; GFX9-LABEL: ssubsat_i32_sv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_gt_i32 s0, -1
-; GFX9-NEXT: s_cselect_b32 s1, s0, -1
-; GFX9-NEXT: s_sub_i32 s1, s1, 0x7fffffff
-; GFX9-NEXT: s_cmp_lt_i32 s0, -1
-; GFX9-NEXT: s_cselect_b32 s2, s0, -1
-; GFX9-NEXT: s_sub_i32 s2, s2, 0x80000000
-; GFX9-NEXT: v_max_i32_e32 v0, s1, v0
-; GFX9-NEXT: v_min_i32_e32 v0, s2, v0
-; GFX9-NEXT: v_sub_u32_e32 v0, s0, v0
+; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i32_sv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_gt_i32 s0, -1
+; GFX10-NEXT: v_sub_nc_i32 v0, s0, v0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s1, s0, -1
-; GFX10-NEXT: s_sub_i32 s1, s1, 0x7fffffff
-; GFX10-NEXT: s_cmp_lt_i32 s0, -1
-; GFX10-NEXT: v_max_i32_e32 v0, s1, v0
-; GFX10-NEXT: s_cselect_b32 s1, s0, -1
-; GFX10-NEXT: s_sub_i32 s1, s1, 0x80000000
-; GFX10-NEXT: v_min_i32_e32 v0, s1, v0
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
@@ -1679,25 +1223,13 @@ define amdgpu_ps float @ssubsat_i32_vs(i32 %lhs, i32 inreg %rhs) {
;
; GFX9-LABEL: ssubsat_i32_vs:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_max_i32_e32 v1, -1, v0
-; GFX9-NEXT: v_subrev_u32_e32 v1, 0x7fffffff, v1
-; GFX9-NEXT: v_min_i32_e32 v2, -1, v0
-; GFX9-NEXT: v_subrev_u32_e32 v2, 0x80000000, v2
-; GFX9-NEXT: v_max_i32_e32 v1, s0, v1
-; GFX9-NEXT: v_min_i32_e32 v1, v1, v2
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_sub_i32 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i32_vs:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_max_i32_e32 v1, -1, v0
-; GFX10-NEXT: v_min_i32_e32 v2, -1, v0
+; GFX10-NEXT: v_sub_nc_i32 v0, v0, s0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_subrev_nc_u32_e32 v1, 0x7fffffff, v1
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 0x80000000, v2
-; GFX10-NEXT: v_max_i32_e32 v1, s0, v1
-; GFX10-NEXT: v_min_i32_e32 v1, v1, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
@@ -1750,45 +1282,17 @@ define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX9-LABEL: v_ssubsat_v2i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: v_max_i32_e32 v4, -1, v0
-; GFX9-NEXT: v_subrev_u32_e32 v4, s4, v4
-; GFX9-NEXT: s_brev_b32 s5, 1
-; GFX9-NEXT: v_min_i32_e32 v5, -1, v0
-; GFX9-NEXT: v_max_i32_e32 v2, v4, v2
-; GFX9-NEXT: v_subrev_u32_e32 v5, s5, v5
-; GFX9-NEXT: v_min_i32_e32 v2, v2, v5
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v2
-; GFX9-NEXT: v_max_i32_e32 v2, -1, v1
-; GFX9-NEXT: v_subrev_u32_e32 v2, s4, v2
-; GFX9-NEXT: v_min_i32_e32 v4, -1, v1
-; GFX9-NEXT: v_subrev_u32_e32 v4, s5, v4
-; GFX9-NEXT: v_max_i32_e32 v2, v2, v3
-; GFX9-NEXT: v_min_i32_e32 v2, v2, v4
-; GFX9-NEXT: v_sub_u32_e32 v1, v1, v2
+; GFX9-NEXT: v_sub_i32 v0, v0, v2 clamp
+; GFX9-NEXT: v_sub_i32 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v2i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_max_i32_e32 v4, -1, v0
-; GFX10-NEXT: v_max_i32_e32 v5, -1, v1
-; GFX10-NEXT: s_brev_b32 s4, -2
-; GFX10-NEXT: v_min_i32_e32 v6, -1, v0
-; GFX10-NEXT: v_min_i32_e32 v7, -1, v1
-; GFX10-NEXT: v_subrev_nc_u32_e32 v4, s4, v4
-; GFX10-NEXT: v_subrev_nc_u32_e32 v5, s4, v5
-; GFX10-NEXT: s_brev_b32 s4, 1
+; GFX10-NEXT: v_sub_nc_i32 v0, v0, v2 clamp
+; GFX10-NEXT: v_sub_nc_i32 v1, v1, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s4, v6
-; GFX10-NEXT: v_max_i32_e32 v11, v4, v2
-; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s4, v7
-; GFX10-NEXT: v_max_i32_e32 v10, v5, v3
-; GFX10-NEXT: v_min_i32_e32 v2, v11, v6
-; GFX10-NEXT: v_min_i32_e32 v3, v10, v7
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
@@ -1853,59 +1357,21 @@ define amdgpu_ps <2 x i32> @s_ssubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inre
;
; GFX9-LABEL: s_ssubsat_v2i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_gt_i32 s0, -1
-; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: s_cselect_b32 s6, s0, -1
-; GFX9-NEXT: s_sub_i32 s6, s6, s4
-; GFX9-NEXT: s_cmp_lt_i32 s0, -1
-; GFX9-NEXT: s_brev_b32 s5, 1
-; GFX9-NEXT: s_cselect_b32 s7, s0, -1
-; GFX9-NEXT: s_sub_i32 s7, s7, s5
-; GFX9-NEXT: s_cmp_gt_i32 s6, s2
-; GFX9-NEXT: s_cselect_b32 s2, s6, s2
-; GFX9-NEXT: s_cmp_lt_i32 s2, s7
-; GFX9-NEXT: s_cselect_b32 s2, s2, s7
-; GFX9-NEXT: s_sub_i32 s0, s0, s2
-; GFX9-NEXT: s_cmp_gt_i32 s1, -1
-; GFX9-NEXT: s_cselect_b32 s2, s1, -1
-; GFX9-NEXT: s_sub_i32 s2, s2, s4
-; GFX9-NEXT: s_cmp_lt_i32 s1, -1
-; GFX9-NEXT: s_cselect_b32 s4, s1, -1
-; GFX9-NEXT: s_sub_i32 s4, s4, s5
-; GFX9-NEXT: s_cmp_gt_i32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s2, s3
-; GFX9-NEXT: s_cmp_lt_i32 s2, s4
-; GFX9-NEXT: s_cselect_b32 s2, s2, s4
-; GFX9-NEXT: s_sub_i32 s1, s1, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
+; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v2i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_gt_i32 s0, -1
-; GFX10-NEXT: s_brev_b32 s4, -2
-; GFX10-NEXT: s_cselect_b32 s5, s0, -1
-; GFX10-NEXT: s_brev_b32 s6, 1
-; GFX10-NEXT: s_sub_i32 s5, s5, s4
-; GFX10-NEXT: s_cmp_lt_i32 s0, -1
+; GFX10-NEXT: v_sub_nc_i32 v0, s0, s2 clamp
+; GFX10-NEXT: v_sub_nc_i32 v1, s1, s3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s7, s0, -1
-; GFX10-NEXT: s_sub_i32 s7, s7, s6
-; GFX10-NEXT: s_cmp_gt_i32 s5, s2
-; GFX10-NEXT: s_cselect_b32 s2, s5, s2
-; GFX10-NEXT: s_cmp_lt_i32 s2, s7
-; GFX10-NEXT: s_cselect_b32 s2, s2, s7
-; GFX10-NEXT: s_sub_i32 s0, s0, s2
-; GFX10-NEXT: s_cmp_gt_i32 s1, -1
-; GFX10-NEXT: s_cselect_b32 s2, s1, -1
-; GFX10-NEXT: s_sub_i32 s2, s2, s4
-; GFX10-NEXT: s_cmp_lt_i32 s1, -1
-; GFX10-NEXT: s_cselect_b32 s4, s1, -1
-; GFX10-NEXT: s_sub_i32 s4, s4, s6
-; GFX10-NEXT: s_cmp_gt_i32 s2, s3
-; GFX10-NEXT: s_cselect_b32 s2, s2, s3
-; GFX10-NEXT: s_cmp_lt_i32 s2, s4
-; GFX10-NEXT: s_cselect_b32 s2, s2, s4
-; GFX10-NEXT: s_sub_i32 s1, s1, s2
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
@@ -1971,59 +1437,19 @@ define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX9-LABEL: v_ssubsat_v3i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: v_max_i32_e32 v6, -1, v0
-; GFX9-NEXT: v_subrev_u32_e32 v6, s4, v6
-; GFX9-NEXT: s_brev_b32 s5, 1
-; GFX9-NEXT: v_min_i32_e32 v7, -1, v0
-; GFX9-NEXT: v_max_i32_e32 v3, v6, v3
-; GFX9-NEXT: v_subrev_u32_e32 v7, s5, v7
-; GFX9-NEXT: v_min_i32_e32 v3, v3, v7
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3
-; GFX9-NEXT: v_max_i32_e32 v3, -1, v1
-; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v3
-; GFX9-NEXT: v_min_i32_e32 v6, -1, v1
-; GFX9-NEXT: v_max_i32_e32 v3, v3, v4
-; GFX9-NEXT: v_subrev_u32_e32 v6, s5, v6
-; GFX9-NEXT: v_min_i32_e32 v3, v3, v6
-; GFX9-NEXT: v_sub_u32_e32 v1, v1, v3
-; GFX9-NEXT: v_max_i32_e32 v3, -1, v2
-; GFX9-NEXT: v_subrev_u32_e32 v3, s4, v3
-; GFX9-NEXT: v_min_i32_e32 v4, -1, v2
-; GFX9-NEXT: v_subrev_u32_e32 v4, s5, v4
-; GFX9-NEXT: v_max_i32_e32 v3, v3, v5
-; GFX9-NEXT: v_min_i32_e32 v3, v3, v4
-; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3
+; GFX9-NEXT: v_sub_i32 v0, v0, v3 clamp
+; GFX9-NEXT: v_sub_i32 v1, v1, v4 clamp
+; GFX9-NEXT: v_sub_i32 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v3i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_max_i32_e32 v6, -1, v0
-; GFX10-NEXT: v_max_i32_e32 v8, -1, v1
-; GFX10-NEXT: v_max_i32_e32 v9, -1, v2
-; GFX10-NEXT: s_brev_b32 s4, -2
-; GFX10-NEXT: v_min_i32_e32 v7, -1, v0
-; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s4, v6
-; GFX10-NEXT: v_subrev_nc_u32_e32 v15, s4, v8
-; GFX10-NEXT: v_subrev_nc_u32_e32 v19, s4, v9
-; GFX10-NEXT: v_min_i32_e32 v10, -1, v1
-; GFX10-NEXT: v_min_i32_e32 v11, -1, v2
-; GFX10-NEXT: s_brev_b32 s5, 1
-; GFX10-NEXT: v_max_i32_e32 v14, v6, v3
-; GFX10-NEXT: v_subrev_nc_u32_e32 v7, s5, v7
-; GFX10-NEXT: v_subrev_nc_u32_e32 v6, s5, v10
-; GFX10-NEXT: v_max_i32_e32 v4, v15, v4
-; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s5, v11
-; GFX10-NEXT: v_max_i32_e32 v5, v19, v5
-; GFX10-NEXT: v_min_i32_e32 v3, v14, v7
+; GFX10-NEXT: v_sub_nc_i32 v0, v0, v3 clamp
+; GFX10-NEXT: v_sub_nc_i32 v1, v1, v4 clamp
+; GFX10-NEXT: v_sub_nc_i32 v2, v2, v5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_i32_e32 v4, v4, v6
-; GFX10-NEXT: v_min_i32_e32 v5, v5, v8
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v3
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v4
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
@@ -2110,81 +1536,26 @@ define amdgpu_ps <3 x i32> @s_ssubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inre
;
; GFX9-LABEL: s_ssubsat_v3i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_gt_i32 s0, -1
-; GFX9-NEXT: s_brev_b32 s6, -2
-; GFX9-NEXT: s_cselect_b32 s8, s0, -1
-; GFX9-NEXT: s_sub_i32 s8, s8, s6
-; GFX9-NEXT: s_cmp_lt_i32 s0, -1
-; GFX9-NEXT: s_brev_b32 s7, 1
-; GFX9-NEXT: s_cselect_b32 s9, s0, -1
-; GFX9-NEXT: s_sub_i32 s9, s9, s7
-; GFX9-NEXT: s_cmp_gt_i32 s8, s3
-; GFX9-NEXT: s_cselect_b32 s3, s8, s3
-; GFX9-NEXT: s_cmp_lt_i32 s3, s9
-; GFX9-NEXT: s_cselect_b32 s3, s3, s9
-; GFX9-NEXT: s_sub_i32 s0, s0, s3
-; GFX9-NEXT: s_cmp_gt_i32 s1, -1
-; GFX9-NEXT: s_cselect_b32 s3, s1, -1
-; GFX9-NEXT: s_sub_i32 s3, s3, s6
-; GFX9-NEXT: s_cmp_lt_i32 s1, -1
-; GFX9-NEXT: s_cselect_b32 s8, s1, -1
-; GFX9-NEXT: s_sub_i32 s8, s8, s7
-; GFX9-NEXT: s_cmp_gt_i32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s3, s3, s4
-; GFX9-NEXT: s_cmp_lt_i32 s3, s8
-; GFX9-NEXT: s_cselect_b32 s3, s3, s8
-; GFX9-NEXT: s_sub_i32 s1, s1, s3
-; GFX9-NEXT: s_cmp_gt_i32 s2, -1
-; GFX9-NEXT: s_cselect_b32 s3, s2, -1
-; GFX9-NEXT: s_sub_i32 s3, s3, s6
-; GFX9-NEXT: s_cmp_lt_i32 s2, -1
-; GFX9-NEXT: s_cselect_b32 s4, s2, -1
-; GFX9-NEXT: s_sub_i32 s4, s4, s7
-; GFX9-NEXT: s_cmp_gt_i32 s3, s5
-; GFX9-NEXT: s_cselect_b32 s3, s3, s5
-; GFX9-NEXT: s_cmp_lt_i32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s3, s3, s4
-; GFX9-NEXT: s_sub_i32 s2, s2, s3
+; GFX9-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
+; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp
+; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v3i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_gt_i32 s0, -1
-; GFX10-NEXT: s_brev_b32 s6, -2
-; GFX10-NEXT: s_cselect_b32 s7, s0, -1
-; GFX10-NEXT: s_brev_b32 s8, 1
-; GFX10-NEXT: s_sub_i32 s7, s7, s6
-; GFX10-NEXT: s_cmp_lt_i32 s0, -1
+; GFX10-NEXT: v_sub_nc_i32 v0, s0, s3 clamp
+; GFX10-NEXT: v_sub_nc_i32 v1, s1, s4 clamp
+; GFX10-NEXT: v_sub_nc_i32 v2, s2, s5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s9, s0, -1
-; GFX10-NEXT: s_sub_i32 s9, s9, s8
-; GFX10-NEXT: s_cmp_gt_i32 s7, s3
-; GFX10-NEXT: s_cselect_b32 s3, s7, s3
-; GFX10-NEXT: s_cmp_lt_i32 s3, s9
-; GFX10-NEXT: s_cselect_b32 s3, s3, s9
-; GFX10-NEXT: s_sub_i32 s0, s0, s3
-; GFX10-NEXT: s_cmp_gt_i32 s1, -1
-; GFX10-NEXT: s_cselect_b32 s3, s1, -1
-; GFX10-NEXT: s_sub_i32 s3, s3, s6
-; GFX10-NEXT: s_cmp_lt_i32 s1, -1
-; GFX10-NEXT: s_cselect_b32 s7, s1, -1
-; GFX10-NEXT: s_sub_i32 s7, s7, s8
-; GFX10-NEXT: s_cmp_gt_i32 s3, s4
-; GFX10-NEXT: s_cselect_b32 s3, s3, s4
-; GFX10-NEXT: s_cmp_lt_i32 s3, s7
-; GFX10-NEXT: s_cselect_b32 s3, s3, s7
-; GFX10-NEXT: s_sub_i32 s1, s1, s3
-; GFX10-NEXT: s_cmp_gt_i32 s2, -1
-; GFX10-NEXT: s_cselect_b32 s3, s2, -1
-; GFX10-NEXT: s_sub_i32 s3, s3, s6
-; GFX10-NEXT: s_cmp_lt_i32 s2, -1
-; GFX10-NEXT: s_cselect_b32 s4, s2, -1
-; GFX10-NEXT: s_sub_i32 s4, s4, s8
-; GFX10-NEXT: s_cmp_gt_i32 s3, s5
-; GFX10-NEXT: s_cselect_b32 s3, s3, s5
-; GFX10-NEXT: s_cmp_lt_i32 s3, s4
-; GFX10-NEXT: s_cselect_b32 s3, s3, s4
-; GFX10-NEXT: s_sub_i32 s2, s2, s3
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: ; return to shader part epilog
%result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
@@ -2264,73 +1635,21 @@ define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX9-LABEL: v_ssubsat_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: v_max_i32_e32 v8, -1, v0
-; GFX9-NEXT: v_subrev_u32_e32 v8, s4, v8
-; GFX9-NEXT: s_brev_b32 s5, 1
-; GFX9-NEXT: v_min_i32_e32 v9, -1, v0
-; GFX9-NEXT: v_max_i32_e32 v4, v8, v4
-; GFX9-NEXT: v_subrev_u32_e32 v9, s5, v9
-; GFX9-NEXT: v_min_i32_e32 v4, v4, v9
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v4
-; GFX9-NEXT: v_max_i32_e32 v4, -1, v1
-; GFX9-NEXT: v_subrev_u32_e32 v4, s4, v4
-; GFX9-NEXT: v_min_i32_e32 v8, -1, v1
-; GFX9-NEXT: v_max_i32_e32 v4, v4, v5
-; GFX9-NEXT: v_subrev_u32_e32 v8, s5, v8
-; GFX9-NEXT: v_min_i32_e32 v4, v4, v8
-; GFX9-NEXT: v_sub_u32_e32 v1, v1, v4
-; GFX9-NEXT: v_max_i32_e32 v4, -1, v2
-; GFX9-NEXT: v_subrev_u32_e32 v4, s4, v4
-; GFX9-NEXT: v_min_i32_e32 v5, -1, v2
-; GFX9-NEXT: v_subrev_u32_e32 v5, s5, v5
-; GFX9-NEXT: v_max_i32_e32 v4, v4, v6
-; GFX9-NEXT: v_min_i32_e32 v4, v4, v5
-; GFX9-NEXT: v_sub_u32_e32 v2, v2, v4
-; GFX9-NEXT: v_max_i32_e32 v4, -1, v3
-; GFX9-NEXT: v_subrev_u32_e32 v4, 0x7fffffff, v4
-; GFX9-NEXT: v_min_i32_e32 v5, -1, v3
-; GFX9-NEXT: v_subrev_u32_e32 v5, 0x80000000, v5
-; GFX9-NEXT: v_max_i32_e32 v4, v4, v7
-; GFX9-NEXT: v_min_i32_e32 v4, v4, v5
-; GFX9-NEXT: v_sub_u32_e32 v3, v3, v4
+; GFX9-NEXT: v_sub_i32 v0, v0, v4 clamp
+; GFX9-NEXT: v_sub_i32 v1, v1, v5 clamp
+; GFX9-NEXT: v_sub_i32 v2, v2, v6 clamp
+; GFX9-NEXT: v_sub_i32 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v4i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_max_i32_e32 v8, -1, v0
-; GFX10-NEXT: s_brev_b32 s4, -2
-; GFX10-NEXT: v_max_i32_e32 v10, -1, v1
-; GFX10-NEXT: v_max_i32_e32 v12, -1, v3
-; GFX10-NEXT: v_min_i32_e32 v9, -1, v0
-; GFX10-NEXT: v_subrev_nc_u32_e32 v15, s4, v8
-; GFX10-NEXT: v_max_i32_e32 v8, -1, v2
-; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s4, v10
-; GFX10-NEXT: v_subrev_nc_u32_e32 v12, 0x7fffffff, v12
-; GFX10-NEXT: v_min_i32_e32 v11, -1, v1
-; GFX10-NEXT: v_min_i32_e32 v13, -1, v2
-; GFX10-NEXT: v_subrev_nc_u32_e32 v8, s4, v8
-; GFX10-NEXT: v_min_i32_e32 v14, -1, v3
-; GFX10-NEXT: s_brev_b32 s5, 1
-; GFX10-NEXT: v_max_i32_e32 v4, v15, v4
-; GFX10-NEXT: v_subrev_nc_u32_e32 v9, s5, v9
-; GFX10-NEXT: v_max_i32_e32 v5, v10, v5
-; GFX10-NEXT: v_subrev_nc_u32_e32 v11, s5, v11
-; GFX10-NEXT: v_max_i32_e32 v15, v8, v6
-; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s5, v13
-; GFX10-NEXT: v_subrev_nc_u32_e32 v8, 0x80000000, v14
-; GFX10-NEXT: v_max_i32_e32 v7, v12, v7
-; GFX10-NEXT: v_min_i32_e32 v19, v4, v9
-; GFX10-NEXT: v_min_i32_e32 v11, v5, v11
-; GFX10-NEXT: v_min_i32_e32 v15, v15, v10
+; GFX10-NEXT: v_sub_nc_i32 v0, v0, v4 clamp
+; GFX10-NEXT: v_sub_nc_i32 v1, v1, v5 clamp
+; GFX10-NEXT: v_sub_nc_i32 v2, v2, v6 clamp
+; GFX10-NEXT: v_sub_nc_i32 v3, v3, v7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_i32_e32 v6, v7, v8
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v19
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v11
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v15
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, v3, v6
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
@@ -2439,103 +1758,31 @@ define amdgpu_ps <4 x i32> @s_ssubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inre
;
; GFX9-LABEL: s_ssubsat_v4i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_gt_i32 s0, -1
-; GFX9-NEXT: s_brev_b32 s8, -2
-; GFX9-NEXT: s_cselect_b32 s10, s0, -1
-; GFX9-NEXT: s_sub_i32 s10, s10, s8
-; GFX9-NEXT: s_cmp_lt_i32 s0, -1
-; GFX9-NEXT: s_brev_b32 s9, 1
-; GFX9-NEXT: s_cselect_b32 s11, s0, -1
-; GFX9-NEXT: s_sub_i32 s11, s11, s9
-; GFX9-NEXT: s_cmp_gt_i32 s10, s4
-; GFX9-NEXT: s_cselect_b32 s4, s10, s4
-; GFX9-NEXT: s_cmp_lt_i32 s4, s11
-; GFX9-NEXT: s_cselect_b32 s4, s4, s11
-; GFX9-NEXT: s_sub_i32 s0, s0, s4
-; GFX9-NEXT: s_cmp_gt_i32 s1, -1
-; GFX9-NEXT: s_cselect_b32 s4, s1, -1
-; GFX9-NEXT: s_sub_i32 s4, s4, s8
-; GFX9-NEXT: s_cmp_lt_i32 s1, -1
-; GFX9-NEXT: s_cselect_b32 s10, s1, -1
-; GFX9-NEXT: s_sub_i32 s10, s10, s9
-; GFX9-NEXT: s_cmp_gt_i32 s4, s5
-; GFX9-NEXT: s_cselect_b32 s4, s4, s5
-; GFX9-NEXT: s_cmp_lt_i32 s4, s10
-; GFX9-NEXT: s_cselect_b32 s4, s4, s10
-; GFX9-NEXT: s_sub_i32 s1, s1, s4
-; GFX9-NEXT: s_cmp_gt_i32 s2, -1
-; GFX9-NEXT: s_cselect_b32 s4, s2, -1
-; GFX9-NEXT: s_sub_i32 s4, s4, s8
-; GFX9-NEXT: s_cmp_lt_i32 s2, -1
-; GFX9-NEXT: s_cselect_b32 s5, s2, -1
-; GFX9-NEXT: s_sub_i32 s5, s5, s9
-; GFX9-NEXT: s_cmp_gt_i32 s4, s6
-; GFX9-NEXT: s_cselect_b32 s4, s4, s6
-; GFX9-NEXT: s_cmp_lt_i32 s4, s5
-; GFX9-NEXT: s_cselect_b32 s4, s4, s5
-; GFX9-NEXT: s_sub_i32 s2, s2, s4
-; GFX9-NEXT: s_cmp_gt_i32 s3, -1
-; GFX9-NEXT: s_cselect_b32 s4, s3, -1
-; GFX9-NEXT: s_sub_i32 s4, s4, s8
-; GFX9-NEXT: s_cmp_lt_i32 s3, -1
-; GFX9-NEXT: s_cselect_b32 s5, s3, -1
-; GFX9-NEXT: s_sub_i32 s5, s5, s9
-; GFX9-NEXT: s_cmp_gt_i32 s4, s7
-; GFX9-NEXT: s_cselect_b32 s4, s4, s7
-; GFX9-NEXT: s_cmp_lt_i32 s4, s5
-; GFX9-NEXT: s_cselect_b32 s4, s4, s5
-; GFX9-NEXT: s_sub_i32 s3, s3, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
+; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp
+; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp
+; GFX9-NEXT: v_sub_i32 v3, s3, v3 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v4i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_gt_i32 s0, -1
-; GFX10-NEXT: s_brev_b32 s8, -2
-; GFX10-NEXT: s_cselect_b32 s9, s0, -1
-; GFX10-NEXT: s_brev_b32 s10, 1
-; GFX10-NEXT: s_sub_i32 s9, s9, s8
-; GFX10-NEXT: s_cmp_lt_i32 s0, -1
+; GFX10-NEXT: v_sub_nc_i32 v0, s0, s4 clamp
+; GFX10-NEXT: v_sub_nc_i32 v1, s1, s5 clamp
+; GFX10-NEXT: v_sub_nc_i32 v2, s2, s6 clamp
+; GFX10-NEXT: v_sub_nc_i32 v3, s3, s7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s11, s0, -1
-; GFX10-NEXT: s_sub_i32 s11, s11, s10
-; GFX10-NEXT: s_cmp_gt_i32 s9, s4
-; GFX10-NEXT: s_cselect_b32 s4, s9, s4
-; GFX10-NEXT: s_cmp_lt_i32 s4, s11
-; GFX10-NEXT: s_cselect_b32 s4, s4, s11
-; GFX10-NEXT: s_sub_i32 s0, s0, s4
-; GFX10-NEXT: s_cmp_gt_i32 s1, -1
-; GFX10-NEXT: s_cselect_b32 s4, s1, -1
-; GFX10-NEXT: s_sub_i32 s4, s4, s8
-; GFX10-NEXT: s_cmp_lt_i32 s1, -1
-; GFX10-NEXT: s_cselect_b32 s9, s1, -1
-; GFX10-NEXT: s_sub_i32 s9, s9, s10
-; GFX10-NEXT: s_cmp_gt_i32 s4, s5
-; GFX10-NEXT: s_cselect_b32 s4, s4, s5
-; GFX10-NEXT: s_cmp_lt_i32 s4, s9
-; GFX10-NEXT: s_cselect_b32 s4, s4, s9
-; GFX10-NEXT: s_sub_i32 s1, s1, s4
-; GFX10-NEXT: s_cmp_gt_i32 s2, -1
-; GFX10-NEXT: s_cselect_b32 s4, s2, -1
-; GFX10-NEXT: s_sub_i32 s4, s4, s8
-; GFX10-NEXT: s_cmp_lt_i32 s2, -1
-; GFX10-NEXT: s_cselect_b32 s5, s2, -1
-; GFX10-NEXT: s_sub_i32 s5, s5, s10
-; GFX10-NEXT: s_cmp_gt_i32 s4, s6
-; GFX10-NEXT: s_cselect_b32 s4, s4, s6
-; GFX10-NEXT: s_cmp_lt_i32 s4, s5
-; GFX10-NEXT: s_cselect_b32 s4, s4, s5
-; GFX10-NEXT: s_sub_i32 s2, s2, s4
-; GFX10-NEXT: s_cmp_gt_i32 s3, -1
-; GFX10-NEXT: s_cselect_b32 s4, s3, -1
-; GFX10-NEXT: s_sub_i32 s4, s4, s8
-; GFX10-NEXT: s_cmp_lt_i32 s3, -1
-; GFX10-NEXT: s_cselect_b32 s5, s3, -1
-; GFX10-NEXT: s_sub_i32 s5, s5, s10
-; GFX10-NEXT: s_cmp_gt_i32 s4, s7
-; GFX10-NEXT: s_cselect_b32 s4, s4, s7
-; GFX10-NEXT: s_cmp_lt_i32 s4, s5
-; GFX10-NEXT: s_cselect_b32 s4, s4, s5
-; GFX10-NEXT: s_sub_i32 s3, s3, s4
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: ; return to shader part epilog
%result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
@@ -2633,90 +1880,22 @@ define <5 x i32> @v_ssubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX9-LABEL: v_ssubsat_v5i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: v_max_i32_e32 v10, -1, v0
-; GFX9-NEXT: v_subrev_u32_e32 v10, s4, v10
-; GFX9-NEXT: s_brev_b32 s5, 1
-; GFX9-NEXT: v_min_i32_e32 v12, -1, v0
-; GFX9-NEXT: v_max_i32_e32 v5, v10, v5
-; GFX9-NEXT: v_subrev_u32_e32 v12, s5, v12
-; GFX9-NEXT: v_min_i32_e32 v5, v5, v12
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v5
-; GFX9-NEXT: v_max_i32_e32 v5, -1, v1
-; GFX9-NEXT: v_subrev_u32_e32 v5, s4, v5
-; GFX9-NEXT: v_min_i32_e32 v10, -1, v1
-; GFX9-NEXT: v_max_i32_e32 v5, v5, v6
-; GFX9-NEXT: v_subrev_u32_e32 v10, s5, v10
-; GFX9-NEXT: v_min_i32_e32 v5, v5, v10
-; GFX9-NEXT: v_sub_u32_e32 v1, v1, v5
-; GFX9-NEXT: v_max_i32_e32 v5, -1, v2
-; GFX9-NEXT: v_subrev_u32_e32 v5, s4, v5
-; GFX9-NEXT: v_min_i32_e32 v6, -1, v2
-; GFX9-NEXT: v_subrev_u32_e32 v6, s5, v6
-; GFX9-NEXT: v_max_i32_e32 v5, v5, v7
-; GFX9-NEXT: v_min_i32_e32 v5, v5, v6
-; GFX9-NEXT: v_sub_u32_e32 v2, v2, v5
-; GFX9-NEXT: v_bfrev_b32_e32 v11, -2
-; GFX9-NEXT: v_max_i32_e32 v5, -1, v3
-; GFX9-NEXT: v_sub_u32_e32 v5, v5, v11
-; GFX9-NEXT: v_bfrev_b32_e32 v13, 1
-; GFX9-NEXT: v_min_i32_e32 v6, -1, v3
-; GFX9-NEXT: v_sub_u32_e32 v6, v6, v13
-; GFX9-NEXT: v_max_i32_e32 v5, v5, v8
-; GFX9-NEXT: v_min_i32_e32 v5, v5, v6
-; GFX9-NEXT: v_sub_u32_e32 v3, v3, v5
-; GFX9-NEXT: v_max_i32_e32 v5, -1, v4
-; GFX9-NEXT: v_sub_u32_e32 v5, v5, v11
-; GFX9-NEXT: v_min_i32_e32 v6, -1, v4
-; GFX9-NEXT: v_sub_u32_e32 v6, v6, v13
-; GFX9-NEXT: v_max_i32_e32 v5, v5, v9
-; GFX9-NEXT: v_min_i32_e32 v5, v5, v6
-; GFX9-NEXT: v_sub_u32_e32 v4, v4, v5
+; GFX9-NEXT: v_sub_i32 v0, v0, v5 clamp
+; GFX9-NEXT: v_sub_i32 v1, v1, v6 clamp
+; GFX9-NEXT: v_sub_i32 v2, v2, v7 clamp
+; GFX9-NEXT: v_sub_i32 v3, v3, v8 clamp
+; GFX9-NEXT: v_sub_i32 v4, v4, v9 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v5i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_max_i32_e32 v10, -1, v0
-; GFX10-NEXT: v_max_i32_e32 v13, -1, v1
-; GFX10-NEXT: s_brev_b32 s4, -2
-; GFX10-NEXT: v_bfrev_b32_e32 v11, -2
-; GFX10-NEXT: v_max_i32_e32 v17, -1, v4
-; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s4, v10
-; GFX10-NEXT: v_subrev_nc_u32_e32 v13, s4, v13
-; GFX10-NEXT: v_min_i32_e32 v12, -1, v0
-; GFX10-NEXT: v_bfrev_b32_e32 v14, 1
-; GFX10-NEXT: v_min_i32_e32 v15, -1, v1
-; GFX10-NEXT: v_max_i32_e32 v5, v10, v5
-; GFX10-NEXT: v_max_i32_e32 v10, -1, v2
-; GFX10-NEXT: v_max_i32_e32 v6, v13, v6
-; GFX10-NEXT: v_max_i32_e32 v13, -1, v3
-; GFX10-NEXT: v_min_i32_e32 v16, -1, v2
-; GFX10-NEXT: v_min_i32_e32 v23, -1, v3
-; GFX10-NEXT: v_subrev_nc_u32_e32 v10, s4, v10
-; GFX10-NEXT: v_min_i32_e32 v19, -1, v4
-; GFX10-NEXT: v_sub_nc_u32_e32 v13, v13, v11
-; GFX10-NEXT: v_sub_nc_u32_e32 v11, v17, v11
-; GFX10-NEXT: s_brev_b32 s5, 1
-; GFX10-NEXT: v_max_i32_e32 v7, v10, v7
-; GFX10-NEXT: v_subrev_nc_u32_e32 v12, s5, v12
-; GFX10-NEXT: v_subrev_nc_u32_e32 v15, s5, v15
-; GFX10-NEXT: v_subrev_nc_u32_e32 v16, s5, v16
-; GFX10-NEXT: v_max_i32_e32 v8, v13, v8
-; GFX10-NEXT: v_sub_nc_u32_e32 v10, v23, v14
-; GFX10-NEXT: v_sub_nc_u32_e32 v13, v19, v14
-; GFX10-NEXT: v_max_i32_e32 v11, v11, v9
-; GFX10-NEXT: v_min_i32_e32 v5, v5, v12
-; GFX10-NEXT: v_min_i32_e32 v6, v6, v15
-; GFX10-NEXT: v_min_i32_e32 v7, v7, v16
-; GFX10-NEXT: v_min_i32_e32 v8, v8, v10
-; GFX10-NEXT: v_min_i32_e32 v9, v11, v13
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v5
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v6
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v7
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, v3, v8
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v9
+; GFX10-NEXT: v_sub_nc_i32 v0, v0, v5 clamp
+; GFX10-NEXT: v_sub_nc_i32 v1, v1, v6 clamp
+; GFX10-NEXT: v_sub_nc_i32 v2, v2, v7 clamp
+; GFX10-NEXT: v_sub_nc_i32 v3, v3, v8 clamp
+; GFX10-NEXT: v_sub_nc_i32 v4, v4, v9 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
@@ -2848,125 +2027,36 @@ define amdgpu_ps <5 x i32> @s_ssubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inre
;
; GFX9-LABEL: s_ssubsat_v5i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_gt_i32 s0, -1
-; GFX9-NEXT: s_brev_b32 s10, -2
-; GFX9-NEXT: s_cselect_b32 s12, s0, -1
-; GFX9-NEXT: s_sub_i32 s12, s12, s10
-; GFX9-NEXT: s_cmp_lt_i32 s0, -1
-; GFX9-NEXT: s_brev_b32 s11, 1
-; GFX9-NEXT: s_cselect_b32 s13, s0, -1
-; GFX9-NEXT: s_sub_i32 s13, s13, s11
-; GFX9-NEXT: s_cmp_gt_i32 s12, s5
-; GFX9-NEXT: s_cselect_b32 s5, s12, s5
-; GFX9-NEXT: s_cmp_lt_i32 s5, s13
-; GFX9-NEXT: s_cselect_b32 s5, s5, s13
-; GFX9-NEXT: s_sub_i32 s0, s0, s5
-; GFX9-NEXT: s_cmp_gt_i32 s1, -1
-; GFX9-NEXT: s_cselect_b32 s5, s1, -1
-; GFX9-NEXT: s_sub_i32 s5, s5, s10
-; GFX9-NEXT: s_cmp_lt_i32 s1, -1
-; GFX9-NEXT: s_cselect_b32 s12, s1, -1
-; GFX9-NEXT: s_sub_i32 s12, s12, s11
-; GFX9-NEXT: s_cmp_gt_i32 s5, s6
-; GFX9-NEXT: s_cselect_b32 s5, s5, s6
-; GFX9-NEXT: s_cmp_lt_i32 s5, s12
-; GFX9-NEXT: s_cselect_b32 s5, s5, s12
-; GFX9-NEXT: s_sub_i32 s1, s1, s5
-; GFX9-NEXT: s_cmp_gt_i32 s2, -1
-; GFX9-NEXT: s_cselect_b32 s5, s2, -1
-; GFX9-NEXT: s_sub_i32 s5, s5, s10
-; GFX9-NEXT: s_cmp_lt_i32 s2, -1
-; GFX9-NEXT: s_cselect_b32 s6, s2, -1
-; GFX9-NEXT: s_sub_i32 s6, s6, s11
-; GFX9-NEXT: s_cmp_gt_i32 s5, s7
-; GFX9-NEXT: s_cselect_b32 s5, s5, s7
-; GFX9-NEXT: s_cmp_lt_i32 s5, s6
-; GFX9-NEXT: s_cselect_b32 s5, s5, s6
-; GFX9-NEXT: s_sub_i32 s2, s2, s5
-; GFX9-NEXT: s_cmp_gt_i32 s3, -1
-; GFX9-NEXT: s_cselect_b32 s5, s3, -1
-; GFX9-NEXT: s_sub_i32 s5, s5, s10
-; GFX9-NEXT: s_cmp_lt_i32 s3, -1
-; GFX9-NEXT: s_cselect_b32 s6, s3, -1
-; GFX9-NEXT: s_sub_i32 s6, s6, s11
-; GFX9-NEXT: s_cmp_gt_i32 s5, s8
-; GFX9-NEXT: s_cselect_b32 s5, s5, s8
-; GFX9-NEXT: s_cmp_lt_i32 s5, s6
-; GFX9-NEXT: s_cselect_b32 s5, s5, s6
-; GFX9-NEXT: s_sub_i32 s3, s3, s5
-; GFX9-NEXT: s_cmp_gt_i32 s4, -1
-; GFX9-NEXT: s_cselect_b32 s5, s4, -1
-; GFX9-NEXT: s_sub_i32 s5, s5, s10
-; GFX9-NEXT: s_cmp_lt_i32 s4, -1
-; GFX9-NEXT: s_cselect_b32 s6, s4, -1
-; GFX9-NEXT: s_sub_i32 s6, s6, s11
-; GFX9-NEXT: s_cmp_gt_i32 s5, s9
-; GFX9-NEXT: s_cselect_b32 s5, s5, s9
-; GFX9-NEXT: s_cmp_lt_i32 s5, s6
-; GFX9-NEXT: s_cselect_b32 s5, s5, s6
-; GFX9-NEXT: s_sub_i32 s4, s4, s5
+; GFX9-NEXT: v_mov_b32_e32 v0, s5
+; GFX9-NEXT: v_mov_b32_e32 v1, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s7
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
+; GFX9-NEXT: v_mov_b32_e32 v4, s9
+; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
+; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp
+; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp
+; GFX9-NEXT: v_sub_i32 v3, s3, v3 clamp
+; GFX9-NEXT: v_sub_i32 v4, s4, v4 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
+; GFX9-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v5i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_gt_i32 s0, -1
-; GFX10-NEXT: s_brev_b32 s10, -2
-; GFX10-NEXT: s_cselect_b32 s11, s0, -1
-; GFX10-NEXT: s_brev_b32 s12, 1
-; GFX10-NEXT: s_sub_i32 s11, s11, s10
-; GFX10-NEXT: s_cmp_lt_i32 s0, -1
+; GFX10-NEXT: v_sub_nc_i32 v0, s0, s5 clamp
+; GFX10-NEXT: v_sub_nc_i32 v1, s1, s6 clamp
+; GFX10-NEXT: v_sub_nc_i32 v2, s2, s7 clamp
+; GFX10-NEXT: v_sub_nc_i32 v3, s3, s8 clamp
+; GFX10-NEXT: v_sub_nc_i32 v4, s4, s9 clamp
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10-NEXT: v_readfirstlane_b32 s4, v4
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s13, s0, -1
-; GFX10-NEXT: s_sub_i32 s13, s13, s12
-; GFX10-NEXT: s_cmp_gt_i32 s11, s5
-; GFX10-NEXT: s_cselect_b32 s5, s11, s5
-; GFX10-NEXT: s_cmp_lt_i32 s5, s13
-; GFX10-NEXT: s_cselect_b32 s5, s5, s13
-; GFX10-NEXT: s_sub_i32 s0, s0, s5
-; GFX10-NEXT: s_cmp_gt_i32 s1, -1
-; GFX10-NEXT: s_cselect_b32 s5, s1, -1
-; GFX10-NEXT: s_sub_i32 s5, s5, s10
-; GFX10-NEXT: s_cmp_lt_i32 s1, -1
-; GFX10-NEXT: s_cselect_b32 s11, s1, -1
-; GFX10-NEXT: s_sub_i32 s11, s11, s12
-; GFX10-NEXT: s_cmp_gt_i32 s5, s6
-; GFX10-NEXT: s_cselect_b32 s5, s5, s6
-; GFX10-NEXT: s_cmp_lt_i32 s5, s11
-; GFX10-NEXT: s_cselect_b32 s5, s5, s11
-; GFX10-NEXT: s_sub_i32 s1, s1, s5
-; GFX10-NEXT: s_cmp_gt_i32 s2, -1
-; GFX10-NEXT: s_cselect_b32 s5, s2, -1
-; GFX10-NEXT: s_sub_i32 s5, s5, s10
-; GFX10-NEXT: s_cmp_lt_i32 s2, -1
-; GFX10-NEXT: s_cselect_b32 s6, s2, -1
-; GFX10-NEXT: s_sub_i32 s6, s6, s12
-; GFX10-NEXT: s_cmp_gt_i32 s5, s7
-; GFX10-NEXT: s_cselect_b32 s5, s5, s7
-; GFX10-NEXT: s_cmp_lt_i32 s5, s6
-; GFX10-NEXT: s_cselect_b32 s5, s5, s6
-; GFX10-NEXT: s_sub_i32 s2, s2, s5
-; GFX10-NEXT: s_cmp_gt_i32 s3, -1
-; GFX10-NEXT: s_cselect_b32 s5, s3, -1
-; GFX10-NEXT: s_sub_i32 s5, s5, s10
-; GFX10-NEXT: s_cmp_lt_i32 s3, -1
-; GFX10-NEXT: s_cselect_b32 s6, s3, -1
-; GFX10-NEXT: s_sub_i32 s6, s6, s12
-; GFX10-NEXT: s_cmp_gt_i32 s5, s8
-; GFX10-NEXT: s_cselect_b32 s5, s5, s8
-; GFX10-NEXT: s_cmp_lt_i32 s5, s6
-; GFX10-NEXT: s_cselect_b32 s5, s5, s6
-; GFX10-NEXT: s_sub_i32 s3, s3, s5
-; GFX10-NEXT: s_cmp_gt_i32 s4, -1
-; GFX10-NEXT: s_cselect_b32 s5, s4, -1
-; GFX10-NEXT: s_sub_i32 s5, s5, s10
-; GFX10-NEXT: s_cmp_lt_i32 s4, -1
-; GFX10-NEXT: s_cselect_b32 s6, s4, -1
-; GFX10-NEXT: s_sub_i32 s6, s6, s12
-; GFX10-NEXT: s_cmp_gt_i32 s5, s9
-; GFX10-NEXT: s_cselect_b32 s5, s5, s9
-; GFX10-NEXT: s_cmp_lt_i32 s5, s6
-; GFX10-NEXT: s_cselect_b32 s5, s5, s6
-; GFX10-NEXT: s_sub_i32 s4, s4, s5
; GFX10-NEXT: ; return to shader part epilog
%result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result
@@ -3218,244 +2308,44 @@ define <16 x i32> @v_ssubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
; GFX9-LABEL: v_ssubsat_v16i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_brev_b32 s4, -2
-; GFX9-NEXT: v_max_i32_e32 v32, -1, v0
-; GFX9-NEXT: v_subrev_u32_e32 v32, s4, v32
-; GFX9-NEXT: v_max_i32_e32 v16, v32, v16
-; GFX9-NEXT: s_brev_b32 s5, 1
-; GFX9-NEXT: v_min_i32_e32 v32, -1, v0
-; GFX9-NEXT: v_subrev_u32_e32 v32, s5, v32
-; GFX9-NEXT: v_min_i32_e32 v16, v16, v32
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v16
-; GFX9-NEXT: v_max_i32_e32 v16, -1, v1
-; GFX9-NEXT: v_subrev_u32_e32 v16, s4, v16
-; GFX9-NEXT: v_max_i32_e32 v16, v16, v17
-; GFX9-NEXT: v_min_i32_e32 v17, -1, v1
-; GFX9-NEXT: v_subrev_u32_e32 v17, s5, v17
-; GFX9-NEXT: v_min_i32_e32 v16, v16, v17
-; GFX9-NEXT: v_sub_u32_e32 v1, v1, v16
-; GFX9-NEXT: v_max_i32_e32 v16, -1, v2
-; GFX9-NEXT: v_subrev_u32_e32 v16, s4, v16
-; GFX9-NEXT: v_min_i32_e32 v17, -1, v2
-; GFX9-NEXT: v_max_i32_e32 v16, v16, v18
-; GFX9-NEXT: v_subrev_u32_e32 v17, s5, v17
-; GFX9-NEXT: v_min_i32_e32 v16, v16, v17
-; GFX9-NEXT: v_sub_u32_e32 v2, v2, v16
-; GFX9-NEXT: v_bfrev_b32_e32 v16, -2
-; GFX9-NEXT: v_max_i32_e32 v17, -1, v3
-; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_bfrev_b32_e32 v18, 1
-; GFX9-NEXT: v_min_i32_e32 v19, -1, v3
-; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_sub_u32_e32 v3, v3, v17
-; GFX9-NEXT: v_max_i32_e32 v17, -1, v4
-; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16
-; GFX9-NEXT: v_min_i32_e32 v19, -1, v4
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v20
-; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_sub_u32_e32 v4, v4, v17
-; GFX9-NEXT: v_max_i32_e32 v17, -1, v5
-; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16
-; GFX9-NEXT: v_min_i32_e32 v19, -1, v5
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v21
-; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_sub_u32_e32 v5, v5, v17
-; GFX9-NEXT: v_max_i32_e32 v17, -1, v6
-; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16
-; GFX9-NEXT: v_min_i32_e32 v19, -1, v6
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v22
-; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_sub_u32_e32 v6, v6, v17
-; GFX9-NEXT: v_max_i32_e32 v17, -1, v7
-; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16
-; GFX9-NEXT: v_min_i32_e32 v19, -1, v7
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v23
-; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_sub_u32_e32 v7, v7, v17
-; GFX9-NEXT: v_max_i32_e32 v17, -1, v8
-; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16
-; GFX9-NEXT: v_min_i32_e32 v19, -1, v8
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v24
-; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_sub_u32_e32 v8, v8, v17
-; GFX9-NEXT: v_max_i32_e32 v17, -1, v9
-; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16
-; GFX9-NEXT: v_min_i32_e32 v19, -1, v9
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v25
-; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_sub_u32_e32 v9, v9, v17
-; GFX9-NEXT: v_max_i32_e32 v17, -1, v10
-; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16
-; GFX9-NEXT: v_min_i32_e32 v19, -1, v10
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v26
-; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_sub_u32_e32 v10, v10, v17
-; GFX9-NEXT: v_max_i32_e32 v17, -1, v11
-; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16
-; GFX9-NEXT: v_min_i32_e32 v19, -1, v11
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v27
-; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_sub_u32_e32 v11, v11, v17
-; GFX9-NEXT: v_max_i32_e32 v17, -1, v12
-; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16
-; GFX9-NEXT: v_min_i32_e32 v19, -1, v12
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v28
-; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_sub_u32_e32 v12, v12, v17
-; GFX9-NEXT: v_max_i32_e32 v17, -1, v13
-; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16
-; GFX9-NEXT: v_min_i32_e32 v19, -1, v13
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v29
-; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_sub_u32_e32 v13, v13, v17
-; GFX9-NEXT: v_max_i32_e32 v17, -1, v14
-; GFX9-NEXT: v_sub_u32_e32 v17, v17, v16
-; GFX9-NEXT: v_min_i32_e32 v19, -1, v14
-; GFX9-NEXT: v_max_i32_e32 v17, v17, v30
-; GFX9-NEXT: v_sub_u32_e32 v19, v19, v18
-; GFX9-NEXT: v_min_i32_e32 v17, v17, v19
-; GFX9-NEXT: v_sub_u32_e32 v14, v14, v17
-; GFX9-NEXT: v_max_i32_e32 v17, -1, v15
-; GFX9-NEXT: v_sub_u32_e32 v16, v17, v16
-; GFX9-NEXT: v_min_i32_e32 v17, -1, v15
-; GFX9-NEXT: v_sub_u32_e32 v17, v17, v18
-; GFX9-NEXT: v_max_i32_e32 v16, v16, v31
-; GFX9-NEXT: v_min_i32_e32 v16, v16, v17
-; GFX9-NEXT: v_sub_u32_e32 v15, v15, v16
+; GFX9-NEXT: v_sub_i32 v0, v0, v16 clamp
+; GFX9-NEXT: v_sub_i32 v1, v1, v17 clamp
+; GFX9-NEXT: v_sub_i32 v2, v2, v18 clamp
+; GFX9-NEXT: v_sub_i32 v3, v3, v19 clamp
+; GFX9-NEXT: v_sub_i32 v4, v4, v20 clamp
+; GFX9-NEXT: v_sub_i32 v5, v5, v21 clamp
+; GFX9-NEXT: v_sub_i32 v6, v6, v22 clamp
+; GFX9-NEXT: v_sub_i32 v7, v7, v23 clamp
+; GFX9-NEXT: v_sub_i32 v8, v8, v24 clamp
+; GFX9-NEXT: v_sub_i32 v9, v9, v25 clamp
+; GFX9-NEXT: v_sub_i32 v10, v10, v26 clamp
+; GFX9-NEXT: v_sub_i32 v11, v11, v27 clamp
+; GFX9-NEXT: v_sub_i32 v12, v12, v28 clamp
+; GFX9-NEXT: v_sub_i32 v13, v13, v29 clamp
+; GFX9-NEXT: v_sub_i32 v14, v14, v30 clamp
+; GFX9-NEXT: v_sub_i32 v15, v15, v31 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v16i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_max_i32_e32 v32, -1, v0
-; GFX10-NEXT: s_brev_b32 s4, -2
-; GFX10-NEXT: v_min_i32_e32 v33, -1, v0
-; GFX10-NEXT: s_brev_b32 s5, 1
-; GFX10-NEXT: v_max_i32_e32 v36, -1, v2
-; GFX10-NEXT: v_subrev_nc_u32_e32 v35, s4, v32
-; GFX10-NEXT: v_max_i32_e32 v32, -1, v1
-; GFX10-NEXT: v_subrev_nc_u32_e32 v33, s5, v33
-; GFX10-NEXT: v_bfrev_b32_e32 v34, -2
-; GFX10-NEXT: v_subrev_nc_u32_e32 v36, s4, v36
-; GFX10-NEXT: v_max_i32_e32 v16, v35, v16
-; GFX10-NEXT: v_subrev_nc_u32_e32 v32, s4, v32
-; GFX10-NEXT: v_max_i32_e32 v39, -1, v3
-; GFX10-NEXT: v_min_i32_e32 v37, -1, v1
-; GFX10-NEXT: v_max_i32_e32 v18, v36, v18
-; GFX10-NEXT: v_min_i32_e32 v16, v16, v33
-; GFX10-NEXT: v_min_i32_e32 v33, -1, v2
-; GFX10-NEXT: v_max_i32_e32 v38, v32, v17
-; GFX10-NEXT: v_max_i32_e32 v17, -1, v4
-; GFX10-NEXT: v_sub_nc_u32_e32 v36, v39, v34
-; GFX10-NEXT: v_bfrev_b32_e32 v35, 1
-; GFX10-NEXT: v_subrev_nc_u32_e32 v32, s5, v33
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v16
-; GFX10-NEXT: v_min_i32_e32 v33, -1, v3
-; GFX10-NEXT: v_sub_nc_u32_e32 v17, v17, v34
-; GFX10-NEXT: v_subrev_nc_u32_e32 v37, s5, v37
-; GFX10-NEXT: v_min_i32_e32 v16, v18, v32
-; GFX10-NEXT: v_max_i32_e32 v19, v36, v19
-; GFX10-NEXT: v_sub_nc_u32_e32 v18, v33, v35
-; GFX10-NEXT: v_max_i32_e32 v17, v17, v20
-; GFX10-NEXT: v_min_i32_e32 v39, v38, v37
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v16
-; GFX10-NEXT: v_min_i32_e32 v16, -1, v4
-; GFX10-NEXT: v_min_i32_e32 v18, v19, v18
-; GFX10-NEXT: v_max_i32_e32 v19, -1, v5
-; GFX10-NEXT: v_max_i32_e32 v32, -1, v6
-; GFX10-NEXT: v_min_i32_e32 v33, -1, v5
-; GFX10-NEXT: v_sub_nc_u32_e32 v16, v16, v35
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v39
-; GFX10-NEXT: v_sub_nc_u32_e32 v19, v19, v34
-; GFX10-NEXT: v_sub_nc_u32_e32 v32, v32, v34
-; GFX10-NEXT: v_min_i32_e32 v36, -1, v6
-; GFX10-NEXT: v_min_i32_e32 v39, v17, v16
-; GFX10-NEXT: v_max_i32_e32 v17, -1, v7
-; GFX10-NEXT: v_min_i32_e32 v16, -1, v7
-; GFX10-NEXT: v_max_i32_e32 v19, v19, v21
-; GFX10-NEXT: v_sub_nc_u32_e32 v20, v33, v35
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v39
-; GFX10-NEXT: v_sub_nc_u32_e32 v17, v17, v34
-; GFX10-NEXT: v_sub_nc_u32_e32 v21, v36, v35
-; GFX10-NEXT: v_max_i32_e32 v22, v32, v22
-; GFX10-NEXT: v_min_i32_e32 v38, v19, v20
-; GFX10-NEXT: v_max_i32_e32 v20, -1, v9
-; GFX10-NEXT: v_max_i32_e32 v39, -1, v8
-; GFX10-NEXT: v_sub_nc_u32_e32 v16, v16, v35
-; GFX10-NEXT: v_max_i32_e32 v17, v17, v23
-; GFX10-NEXT: v_min_i32_e32 v19, v22, v21
-; GFX10-NEXT: v_min_i32_e32 v21, -1, v9
-; GFX10-NEXT: v_sub_nc_u32_e32 v20, v20, v34
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, v3, v18
-; GFX10-NEXT: v_sub_nc_u32_e32 v18, v39, v34
-; GFX10-NEXT: v_max_i32_e32 v39, -1, v10
-; GFX10-NEXT: v_min_i32_e32 v16, v17, v16
-; GFX10-NEXT: v_min_i32_e32 v22, -1, v8
-; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v38
-; GFX10-NEXT: v_sub_nc_u32_e32 v6, v6, v19
-; GFX10-NEXT: v_max_i32_e32 v18, v18, v24
-; GFX10-NEXT: v_max_i32_e32 v20, v20, v25
-; GFX10-NEXT: v_sub_nc_u32_e32 v19, v22, v35
-; GFX10-NEXT: v_sub_nc_u32_e32 v21, v21, v35
-; GFX10-NEXT: v_sub_nc_u32_e32 v7, v7, v16
-; GFX10-NEXT: v_max_i32_e32 v16, -1, v11
-; GFX10-NEXT: v_min_i32_e32 v38, -1, v10
-; GFX10-NEXT: v_sub_nc_u32_e32 v23, v39, v34
-; GFX10-NEXT: v_min_i32_e32 v17, v18, v19
-; GFX10-NEXT: v_min_i32_e32 v20, v20, v21
-; GFX10-NEXT: v_sub_nc_u32_e32 v16, v16, v34
-; GFX10-NEXT: v_sub_nc_u32_e32 v18, v38, v35
-; GFX10-NEXT: v_max_i32_e32 v19, v23, v26
-; GFX10-NEXT: v_sub_nc_u32_e32 v8, v8, v17
-; GFX10-NEXT: v_sub_nc_u32_e32 v9, v9, v20
-; GFX10-NEXT: v_max_i32_e32 v20, -1, v13
-; GFX10-NEXT: v_max_i32_e32 v16, v16, v27
-; GFX10-NEXT: v_min_i32_e32 v17, v19, v18
-; GFX10-NEXT: v_max_i32_e32 v19, -1, v12
-; GFX10-NEXT: v_max_i32_e32 v27, -1, v14
-; GFX10-NEXT: v_max_i32_e32 v23, -1, v15
-; GFX10-NEXT: v_min_i32_e32 v18, -1, v11
-; GFX10-NEXT: v_min_i32_e32 v21, -1, v13
-; GFX10-NEXT: v_sub_nc_u32_e32 v19, v19, v34
-; GFX10-NEXT: v_sub_nc_u32_e32 v20, v20, v34
-; GFX10-NEXT: v_min_i32_e32 v24, -1, v14
-; GFX10-NEXT: v_min_i32_e32 v25, -1, v15
-; GFX10-NEXT: v_sub_nc_u32_e32 v26, v23, v34
-; GFX10-NEXT: v_sub_nc_u32_e32 v10, v10, v17
-; GFX10-NEXT: v_min_i32_e32 v17, -1, v12
-; GFX10-NEXT: v_sub_nc_u32_e32 v27, v27, v34
-; GFX10-NEXT: v_sub_nc_u32_e32 v18, v18, v35
-; GFX10-NEXT: v_max_i32_e32 v19, v19, v28
-; GFX10-NEXT: v_sub_nc_u32_e32 v21, v21, v35
-; GFX10-NEXT: v_sub_nc_u32_e32 v17, v17, v35
-; GFX10-NEXT: v_max_i32_e32 v20, v20, v29
-; GFX10-NEXT: v_sub_nc_u32_e32 v24, v24, v35
-; GFX10-NEXT: v_max_i32_e32 v22, v27, v30
-; GFX10-NEXT: v_sub_nc_u32_e32 v25, v25, v35
-; GFX10-NEXT: v_max_i32_e32 v23, v26, v31
-; GFX10-NEXT: v_min_i32_e32 v16, v16, v18
-; GFX10-NEXT: v_min_i32_e32 v17, v19, v17
-; GFX10-NEXT: v_min_i32_e32 v18, v20, v21
-; GFX10-NEXT: v_min_i32_e32 v19, v22, v24
-; GFX10-NEXT: v_min_i32_e32 v20, v23, v25
-; GFX10-NEXT: v_sub_nc_u32_e32 v11, v11, v16
-; GFX10-NEXT: v_sub_nc_u32_e32 v12, v12, v17
-; GFX10-NEXT: v_sub_nc_u32_e32 v13, v13, v18
-; GFX10-NEXT: v_sub_nc_u32_e32 v14, v14, v19
-; GFX10-NEXT: v_sub_nc_u32_e32 v15, v15, v20
+; GFX10-NEXT: v_sub_nc_i32 v0, v0, v16 clamp
+; GFX10-NEXT: v_sub_nc_i32 v1, v1, v17 clamp
+; GFX10-NEXT: v_sub_nc_i32 v2, v2, v18 clamp
+; GFX10-NEXT: v_sub_nc_i32 v3, v3, v19 clamp
+; GFX10-NEXT: v_sub_nc_i32 v4, v4, v20 clamp
+; GFX10-NEXT: v_sub_nc_i32 v5, v5, v21 clamp
+; GFX10-NEXT: v_sub_nc_i32 v6, v6, v22 clamp
+; GFX10-NEXT: v_sub_nc_i32 v7, v7, v23 clamp
+; GFX10-NEXT: v_sub_nc_i32 v8, v8, v24 clamp
+; GFX10-NEXT: v_sub_nc_i32 v9, v9, v25 clamp
+; GFX10-NEXT: v_sub_nc_i32 v10, v10, v26 clamp
+; GFX10-NEXT: v_sub_nc_i32 v11, v11, v27 clamp
+; GFX10-NEXT: v_sub_nc_i32 v12, v12, v28 clamp
+; GFX10-NEXT: v_sub_nc_i32 v13, v13, v29 clamp
+; GFX10-NEXT: v_sub_nc_i32 v14, v14, v30 clamp
+; GFX10-NEXT: v_sub_nc_i32 v15, v15, v31 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
@@ -3829,367 +2719,91 @@ define amdgpu_ps <16 x i32> @s_ssubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32>
;
; GFX9-LABEL: s_ssubsat_v16i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_gt_i32 s0, -1
-; GFX9-NEXT: s_brev_b32 s32, -2
-; GFX9-NEXT: s_cselect_b32 s34, s0, -1
-; GFX9-NEXT: s_sub_i32 s34, s34, s32
-; GFX9-NEXT: s_cmp_lt_i32 s0, -1
-; GFX9-NEXT: s_brev_b32 s33, 1
-; GFX9-NEXT: s_cselect_b32 s35, s0, -1
-; GFX9-NEXT: s_sub_i32 s35, s35, s33
-; GFX9-NEXT: s_cmp_gt_i32 s34, s16
-; GFX9-NEXT: s_cselect_b32 s16, s34, s16
-; GFX9-NEXT: s_cmp_lt_i32 s16, s35
-; GFX9-NEXT: s_cselect_b32 s16, s16, s35
-; GFX9-NEXT: s_sub_i32 s0, s0, s16
-; GFX9-NEXT: s_cmp_gt_i32 s1, -1
-; GFX9-NEXT: s_cselect_b32 s16, s1, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s1, -1
-; GFX9-NEXT: s_cselect_b32 s34, s1, -1
-; GFX9-NEXT: s_sub_i32 s34, s34, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_cmp_lt_i32 s16, s34
-; GFX9-NEXT: s_cselect_b32 s16, s16, s34
-; GFX9-NEXT: s_sub_i32 s1, s1, s16
-; GFX9-NEXT: s_cmp_gt_i32 s2, -1
-; GFX9-NEXT: s_cselect_b32 s16, s2, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s2, -1
-; GFX9-NEXT: s_cselect_b32 s17, s2, -1
-; GFX9-NEXT: s_sub_i32 s17, s17, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s18
-; GFX9-NEXT: s_cselect_b32 s16, s16, s18
-; GFX9-NEXT: s_cmp_lt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_sub_i32 s2, s2, s16
-; GFX9-NEXT: s_cmp_gt_i32 s3, -1
-; GFX9-NEXT: s_cselect_b32 s16, s3, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s3, -1
-; GFX9-NEXT: s_cselect_b32 s17, s3, -1
-; GFX9-NEXT: s_sub_i32 s17, s17, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s19
-; GFX9-NEXT: s_cselect_b32 s16, s16, s19
-; GFX9-NEXT: s_cmp_lt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_sub_i32 s3, s3, s16
-; GFX9-NEXT: s_cmp_gt_i32 s4, -1
-; GFX9-NEXT: s_cselect_b32 s16, s4, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s4, -1
-; GFX9-NEXT: s_cselect_b32 s17, s4, -1
-; GFX9-NEXT: s_sub_i32 s17, s17, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s20
-; GFX9-NEXT: s_cselect_b32 s16, s16, s20
-; GFX9-NEXT: s_cmp_lt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_sub_i32 s4, s4, s16
-; GFX9-NEXT: s_cmp_gt_i32 s5, -1
-; GFX9-NEXT: s_cselect_b32 s16, s5, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s5, -1
-; GFX9-NEXT: s_cselect_b32 s17, s5, -1
-; GFX9-NEXT: s_sub_i32 s17, s17, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s21
-; GFX9-NEXT: s_cselect_b32 s16, s16, s21
-; GFX9-NEXT: s_cmp_lt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_sub_i32 s5, s5, s16
-; GFX9-NEXT: s_cmp_gt_i32 s6, -1
-; GFX9-NEXT: s_cselect_b32 s16, s6, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s6, -1
-; GFX9-NEXT: s_cselect_b32 s17, s6, -1
-; GFX9-NEXT: s_sub_i32 s17, s17, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s22
-; GFX9-NEXT: s_cselect_b32 s16, s16, s22
-; GFX9-NEXT: s_cmp_lt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_sub_i32 s6, s6, s16
-; GFX9-NEXT: s_cmp_gt_i32 s7, -1
-; GFX9-NEXT: s_cselect_b32 s16, s7, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s7, -1
-; GFX9-NEXT: s_cselect_b32 s17, s7, -1
-; GFX9-NEXT: s_sub_i32 s17, s17, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s23
-; GFX9-NEXT: s_cselect_b32 s16, s16, s23
-; GFX9-NEXT: s_cmp_lt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_sub_i32 s7, s7, s16
-; GFX9-NEXT: s_cmp_gt_i32 s8, -1
-; GFX9-NEXT: s_cselect_b32 s16, s8, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s8, -1
-; GFX9-NEXT: s_cselect_b32 s17, s8, -1
-; GFX9-NEXT: s_sub_i32 s17, s17, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s24
-; GFX9-NEXT: s_cselect_b32 s16, s16, s24
-; GFX9-NEXT: s_cmp_lt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_sub_i32 s8, s8, s16
-; GFX9-NEXT: s_cmp_gt_i32 s9, -1
-; GFX9-NEXT: s_cselect_b32 s16, s9, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s9, -1
-; GFX9-NEXT: s_cselect_b32 s17, s9, -1
-; GFX9-NEXT: s_sub_i32 s17, s17, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s25
-; GFX9-NEXT: s_cselect_b32 s16, s16, s25
-; GFX9-NEXT: s_cmp_lt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_sub_i32 s9, s9, s16
-; GFX9-NEXT: s_cmp_gt_i32 s10, -1
-; GFX9-NEXT: s_cselect_b32 s16, s10, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s10, -1
-; GFX9-NEXT: s_cselect_b32 s17, s10, -1
-; GFX9-NEXT: s_sub_i32 s17, s17, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s26
-; GFX9-NEXT: s_cselect_b32 s16, s16, s26
-; GFX9-NEXT: s_cmp_lt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_sub_i32 s10, s10, s16
-; GFX9-NEXT: s_cmp_gt_i32 s11, -1
-; GFX9-NEXT: s_cselect_b32 s16, s11, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s11, -1
-; GFX9-NEXT: s_cselect_b32 s17, s11, -1
-; GFX9-NEXT: s_sub_i32 s17, s17, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s27
-; GFX9-NEXT: s_cselect_b32 s16, s16, s27
-; GFX9-NEXT: s_cmp_lt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_sub_i32 s11, s11, s16
-; GFX9-NEXT: s_cmp_gt_i32 s12, -1
-; GFX9-NEXT: s_cselect_b32 s16, s12, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s12, -1
-; GFX9-NEXT: s_cselect_b32 s17, s12, -1
-; GFX9-NEXT: s_sub_i32 s17, s17, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s28
-; GFX9-NEXT: s_cselect_b32 s16, s16, s28
-; GFX9-NEXT: s_cmp_lt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_sub_i32 s12, s12, s16
-; GFX9-NEXT: s_cmp_gt_i32 s13, -1
-; GFX9-NEXT: s_cselect_b32 s16, s13, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s13, -1
-; GFX9-NEXT: s_cselect_b32 s17, s13, -1
-; GFX9-NEXT: s_sub_i32 s17, s17, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s29
-; GFX9-NEXT: s_cselect_b32 s16, s16, s29
-; GFX9-NEXT: s_cmp_lt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_sub_i32 s13, s13, s16
-; GFX9-NEXT: s_cmp_gt_i32 s14, -1
-; GFX9-NEXT: s_cselect_b32 s16, s14, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s14, -1
-; GFX9-NEXT: s_cselect_b32 s17, s14, -1
-; GFX9-NEXT: s_sub_i32 s17, s17, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s30
-; GFX9-NEXT: s_cselect_b32 s16, s16, s30
-; GFX9-NEXT: s_cmp_lt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_sub_i32 s14, s14, s16
-; GFX9-NEXT: s_cmp_gt_i32 s15, -1
-; GFX9-NEXT: s_cselect_b32 s16, s15, -1
-; GFX9-NEXT: s_sub_i32 s16, s16, s32
-; GFX9-NEXT: s_cmp_lt_i32 s15, -1
-; GFX9-NEXT: s_cselect_b32 s17, s15, -1
-; GFX9-NEXT: s_sub_i32 s17, s17, s33
-; GFX9-NEXT: s_cmp_gt_i32 s16, s31
-; GFX9-NEXT: s_cselect_b32 s16, s16, s31
-; GFX9-NEXT: s_cmp_lt_i32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_sub_i32 s15, s15, s16
+; GFX9-NEXT: v_mov_b32_e32 v0, s16
+; GFX9-NEXT: v_mov_b32_e32 v1, s17
+; GFX9-NEXT: v_mov_b32_e32 v2, s18
+; GFX9-NEXT: v_mov_b32_e32 v3, s19
+; GFX9-NEXT: v_mov_b32_e32 v4, s20
+; GFX9-NEXT: v_mov_b32_e32 v5, s21
+; GFX9-NEXT: v_mov_b32_e32 v6, s22
+; GFX9-NEXT: v_mov_b32_e32 v7, s23
+; GFX9-NEXT: v_mov_b32_e32 v8, s24
+; GFX9-NEXT: v_mov_b32_e32 v9, s25
+; GFX9-NEXT: v_mov_b32_e32 v10, s26
+; GFX9-NEXT: v_mov_b32_e32 v11, s27
+; GFX9-NEXT: v_mov_b32_e32 v12, s28
+; GFX9-NEXT: v_mov_b32_e32 v13, s29
+; GFX9-NEXT: v_mov_b32_e32 v14, s30
+; GFX9-NEXT: v_mov_b32_e32 v15, s31
+; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
+; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp
+; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp
+; GFX9-NEXT: v_sub_i32 v3, s3, v3 clamp
+; GFX9-NEXT: v_sub_i32 v4, s4, v4 clamp
+; GFX9-NEXT: v_sub_i32 v5, s5, v5 clamp
+; GFX9-NEXT: v_sub_i32 v6, s6, v6 clamp
+; GFX9-NEXT: v_sub_i32 v7, s7, v7 clamp
+; GFX9-NEXT: v_sub_i32 v8, s8, v8 clamp
+; GFX9-NEXT: v_sub_i32 v9, s9, v9 clamp
+; GFX9-NEXT: v_sub_i32 v10, s10, v10 clamp
+; GFX9-NEXT: v_sub_i32 v11, s11, v11 clamp
+; GFX9-NEXT: v_sub_i32 v12, s12, v12 clamp
+; GFX9-NEXT: v_sub_i32 v13, s13, v13 clamp
+; GFX9-NEXT: v_sub_i32 v14, s14, v14 clamp
+; GFX9-NEXT: v_sub_i32 v15, s15, v15 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
+; GFX9-NEXT: v_readfirstlane_b32 s4, v4
+; GFX9-NEXT: v_readfirstlane_b32 s5, v5
+; GFX9-NEXT: v_readfirstlane_b32 s6, v6
+; GFX9-NEXT: v_readfirstlane_b32 s7, v7
+; GFX9-NEXT: v_readfirstlane_b32 s8, v8
+; GFX9-NEXT: v_readfirstlane_b32 s9, v9
+; GFX9-NEXT: v_readfirstlane_b32 s10, v10
+; GFX9-NEXT: v_readfirstlane_b32 s11, v11
+; GFX9-NEXT: v_readfirstlane_b32 s12, v12
+; GFX9-NEXT: v_readfirstlane_b32 s13, v13
+; GFX9-NEXT: v_readfirstlane_b32 s14, v14
+; GFX9-NEXT: v_readfirstlane_b32 s15, v15
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v16i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_gt_i32 s0, -1
-; GFX10-NEXT: s_brev_b32 s46, -2
-; GFX10-NEXT: s_cselect_b32 s33, s0, -1
-; GFX10-NEXT: s_brev_b32 s34, 1
-; GFX10-NEXT: s_sub_i32 s47, s33, s46
-; GFX10-NEXT: s_cmp_lt_i32 s0, -1
+; GFX10-NEXT: v_sub_nc_i32 v0, s0, s16 clamp
+; GFX10-NEXT: v_sub_nc_i32 v1, s1, s17 clamp
+; GFX10-NEXT: v_sub_nc_i32 v2, s2, s18 clamp
+; GFX10-NEXT: v_sub_nc_i32 v3, s3, s19 clamp
+; GFX10-NEXT: v_sub_nc_i32 v4, s4, s20 clamp
+; GFX10-NEXT: v_sub_nc_i32 v5, s5, s21 clamp
+; GFX10-NEXT: v_sub_nc_i32 v6, s6, s22 clamp
+; GFX10-NEXT: v_sub_nc_i32 v7, s7, s23 clamp
+; GFX10-NEXT: v_sub_nc_i32 v8, s8, s24 clamp
+; GFX10-NEXT: v_sub_nc_i32 v9, s9, s25 clamp
+; GFX10-NEXT: v_sub_nc_i32 v10, s10, s26 clamp
+; GFX10-NEXT: v_sub_nc_i32 v11, s11, s27 clamp
+; GFX10-NEXT: v_sub_nc_i32 v12, s12, s28 clamp
+; GFX10-NEXT: v_sub_nc_i32 v13, s13, s29 clamp
+; GFX10-NEXT: v_sub_nc_i32 v14, s14, s30 clamp
+; GFX10-NEXT: v_sub_nc_i32 v15, s15, s31 clamp
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10-NEXT: v_readfirstlane_b32 s8, v8
+; GFX10-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10-NEXT: v_readfirstlane_b32 s10, v10
+; GFX10-NEXT: v_readfirstlane_b32 s11, v11
+; GFX10-NEXT: v_readfirstlane_b32 s12, v12
+; GFX10-NEXT: v_readfirstlane_b32 s13, v13
+; GFX10-NEXT: v_readfirstlane_b32 s14, v14
+; GFX10-NEXT: v_readfirstlane_b32 s15, v15
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s35, s0, -1
-; GFX10-NEXT: s_sub_i32 s35, s35, s34
-; GFX10-NEXT: s_cmp_gt_i32 s47, s16
-; GFX10-NEXT: s_cselect_b32 s16, s47, s16
-; GFX10-NEXT: s_cmp_lt_i32 s16, s35
-; GFX10-NEXT: s_cselect_b32 s47, s16, s35
-; GFX10-NEXT: s_sub_i32 s0, s0, s47
-; GFX10-NEXT: s_cmp_gt_i32 s1, -1
-; GFX10-NEXT: s_cselect_b32 s16, s1, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s1, -1
-; GFX10-NEXT: s_cselect_b32 s33, s1, -1
-; GFX10-NEXT: s_sub_i32 s47, s33, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_cmp_lt_i32 s16, s47
-; GFX10-NEXT: s_cselect_b32 s47, s16, s47
-; GFX10-NEXT: s_sub_i32 s1, s1, s47
-; GFX10-NEXT: s_cmp_gt_i32 s2, -1
-; GFX10-NEXT: s_cselect_b32 s16, s2, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s2, -1
-; GFX10-NEXT: s_cselect_b32 s17, s2, -1
-; GFX10-NEXT: s_sub_i32 s17, s17, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s18
-; GFX10-NEXT: s_cselect_b32 s16, s16, s18
-; GFX10-NEXT: s_cmp_lt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_sub_i32 s2, s2, s16
-; GFX10-NEXT: s_cmp_gt_i32 s3, -1
-; GFX10-NEXT: s_cselect_b32 s16, s3, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s3, -1
-; GFX10-NEXT: s_cselect_b32 s17, s3, -1
-; GFX10-NEXT: s_sub_i32 s17, s17, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s19
-; GFX10-NEXT: s_cselect_b32 s16, s16, s19
-; GFX10-NEXT: s_cmp_lt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_sub_i32 s3, s3, s16
-; GFX10-NEXT: s_cmp_gt_i32 s4, -1
-; GFX10-NEXT: s_cselect_b32 s16, s4, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s4, -1
-; GFX10-NEXT: s_cselect_b32 s17, s4, -1
-; GFX10-NEXT: s_sub_i32 s17, s17, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s20
-; GFX10-NEXT: s_cselect_b32 s16, s16, s20
-; GFX10-NEXT: s_cmp_lt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_sub_i32 s4, s4, s16
-; GFX10-NEXT: s_cmp_gt_i32 s5, -1
-; GFX10-NEXT: s_cselect_b32 s16, s5, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s5, -1
-; GFX10-NEXT: s_cselect_b32 s17, s5, -1
-; GFX10-NEXT: s_sub_i32 s17, s17, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s21
-; GFX10-NEXT: s_cselect_b32 s16, s16, s21
-; GFX10-NEXT: s_cmp_lt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_sub_i32 s5, s5, s16
-; GFX10-NEXT: s_cmp_gt_i32 s6, -1
-; GFX10-NEXT: s_cselect_b32 s16, s6, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s6, -1
-; GFX10-NEXT: s_cselect_b32 s17, s6, -1
-; GFX10-NEXT: s_sub_i32 s17, s17, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s22
-; GFX10-NEXT: s_cselect_b32 s16, s16, s22
-; GFX10-NEXT: s_cmp_lt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_sub_i32 s6, s6, s16
-; GFX10-NEXT: s_cmp_gt_i32 s7, -1
-; GFX10-NEXT: s_cselect_b32 s16, s7, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s7, -1
-; GFX10-NEXT: s_cselect_b32 s17, s7, -1
-; GFX10-NEXT: s_sub_i32 s17, s17, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s23
-; GFX10-NEXT: s_cselect_b32 s16, s16, s23
-; GFX10-NEXT: s_cmp_lt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_sub_i32 s7, s7, s16
-; GFX10-NEXT: s_cmp_gt_i32 s8, -1
-; GFX10-NEXT: s_cselect_b32 s16, s8, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s8, -1
-; GFX10-NEXT: s_cselect_b32 s17, s8, -1
-; GFX10-NEXT: s_sub_i32 s17, s17, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s24
-; GFX10-NEXT: s_cselect_b32 s16, s16, s24
-; GFX10-NEXT: s_cmp_lt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_sub_i32 s8, s8, s16
-; GFX10-NEXT: s_cmp_gt_i32 s9, -1
-; GFX10-NEXT: s_cselect_b32 s16, s9, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s9, -1
-; GFX10-NEXT: s_cselect_b32 s17, s9, -1
-; GFX10-NEXT: s_sub_i32 s17, s17, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s25
-; GFX10-NEXT: s_cselect_b32 s16, s16, s25
-; GFX10-NEXT: s_cmp_lt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_sub_i32 s9, s9, s16
-; GFX10-NEXT: s_cmp_gt_i32 s10, -1
-; GFX10-NEXT: s_cselect_b32 s16, s10, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s10, -1
-; GFX10-NEXT: s_cselect_b32 s17, s10, -1
-; GFX10-NEXT: s_sub_i32 s17, s17, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s26
-; GFX10-NEXT: s_cselect_b32 s16, s16, s26
-; GFX10-NEXT: s_cmp_lt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_sub_i32 s10, s10, s16
-; GFX10-NEXT: s_cmp_gt_i32 s11, -1
-; GFX10-NEXT: s_cselect_b32 s16, s11, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s11, -1
-; GFX10-NEXT: s_cselect_b32 s17, s11, -1
-; GFX10-NEXT: s_sub_i32 s17, s17, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s27
-; GFX10-NEXT: s_cselect_b32 s16, s16, s27
-; GFX10-NEXT: s_cmp_lt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_sub_i32 s11, s11, s16
-; GFX10-NEXT: s_cmp_gt_i32 s12, -1
-; GFX10-NEXT: s_cselect_b32 s16, s12, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s12, -1
-; GFX10-NEXT: s_cselect_b32 s17, s12, -1
-; GFX10-NEXT: s_sub_i32 s17, s17, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s28
-; GFX10-NEXT: s_cselect_b32 s16, s16, s28
-; GFX10-NEXT: s_cmp_lt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_sub_i32 s12, s12, s16
-; GFX10-NEXT: s_cmp_gt_i32 s13, -1
-; GFX10-NEXT: s_cselect_b32 s16, s13, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s13, -1
-; GFX10-NEXT: s_cselect_b32 s17, s13, -1
-; GFX10-NEXT: s_sub_i32 s17, s17, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s29
-; GFX10-NEXT: s_cselect_b32 s16, s16, s29
-; GFX10-NEXT: s_cmp_lt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_sub_i32 s13, s13, s16
-; GFX10-NEXT: s_cmp_gt_i32 s14, -1
-; GFX10-NEXT: s_cselect_b32 s16, s14, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s14, -1
-; GFX10-NEXT: s_cselect_b32 s17, s14, -1
-; GFX10-NEXT: s_sub_i32 s17, s17, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s30
-; GFX10-NEXT: s_cselect_b32 s16, s16, s30
-; GFX10-NEXT: s_cmp_lt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_sub_i32 s14, s14, s16
-; GFX10-NEXT: s_cmp_gt_i32 s15, -1
-; GFX10-NEXT: s_cselect_b32 s16, s15, -1
-; GFX10-NEXT: s_sub_i32 s16, s16, s46
-; GFX10-NEXT: s_cmp_lt_i32 s15, -1
-; GFX10-NEXT: s_cselect_b32 s17, s15, -1
-; GFX10-NEXT: s_sub_i32 s17, s17, s34
-; GFX10-NEXT: s_cmp_gt_i32 s16, s31
-; GFX10-NEXT: s_cselect_b32 s16, s16, s31
-; GFX10-NEXT: s_cmp_lt_i32 s16, s17
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_sub_i32 s15, s15, s16
; GFX10-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
@@ -4226,27 +2840,15 @@ define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) {
; GFX9-LABEL: v_ssubsat_i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_max_i16_e32 v2, -1, v0
-; GFX9-NEXT: v_min_i16_e32 v3, -1, v0
-; GFX9-NEXT: v_subrev_u16_e32 v2, 0x7fff, v2
-; GFX9-NEXT: v_subrev_u16_e32 v3, 0x8000, v3
-; GFX9-NEXT: v_max_i16_e32 v1, v2, v1
-; GFX9-NEXT: v_min_i16_e32 v1, v1, v3
-; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_max_i16_e64 v2, v0, -1
-; GFX10-NEXT: v_min_i16_e64 v3, v0, -1
+; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u16_e64 v2, v2, 0x7fff
-; GFX10-NEXT: v_sub_nc_u16_e64 v3, v3, 0x8000
-; GFX10-NEXT: v_max_i16_e64 v1, v2, v1
-; GFX10-NEXT: v_min_i16_e64 v1, v1, v3
-; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
@@ -4294,45 +2896,16 @@ define amdgpu_ps i16 @s_ssubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
;
; GFX9-LABEL: s_ssubsat_i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sext_i32_i16 s2, s0
-; GFX9-NEXT: s_sext_i32_i16 s3, -1
-; GFX9-NEXT: s_cmp_gt_i32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s4, s2, s3
-; GFX9-NEXT: s_sub_i32 s4, s4, 0x7fff
-; GFX9-NEXT: s_cmp_lt_i32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s2, s3
-; GFX9-NEXT: s_sub_i32 s2, s2, 0xffff8000
-; GFX9-NEXT: s_sext_i32_i16 s3, s4
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_cmp_gt_i32 s3, s1
-; GFX9-NEXT: s_cselect_b32 s1, s3, s1
-; GFX9-NEXT: s_sext_i32_i16 s1, s1
-; GFX9-NEXT: s_sext_i32_i16 s2, s2
-; GFX9-NEXT: s_cmp_lt_i32 s1, s2
-; GFX9-NEXT: s_cselect_b32 s1, s1, s2
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sext_i32_i16 s2, -1
-; GFX10-NEXT: s_sext_i32_i16 s3, s0
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_gt_i32 s3, s2
+; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s4, s3, s2
-; GFX10-NEXT: s_sub_i32 s4, s4, 0x7fff
-; GFX10-NEXT: s_cmp_lt_i32 s3, s2
-; GFX10-NEXT: s_cselect_b32 s2, s3, s2
-; GFX10-NEXT: s_sext_i32_i16 s3, s4
-; GFX10-NEXT: s_sub_i32 s2, s2, 0xffff8000
-; GFX10-NEXT: s_cmp_gt_i32 s3, s1
-; GFX10-NEXT: s_sext_i32_i16 s2, s2
-; GFX10-NEXT: s_cselect_b32 s1, s3, s1
-; GFX10-NEXT: s_sext_i32_i16 s1, s1
-; GFX10-NEXT: s_cmp_lt_i32 s1, s2
-; GFX10-NEXT: s_cselect_b32 s1, s1, s2
-; GFX10-NEXT: s_sub_i32 s0, s0, s1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
@@ -4372,33 +2945,13 @@ define amdgpu_ps half @ssubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
;
; GFX9-LABEL: ssubsat_i16_sv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sext_i32_i16 s1, s0
-; GFX9-NEXT: s_sext_i32_i16 s2, -1
-; GFX9-NEXT: s_cmp_gt_i32 s1, s2
-; GFX9-NEXT: s_cselect_b32 s3, s1, s2
-; GFX9-NEXT: s_sub_i32 s3, s3, 0x7fff
-; GFX9-NEXT: s_cmp_lt_i32 s1, s2
-; GFX9-NEXT: s_cselect_b32 s1, s1, s2
-; GFX9-NEXT: s_sub_i32 s1, s1, 0xffff8000
-; GFX9-NEXT: v_max_i16_e32 v0, s3, v0
-; GFX9-NEXT: v_min_i16_e32 v0, s1, v0
-; GFX9-NEXT: v_sub_u16_e32 v0, s0, v0
+; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i16_sv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sext_i32_i16 s1, s0
-; GFX10-NEXT: s_sext_i32_i16 s2, -1
+; GFX10-NEXT: v_sub_nc_i16 v0, s0, v0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cmp_gt_i32 s1, s2
-; GFX10-NEXT: s_cselect_b32 s3, s1, s2
-; GFX10-NEXT: s_sub_i32 s3, s3, 0x7fff
-; GFX10-NEXT: s_cmp_lt_i32 s1, s2
-; GFX10-NEXT: v_max_i16_e64 v0, s3, v0
-; GFX10-NEXT: s_cselect_b32 s1, s1, s2
-; GFX10-NEXT: s_sub_i32 s1, s1, 0xffff8000
-; GFX10-NEXT: v_min_i16_e64 v0, v0, s1
-; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
@@ -4433,25 +2986,13 @@ define amdgpu_ps half @ssubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
;
; GFX9-LABEL: ssubsat_i16_vs:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_max_i16_e32 v1, -1, v0
-; GFX9-NEXT: v_subrev_u16_e32 v1, 0x7fff, v1
-; GFX9-NEXT: v_min_i16_e32 v2, -1, v0
-; GFX9-NEXT: v_subrev_u16_e32 v2, 0x8000, v2
-; GFX9-NEXT: v_max_i16_e32 v1, s0, v1
-; GFX9-NEXT: v_min_i16_e32 v1, v1, v2
-; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_sub_i16 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i16_vs:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_max_i16_e64 v1, v0, -1
-; GFX10-NEXT: v_min_i16_e64 v2, v0, -1
+; GFX10-NEXT: v_sub_nc_i16 v0, v0, s0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u16_e64 v1, v1, 0x7fff
-; GFX10-NEXT: v_sub_nc_u16_e64 v2, v2, 0x8000
-; GFX10-NEXT: v_max_i16_e64 v1, v1, s0
-; GFX10-NEXT: v_min_i16_e64 v1, v1, v2
-; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
@@ -4512,29 +3053,15 @@ define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX9-LABEL: v_ssubsat_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_max_i16 v2, v0, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x7fff7fff
-; GFX9-NEXT: v_pk_sub_i16 v2, v2, v3
-; GFX9-NEXT: v_pk_min_i16 v3, v0, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_mov_b32_e32 v4, 0x80008000
-; GFX9-NEXT: v_pk_sub_i16 v3, v3, v4
-; GFX9-NEXT: v_pk_max_i16 v1, v2, v1
-; GFX9-NEXT: v_pk_min_i16 v1, v1, v3
-; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1
+; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v2i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_max_i16 v2, v0, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_min_i16 v3, v0, -1 op_sel_hi:[1,0]
+; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_sub_i16 v2, v2, 0x7fff7fff
-; GFX10-NEXT: v_pk_sub_i16 v3, v3, 0x80008000
-; GFX10-NEXT: v_pk_max_i16 v1, v2, v1
-; GFX10-NEXT: v_pk_min_i16 v1, v1, v3
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result
@@ -4627,99 +3154,16 @@ define amdgpu_ps i32 @s_ssubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs
;
; GFX9-LABEL: s_ssubsat_v2i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sext_i32_i16 s2, s0
-; GFX9-NEXT: s_ashr_i32 s3, s0, 16
-; GFX9-NEXT: s_sext_i32_i16 s4, -1
-; GFX9-NEXT: s_cmp_gt_i32 s2, s4
-; GFX9-NEXT: s_cselect_b32 s5, s2, s4
-; GFX9-NEXT: s_cmp_gt_i32 s3, -1
-; GFX9-NEXT: s_cselect_b32 s6, s3, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s6
-; GFX9-NEXT: s_lshr_b32 s6, s5, 16
-; GFX9-NEXT: s_sub_i32 s5, s5, 0x7fff7fff
-; GFX9-NEXT: s_sub_i32 s6, s6, 0x7fff
-; GFX9-NEXT: s_cmp_lt_i32 s2, s4
-; GFX9-NEXT: s_cselect_b32 s2, s2, s4
-; GFX9-NEXT: s_cmp_lt_i32 s3, -1
-; GFX9-NEXT: s_cselect_b32 s3, s3, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3
-; GFX9-NEXT: s_lshr_b32 s3, s2, 16
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s6
-; GFX9-NEXT: s_sub_i32 s2, s2, 0x80008000
-; GFX9-NEXT: s_sub_i32 s3, s3, 0x8000
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3
-; GFX9-NEXT: s_sext_i32_i16 s3, s5
-; GFX9-NEXT: s_ashr_i32 s4, s5, 16
-; GFX9-NEXT: s_sext_i32_i16 s5, s1
-; GFX9-NEXT: s_ashr_i32 s1, s1, 16
-; GFX9-NEXT: s_cmp_gt_i32 s3, s5
-; GFX9-NEXT: s_cselect_b32 s3, s3, s5
-; GFX9-NEXT: s_cmp_gt_i32 s4, s1
-; GFX9-NEXT: s_cselect_b32 s1, s4, s1
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s3, s1
-; GFX9-NEXT: s_sext_i32_i16 s3, s1
-; GFX9-NEXT: s_sext_i32_i16 s4, s2
-; GFX9-NEXT: s_ashr_i32 s1, s1, 16
-; GFX9-NEXT: s_ashr_i32 s2, s2, 16
-; GFX9-NEXT: s_cmp_lt_i32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s3, s3, s4
-; GFX9-NEXT: s_cmp_lt_i32 s1, s2
-; GFX9-NEXT: s_cselect_b32 s1, s1, s2
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s3, s1
-; GFX9-NEXT: s_lshr_b32 s2, s0, 16
-; GFX9-NEXT: s_lshr_b32 s3, s1, 16
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
-; GFX9-NEXT: s_sub_i32 s1, s2, s3
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v2i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sext_i32_i16 s2, s0
-; GFX10-NEXT: s_sext_i32_i16 s3, -1
-; GFX10-NEXT: s_ashr_i32 s4, s0, 16
-; GFX10-NEXT: s_cmp_gt_i32 s2, s3
+; GFX10-NEXT: v_pk_sub_i16 v0, s0, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s5, s2, s3
-; GFX10-NEXT: s_cmp_gt_i32 s4, -1
-; GFX10-NEXT: s_cselect_b32 s6, s4, -1
-; GFX10-NEXT: s_pack_ll_b32_b16 s5, s5, s6
-; GFX10-NEXT: s_sext_i32_i16 s6, s1
-; GFX10-NEXT: s_lshr_b32 s7, s5, 16
-; GFX10-NEXT: s_sub_i32 s5, s5, 0x7fff7fff
-; GFX10-NEXT: s_sub_i32 s7, s7, 0x7fff
-; GFX10-NEXT: s_cmp_lt_i32 s2, s3
-; GFX10-NEXT: s_pack_ll_b32_b16 s5, s5, s7
-; GFX10-NEXT: s_cselect_b32 s2, s2, s3
-; GFX10-NEXT: s_cmp_lt_i32 s4, -1
-; GFX10-NEXT: s_sext_i32_i16 s3, s5
-; GFX10-NEXT: s_cselect_b32 s4, s4, -1
-; GFX10-NEXT: s_ashr_i32 s5, s5, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4
-; GFX10-NEXT: s_ashr_i32 s1, s1, 16
-; GFX10-NEXT: s_lshr_b32 s4, s2, 16
-; GFX10-NEXT: s_sub_i32 s2, s2, 0x80008000
-; GFX10-NEXT: s_sub_i32 s4, s4, 0x8000
-; GFX10-NEXT: s_cmp_gt_i32 s3, s6
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s4
-; GFX10-NEXT: s_cselect_b32 s3, s3, s6
-; GFX10-NEXT: s_cmp_gt_i32 s5, s1
-; GFX10-NEXT: s_sext_i32_i16 s4, s2
-; GFX10-NEXT: s_cselect_b32 s1, s5, s1
-; GFX10-NEXT: s_ashr_i32 s2, s2, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s3, s1
-; GFX10-NEXT: s_sext_i32_i16 s3, s1
-; GFX10-NEXT: s_ashr_i32 s1, s1, 16
-; GFX10-NEXT: s_cmp_lt_i32 s3, s4
-; GFX10-NEXT: s_cselect_b32 s3, s3, s4
-; GFX10-NEXT: s_cmp_lt_i32 s1, s2
-; GFX10-NEXT: s_cselect_b32 s1, s1, s2
-; GFX10-NEXT: s_lshr_b32 s2, s0, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s3, s1
-; GFX10-NEXT: s_lshr_b32 s3, s1, 16
-; GFX10-NEXT: s_sub_i32 s0, s0, s1
-; GFX10-NEXT: s_sub_i32 s1, s2, s3
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to i32
@@ -4795,59 +3239,13 @@ define amdgpu_ps float @ssubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
;
; GFX9-LABEL: ssubsat_v2i16_sv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sext_i32_i16 s1, s0
-; GFX9-NEXT: s_ashr_i32 s2, s0, 16
-; GFX9-NEXT: s_sext_i32_i16 s3, -1
-; GFX9-NEXT: s_cmp_gt_i32 s1, s3
-; GFX9-NEXT: s_cselect_b32 s4, s1, s3
-; GFX9-NEXT: s_cmp_gt_i32 s2, -1
-; GFX9-NEXT: s_cselect_b32 s5, s2, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_lshr_b32 s5, s4, 16
-; GFX9-NEXT: s_sub_i32 s4, s4, 0x7fff7fff
-; GFX9-NEXT: s_sub_i32 s5, s5, 0x7fff
-; GFX9-NEXT: s_cmp_lt_i32 s1, s3
-; GFX9-NEXT: s_cselect_b32 s1, s1, s3
-; GFX9-NEXT: s_cmp_lt_i32 s2, -1
-; GFX9-NEXT: s_cselect_b32 s2, s2, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2
-; GFX9-NEXT: s_lshr_b32 s2, s1, 16
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_sub_i32 s1, s1, 0x80008000
-; GFX9-NEXT: s_sub_i32 s2, s2, 0x8000
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2
-; GFX9-NEXT: v_pk_max_i16 v0, s4, v0
-; GFX9-NEXT: v_pk_min_i16 v0, v0, s1
-; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0
+; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_v2i16_sv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sext_i32_i16 s1, s0
-; GFX10-NEXT: s_sext_i32_i16 s2, -1
-; GFX10-NEXT: s_ashr_i32 s3, s0, 16
-; GFX10-NEXT: s_cmp_gt_i32 s1, s2
+; GFX10-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s4, s1, s2
-; GFX10-NEXT: s_cmp_gt_i32 s3, -1
-; GFX10-NEXT: s_cselect_b32 s5, s3, -1
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX10-NEXT: s_lshr_b32 s5, s4, 16
-; GFX10-NEXT: s_sub_i32 s4, s4, 0x7fff7fff
-; GFX10-NEXT: s_sub_i32 s5, s5, 0x7fff
-; GFX10-NEXT: s_cmp_lt_i32 s1, s2
-; GFX10-NEXT: s_cselect_b32 s1, s1, s2
-; GFX10-NEXT: s_cmp_lt_i32 s3, -1
-; GFX10-NEXT: s_cselect_b32 s2, s3, -1
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s2
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s4, s5
-; GFX10-NEXT: s_lshr_b32 s3, s1, 16
-; GFX10-NEXT: v_pk_max_i16 v0, s2, v0
-; GFX10-NEXT: s_sub_i32 s1, s1, 0x80008000
-; GFX10-NEXT: s_sub_i32 s2, s3, 0x8000
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s2
-; GFX10-NEXT: v_pk_min_i16 v0, v0, s1
-; GFX10-NEXT: v_pk_sub_i16 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
@@ -4911,27 +3309,13 @@ define amdgpu_ps float @ssubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
;
; GFX9-LABEL: ssubsat_v2i16_vs:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_pk_max_i16 v1, v0, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fff7fff
-; GFX9-NEXT: v_pk_sub_i16 v1, v1, v2
-; GFX9-NEXT: v_pk_min_i16 v2, v0, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x80008000
-; GFX9-NEXT: v_pk_sub_i16 v2, v2, v3
-; GFX9-NEXT: v_pk_max_i16 v1, v1, s0
-; GFX9-NEXT: v_pk_min_i16 v1, v1, v2
-; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1
+; GFX9-NEXT: v_pk_sub_i16 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_v2i16_vs:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_max_i16 v1, v0, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_min_i16 v2, v0, -1 op_sel_hi:[1,0]
+; GFX10-NEXT: v_pk_sub_i16 v0, v0, s0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_sub_i16 v1, v1, 0x7fff7fff
-; GFX10-NEXT: v_pk_sub_i16 v2, v2, 0x80008000
-; GFX10-NEXT: v_pk_max_i16 v1, v1, s0
-; GFX10-NEXT: v_pk_min_i16 v1, v1, v2
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
@@ -5050,43 +3434,17 @@ define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX9-LABEL: v_ssubsat_v4i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_max_i16 v4, v0, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_mov_b32_e32 v5, 0x7fff7fff
-; GFX9-NEXT: v_pk_sub_i16 v4, v4, v5
-; GFX9-NEXT: v_pk_min_i16 v6, v0, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_mov_b32_e32 v7, 0x80008000
-; GFX9-NEXT: v_pk_max_i16 v2, v4, v2
-; GFX9-NEXT: v_pk_sub_i16 v6, v6, v7
-; GFX9-NEXT: v_pk_min_i16 v2, v2, v6
-; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2
-; GFX9-NEXT: v_pk_max_i16 v2, v1, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_sub_i16 v2, v2, v5
-; GFX9-NEXT: v_pk_min_i16 v4, v1, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_sub_i16 v4, v4, v7
-; GFX9-NEXT: v_pk_max_i16 v2, v2, v3
-; GFX9-NEXT: v_pk_min_i16 v2, v2, v4
-; GFX9-NEXT: v_pk_sub_i16 v1, v1, v2
+; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2 clamp
+; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v4i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_max_i16 v4, v0, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_max_i16 v5, v1, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_min_i16 v6, v0, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_min_i16 v7, v1, -1 op_sel_hi:[1,0]
+; GFX10-NEXT: v_pk_sub_i16 v0, v0, v2 clamp
+; GFX10-NEXT: v_pk_sub_i16 v1, v1, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_sub_i16 v4, v4, 0x7fff7fff
-; GFX10-NEXT: v_pk_sub_i16 v5, v5, 0x7fff7fff
-; GFX10-NEXT: v_pk_sub_i16 v6, v6, 0x80008000
-; GFX10-NEXT: v_pk_sub_i16 v7, v7, 0x80008000
-; GFX10-NEXT: v_pk_max_i16 v11, v4, v2
-; GFX10-NEXT: v_pk_max_i16 v10, v5, v3
-; GFX10-NEXT: v_pk_min_i16 v2, v11, v6
-; GFX10-NEXT: v_pk_min_i16 v3, v10, v7
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, v2
-; GFX10-NEXT: v_pk_sub_i16 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x float>
@@ -5250,193 +3608,21 @@ define amdgpu_ps <2 x i32> @s_ssubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inre
;
; GFX9-LABEL: s_ssubsat_v4i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sext_i32_i16 s6, s0
-; GFX9-NEXT: s_ashr_i32 s7, s0, 16
-; GFX9-NEXT: s_sext_i32_i16 s8, -1
-; GFX9-NEXT: s_cmp_gt_i32 s6, s8
-; GFX9-NEXT: s_cselect_b32 s9, s6, s8
-; GFX9-NEXT: s_cmp_gt_i32 s7, -1
-; GFX9-NEXT: s_cselect_b32 s10, s7, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s10
-; GFX9-NEXT: s_mov_b32 s4, 0x7fff7fff
-; GFX9-NEXT: s_lshr_b32 s10, s9, 16
-; GFX9-NEXT: s_movk_i32 s11, 0x7fff
-; GFX9-NEXT: s_sub_i32 s9, s9, s4
-; GFX9-NEXT: s_sub_i32 s10, s10, s11
-; GFX9-NEXT: s_cmp_lt_i32 s6, s8
-; GFX9-NEXT: s_cselect_b32 s6, s6, s8
-; GFX9-NEXT: s_cmp_lt_i32 s7, -1
-; GFX9-NEXT: s_cselect_b32 s7, s7, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s7
-; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s10
-; GFX9-NEXT: s_mov_b32 s5, 0x80008000
-; GFX9-NEXT: s_lshr_b32 s7, s6, 16
-; GFX9-NEXT: s_mov_b32 s10, 0x8000
-; GFX9-NEXT: s_sub_i32 s6, s6, s5
-; GFX9-NEXT: s_sub_i32 s7, s7, s10
-; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s7
-; GFX9-NEXT: s_sext_i32_i16 s7, s9
-; GFX9-NEXT: s_sext_i32_i16 s12, s2
-; GFX9-NEXT: s_ashr_i32 s9, s9, 16
-; GFX9-NEXT: s_ashr_i32 s2, s2, 16
-; GFX9-NEXT: s_cmp_gt_i32 s7, s12
-; GFX9-NEXT: s_cselect_b32 s7, s7, s12
-; GFX9-NEXT: s_cmp_gt_i32 s9, s2
-; GFX9-NEXT: s_cselect_b32 s2, s9, s2
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s7, s2
-; GFX9-NEXT: s_sext_i32_i16 s7, s2
-; GFX9-NEXT: s_sext_i32_i16 s9, s6
-; GFX9-NEXT: s_ashr_i32 s2, s2, 16
-; GFX9-NEXT: s_ashr_i32 s6, s6, 16
-; GFX9-NEXT: s_cmp_lt_i32 s7, s9
-; GFX9-NEXT: s_cselect_b32 s7, s7, s9
-; GFX9-NEXT: s_cmp_lt_i32 s2, s6
-; GFX9-NEXT: s_cselect_b32 s2, s2, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s7, s2
-; GFX9-NEXT: s_lshr_b32 s6, s0, 16
-; GFX9-NEXT: s_lshr_b32 s7, s2, 16
-; GFX9-NEXT: s_sub_i32 s0, s0, s2
-; GFX9-NEXT: s_sub_i32 s2, s6, s7
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX9-NEXT: s_sext_i32_i16 s2, s1
-; GFX9-NEXT: s_ashr_i32 s6, s1, 16
-; GFX9-NEXT: s_cmp_gt_i32 s2, s8
-; GFX9-NEXT: s_cselect_b32 s7, s2, s8
-; GFX9-NEXT: s_cmp_gt_i32 s6, -1
-; GFX9-NEXT: s_cselect_b32 s9, s6, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s7, s7, s9
-; GFX9-NEXT: s_lshr_b32 s9, s7, 16
-; GFX9-NEXT: s_sub_i32 s4, s7, s4
-; GFX9-NEXT: s_sub_i32 s7, s9, s11
-; GFX9-NEXT: s_cmp_lt_i32 s2, s8
-; GFX9-NEXT: s_cselect_b32 s2, s2, s8
-; GFX9-NEXT: s_cmp_lt_i32 s6, -1
-; GFX9-NEXT: s_cselect_b32 s6, s6, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s6
-; GFX9-NEXT: s_lshr_b32 s6, s2, 16
-; GFX9-NEXT: s_sub_i32 s2, s2, s5
-; GFX9-NEXT: s_sub_i32 s5, s6, s10
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s7
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s5
-; GFX9-NEXT: s_sext_i32_i16 s5, s4
-; GFX9-NEXT: s_sext_i32_i16 s6, s3
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_ashr_i32 s3, s3, 16
-; GFX9-NEXT: s_cmp_gt_i32 s5, s6
-; GFX9-NEXT: s_cselect_b32 s5, s5, s6
-; GFX9-NEXT: s_cmp_gt_i32 s4, s3
-; GFX9-NEXT: s_cselect_b32 s3, s4, s3
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s5, s3
-; GFX9-NEXT: s_sext_i32_i16 s4, s3
-; GFX9-NEXT: s_sext_i32_i16 s5, s2
-; GFX9-NEXT: s_ashr_i32 s3, s3, 16
-; GFX9-NEXT: s_ashr_i32 s2, s2, 16
-; GFX9-NEXT: s_cmp_lt_i32 s4, s5
-; GFX9-NEXT: s_cselect_b32 s4, s4, s5
-; GFX9-NEXT: s_cmp_lt_i32 s3, s2
-; GFX9-NEXT: s_cselect_b32 s2, s3, s2
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s4, s2
-; GFX9-NEXT: s_lshr_b32 s3, s1, 16
-; GFX9-NEXT: s_lshr_b32 s4, s2, 16
-; GFX9-NEXT: s_sub_i32 s1, s1, s2
-; GFX9-NEXT: s_sub_i32 s2, s3, s4
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_pk_sub_i16 v1, s1, v1 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v4i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sext_i32_i16 s4, s0
-; GFX10-NEXT: s_sext_i32_i16 s5, -1
-; GFX10-NEXT: s_ashr_i32 s6, s0, 16
-; GFX10-NEXT: s_cmp_gt_i32 s4, s5
-; GFX10-NEXT: s_movk_i32 s10, 0x7fff
-; GFX10-NEXT: s_cselect_b32 s7, s4, s5
-; GFX10-NEXT: s_cmp_gt_i32 s6, -1
-; GFX10-NEXT: s_mov_b32 s11, 0x80008000
-; GFX10-NEXT: s_cselect_b32 s8, s6, -1
-; GFX10-NEXT: s_sext_i32_i16 s13, s2
-; GFX10-NEXT: s_pack_ll_b32_b16 s7, s7, s8
-; GFX10-NEXT: s_mov_b32 s8, 0x7fff7fff
-; GFX10-NEXT: s_lshr_b32 s9, s7, 16
-; GFX10-NEXT: s_sub_i32 s7, s7, s8
-; GFX10-NEXT: s_sub_i32 s9, s9, s10
-; GFX10-NEXT: s_cmp_lt_i32 s4, s5
+; GFX10-NEXT: v_pk_sub_i16 v0, s0, s2 clamp
+; GFX10-NEXT: v_pk_sub_i16 v1, s1, s3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s4, s4, s5
-; GFX10-NEXT: s_cmp_lt_i32 s6, -1
-; GFX10-NEXT: s_cselect_b32 s6, s6, -1
-; GFX10-NEXT: s_ashr_i32 s2, s2, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s6
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s7, s9
-; GFX10-NEXT: s_lshr_b32 s7, s4, 16
-; GFX10-NEXT: s_mov_b32 s9, 0x8000
-; GFX10-NEXT: s_sext_i32_i16 s12, s6
-; GFX10-NEXT: s_sub_i32 s4, s4, s11
-; GFX10-NEXT: s_sub_i32 s7, s7, s9
-; GFX10-NEXT: s_ashr_i32 s6, s6, 16
-; GFX10-NEXT: s_cmp_gt_i32 s12, s13
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s7
-; GFX10-NEXT: s_cselect_b32 s12, s12, s13
-; GFX10-NEXT: s_cmp_gt_i32 s6, s2
-; GFX10-NEXT: s_sext_i32_i16 s7, s4
-; GFX10-NEXT: s_cselect_b32 s2, s6, s2
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s12, s2
-; GFX10-NEXT: s_sext_i32_i16 s6, s2
-; GFX10-NEXT: s_ashr_i32 s2, s2, 16
-; GFX10-NEXT: s_cmp_lt_i32 s6, s7
-; GFX10-NEXT: s_cselect_b32 s6, s6, s7
-; GFX10-NEXT: s_cmp_lt_i32 s2, s4
-; GFX10-NEXT: s_cselect_b32 s2, s2, s4
-; GFX10-NEXT: s_lshr_b32 s4, s0, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s6, s2
-; GFX10-NEXT: s_lshr_b32 s6, s2, 16
-; GFX10-NEXT: s_sub_i32 s0, s0, s2
-; GFX10-NEXT: s_sub_i32 s2, s4, s6
-; GFX10-NEXT: s_sext_i32_i16 s4, s1
-; GFX10-NEXT: s_ashr_i32 s6, s1, 16
-; GFX10-NEXT: s_cmp_gt_i32 s4, s5
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX10-NEXT: s_cselect_b32 s7, s4, s5
-; GFX10-NEXT: s_cmp_gt_i32 s6, -1
-; GFX10-NEXT: s_cselect_b32 s12, s6, -1
-; GFX10-NEXT: s_pack_ll_b32_b16 s7, s7, s12
-; GFX10-NEXT: s_lshr_b32 s12, s7, 16
-; GFX10-NEXT: s_sub_i32 s7, s7, s8
-; GFX10-NEXT: s_sub_i32 s8, s12, s10
-; GFX10-NEXT: s_cmp_lt_i32 s4, s5
-; GFX10-NEXT: s_cselect_b32 s4, s4, s5
-; GFX10-NEXT: s_cmp_lt_i32 s6, -1
-; GFX10-NEXT: s_cselect_b32 s5, s6, -1
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX10-NEXT: s_pack_ll_b32_b16 s5, s7, s8
-; GFX10-NEXT: s_lshr_b32 s6, s4, 16
-; GFX10-NEXT: s_sext_i32_i16 s7, s5
-; GFX10-NEXT: s_sext_i32_i16 s8, s3
-; GFX10-NEXT: s_sub_i32 s4, s4, s11
-; GFX10-NEXT: s_sub_i32 s6, s6, s9
-; GFX10-NEXT: s_ashr_i32 s5, s5, 16
-; GFX10-NEXT: s_ashr_i32 s3, s3, 16
-; GFX10-NEXT: s_cmp_gt_i32 s7, s8
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s6
-; GFX10-NEXT: s_cselect_b32 s7, s7, s8
-; GFX10-NEXT: s_cmp_gt_i32 s5, s3
-; GFX10-NEXT: s_sext_i32_i16 s6, s4
-; GFX10-NEXT: s_cselect_b32 s3, s5, s3
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s7, s3
-; GFX10-NEXT: s_sext_i32_i16 s5, s3
-; GFX10-NEXT: s_ashr_i32 s3, s3, 16
-; GFX10-NEXT: s_cmp_lt_i32 s5, s6
-; GFX10-NEXT: s_cselect_b32 s5, s5, s6
-; GFX10-NEXT: s_cmp_lt_i32 s3, s4
-; GFX10-NEXT: s_cselect_b32 s3, s3, s4
-; GFX10-NEXT: s_lshr_b32 s4, s1, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s5, s3
-; GFX10-NEXT: s_lshr_b32 s5, s3, 16
-; GFX10-NEXT: s_sub_i32 s1, s1, s3
-; GFX10-NEXT: s_sub_i32 s3, s4, s5
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x i32>
@@ -5597,57 +3783,19 @@ define <3 x float> @v_ssubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX9-LABEL: v_ssubsat_v6i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_max_i16 v6, v0, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_mov_b32_e32 v7, 0x7fff7fff
-; GFX9-NEXT: v_pk_sub_i16 v6, v6, v7
-; GFX9-NEXT: v_pk_min_i16 v8, v0, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_mov_b32_e32 v9, 0x80008000
-; GFX9-NEXT: v_pk_max_i16 v3, v6, v3
-; GFX9-NEXT: v_pk_sub_i16 v8, v8, v9
-; GFX9-NEXT: v_pk_min_i16 v3, v3, v8
-; GFX9-NEXT: v_pk_sub_i16 v0, v0, v3
-; GFX9-NEXT: v_pk_max_i16 v3, v1, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_sub_i16 v3, v3, v7
-; GFX9-NEXT: v_pk_min_i16 v6, v1, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_max_i16 v3, v3, v4
-; GFX9-NEXT: v_pk_sub_i16 v6, v6, v9
-; GFX9-NEXT: v_pk_min_i16 v3, v3, v6
-; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3
-; GFX9-NEXT: v_pk_max_i16 v3, v2, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_sub_i16 v3, v3, v7
-; GFX9-NEXT: v_pk_min_i16 v4, v2, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_sub_i16 v4, v4, v9
-; GFX9-NEXT: v_pk_max_i16 v3, v3, v5
-; GFX9-NEXT: v_pk_min_i16 v3, v3, v4
-; GFX9-NEXT: v_pk_sub_i16 v2, v2, v3
+; GFX9-NEXT: v_pk_sub_i16 v0, v0, v3 clamp
+; GFX9-NEXT: v_pk_sub_i16 v1, v1, v4 clamp
+; GFX9-NEXT: v_pk_sub_i16 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v6i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_max_i16 v6, v0, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_max_i16 v8, v1, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_max_i16 v9, v2, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_min_i16 v7, v0, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_min_i16 v10, v1, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_sub_i16 v6, v6, 0x7fff7fff
-; GFX10-NEXT: v_pk_sub_i16 v15, v8, 0x7fff7fff
-; GFX10-NEXT: v_pk_min_i16 v11, v2, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_sub_i16 v19, v9, 0x7fff7fff
-; GFX10-NEXT: v_pk_sub_i16 v7, v7, 0x80008000
-; GFX10-NEXT: v_pk_max_i16 v14, v6, v3
-; GFX10-NEXT: v_pk_sub_i16 v6, v10, 0x80008000
-; GFX10-NEXT: v_pk_max_i16 v4, v15, v4
-; GFX10-NEXT: v_pk_sub_i16 v8, v11, 0x80008000
-; GFX10-NEXT: v_pk_max_i16 v5, v19, v5
-; GFX10-NEXT: v_pk_min_i16 v3, v14, v7
+; GFX10-NEXT: v_pk_sub_i16 v0, v0, v3 clamp
+; GFX10-NEXT: v_pk_sub_i16 v1, v1, v4 clamp
+; GFX10-NEXT: v_pk_sub_i16 v2, v2, v5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_min_i16 v4, v4, v6
-; GFX10-NEXT: v_pk_min_i16 v5, v5, v8
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, v3
-; GFX10-NEXT: v_pk_sub_i16 v1, v1, v4
-; GFX10-NEXT: v_pk_sub_i16 v2, v2, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x float>
@@ -5881,279 +4029,26 @@ define amdgpu_ps <3 x i32> @s_ssubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inre
;
; GFX9-LABEL: s_ssubsat_v6i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sext_i32_i16 s8, s0
-; GFX9-NEXT: s_ashr_i32 s9, s0, 16
-; GFX9-NEXT: s_sext_i32_i16 s10, -1
-; GFX9-NEXT: s_cmp_gt_i32 s8, s10
-; GFX9-NEXT: s_cselect_b32 s11, s8, s10
-; GFX9-NEXT: s_cmp_gt_i32 s9, -1
-; GFX9-NEXT: s_cselect_b32 s12, s9, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s12
-; GFX9-NEXT: s_mov_b32 s6, 0x7fff7fff
-; GFX9-NEXT: s_lshr_b32 s12, s11, 16
-; GFX9-NEXT: s_movk_i32 s13, 0x7fff
-; GFX9-NEXT: s_sub_i32 s11, s11, s6
-; GFX9-NEXT: s_sub_i32 s12, s12, s13
-; GFX9-NEXT: s_cmp_lt_i32 s8, s10
-; GFX9-NEXT: s_cselect_b32 s8, s8, s10
-; GFX9-NEXT: s_cmp_lt_i32 s9, -1
-; GFX9-NEXT: s_cselect_b32 s9, s9, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s9
-; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s12
-; GFX9-NEXT: s_mov_b32 s7, 0x80008000
-; GFX9-NEXT: s_lshr_b32 s9, s8, 16
-; GFX9-NEXT: s_mov_b32 s12, 0x8000
-; GFX9-NEXT: s_sub_i32 s8, s8, s7
-; GFX9-NEXT: s_sub_i32 s9, s9, s12
-; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s9
-; GFX9-NEXT: s_sext_i32_i16 s9, s11
-; GFX9-NEXT: s_sext_i32_i16 s14, s3
-; GFX9-NEXT: s_ashr_i32 s11, s11, 16
-; GFX9-NEXT: s_ashr_i32 s3, s3, 16
-; GFX9-NEXT: s_cmp_gt_i32 s9, s14
-; GFX9-NEXT: s_cselect_b32 s9, s9, s14
-; GFX9-NEXT: s_cmp_gt_i32 s11, s3
-; GFX9-NEXT: s_cselect_b32 s3, s11, s3
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s9, s3
-; GFX9-NEXT: s_sext_i32_i16 s9, s3
-; GFX9-NEXT: s_sext_i32_i16 s11, s8
-; GFX9-NEXT: s_ashr_i32 s3, s3, 16
-; GFX9-NEXT: s_ashr_i32 s8, s8, 16
-; GFX9-NEXT: s_cmp_lt_i32 s9, s11
-; GFX9-NEXT: s_cselect_b32 s9, s9, s11
-; GFX9-NEXT: s_cmp_lt_i32 s3, s8
-; GFX9-NEXT: s_cselect_b32 s3, s3, s8
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s9, s3
-; GFX9-NEXT: s_lshr_b32 s8, s0, 16
-; GFX9-NEXT: s_lshr_b32 s9, s3, 16
-; GFX9-NEXT: s_sub_i32 s0, s0, s3
-; GFX9-NEXT: s_sub_i32 s3, s8, s9
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s3
-; GFX9-NEXT: s_sext_i32_i16 s3, s1
-; GFX9-NEXT: s_ashr_i32 s8, s1, 16
-; GFX9-NEXT: s_cmp_gt_i32 s3, s10
-; GFX9-NEXT: s_cselect_b32 s9, s3, s10
-; GFX9-NEXT: s_cmp_gt_i32 s8, -1
-; GFX9-NEXT: s_cselect_b32 s11, s8, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s11
-; GFX9-NEXT: s_lshr_b32 s11, s9, 16
-; GFX9-NEXT: s_sub_i32 s9, s9, s6
-; GFX9-NEXT: s_sub_i32 s11, s11, s13
-; GFX9-NEXT: s_cmp_lt_i32 s3, s10
-; GFX9-NEXT: s_cselect_b32 s3, s3, s10
-; GFX9-NEXT: s_cmp_lt_i32 s8, -1
-; GFX9-NEXT: s_cselect_b32 s8, s8, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s8
-; GFX9-NEXT: s_lshr_b32 s8, s3, 16
-; GFX9-NEXT: s_pack_ll_b32_b16 s9, s9, s11
-; GFX9-NEXT: s_sub_i32 s3, s3, s7
-; GFX9-NEXT: s_sub_i32 s8, s8, s12
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s8
-; GFX9-NEXT: s_sext_i32_i16 s8, s9
-; GFX9-NEXT: s_sext_i32_i16 s11, s4
-; GFX9-NEXT: s_ashr_i32 s9, s9, 16
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_cmp_gt_i32 s8, s11
-; GFX9-NEXT: s_cselect_b32 s8, s8, s11
-; GFX9-NEXT: s_cmp_gt_i32 s9, s4
-; GFX9-NEXT: s_cselect_b32 s4, s9, s4
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s8, s4
-; GFX9-NEXT: s_sext_i32_i16 s8, s4
-; GFX9-NEXT: s_sext_i32_i16 s9, s3
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_ashr_i32 s3, s3, 16
-; GFX9-NEXT: s_cmp_lt_i32 s8, s9
-; GFX9-NEXT: s_cselect_b32 s8, s8, s9
-; GFX9-NEXT: s_cmp_lt_i32 s4, s3
-; GFX9-NEXT: s_cselect_b32 s3, s4, s3
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s8, s3
-; GFX9-NEXT: s_lshr_b32 s4, s1, 16
-; GFX9-NEXT: s_lshr_b32 s8, s3, 16
-; GFX9-NEXT: s_sub_i32 s1, s1, s3
-; GFX9-NEXT: s_sub_i32 s3, s4, s8
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3
-; GFX9-NEXT: s_sext_i32_i16 s3, s2
-; GFX9-NEXT: s_ashr_i32 s4, s2, 16
-; GFX9-NEXT: s_cmp_gt_i32 s3, s10
-; GFX9-NEXT: s_cselect_b32 s8, s3, s10
-; GFX9-NEXT: s_cmp_gt_i32 s4, -1
-; GFX9-NEXT: s_cselect_b32 s9, s4, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s8, s8, s9
-; GFX9-NEXT: s_lshr_b32 s9, s8, 16
-; GFX9-NEXT: s_sub_i32 s6, s8, s6
-; GFX9-NEXT: s_sub_i32 s8, s9, s13
-; GFX9-NEXT: s_cmp_lt_i32 s3, s10
-; GFX9-NEXT: s_cselect_b32 s3, s3, s10
-; GFX9-NEXT: s_cmp_lt_i32 s4, -1
-; GFX9-NEXT: s_cselect_b32 s4, s4, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4
-; GFX9-NEXT: s_lshr_b32 s4, s3, 16
-; GFX9-NEXT: s_sub_i32 s3, s3, s7
-; GFX9-NEXT: s_sub_i32 s4, s4, s12
-; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s8
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4
-; GFX9-NEXT: s_sext_i32_i16 s4, s6
-; GFX9-NEXT: s_sext_i32_i16 s7, s5
-; GFX9-NEXT: s_ashr_i32 s6, s6, 16
-; GFX9-NEXT: s_ashr_i32 s5, s5, 16
-; GFX9-NEXT: s_cmp_gt_i32 s4, s7
-; GFX9-NEXT: s_cselect_b32 s4, s4, s7
-; GFX9-NEXT: s_cmp_gt_i32 s6, s5
-; GFX9-NEXT: s_cselect_b32 s5, s6, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_sext_i32_i16 s5, s4
-; GFX9-NEXT: s_sext_i32_i16 s6, s3
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_ashr_i32 s3, s3, 16
-; GFX9-NEXT: s_cmp_lt_i32 s5, s6
-; GFX9-NEXT: s_cselect_b32 s5, s5, s6
-; GFX9-NEXT: s_cmp_lt_i32 s4, s3
-; GFX9-NEXT: s_cselect_b32 s3, s4, s3
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s5, s3
-; GFX9-NEXT: s_lshr_b32 s4, s2, 16
-; GFX9-NEXT: s_lshr_b32 s5, s3, 16
-; GFX9-NEXT: s_sub_i32 s2, s2, s3
-; GFX9-NEXT: s_sub_i32 s3, s4, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3
+; GFX9-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_pk_sub_i16 v1, s1, v1 clamp
+; GFX9-NEXT: v_pk_sub_i16 v2, s2, v2 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v6i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sext_i32_i16 s6, s0
-; GFX10-NEXT: s_sext_i32_i16 s7, -1
-; GFX10-NEXT: s_ashr_i32 s8, s0, 16
-; GFX10-NEXT: s_cmp_gt_i32 s6, s7
-; GFX10-NEXT: s_movk_i32 s12, 0x7fff
-; GFX10-NEXT: s_cselect_b32 s9, s6, s7
-; GFX10-NEXT: s_cmp_gt_i32 s8, -1
-; GFX10-NEXT: s_mov_b32 s13, 0x80008000
-; GFX10-NEXT: s_cselect_b32 s10, s8, -1
-; GFX10-NEXT: s_sext_i32_i16 s15, s3
-; GFX10-NEXT: s_pack_ll_b32_b16 s9, s9, s10
-; GFX10-NEXT: s_mov_b32 s10, 0x7fff7fff
-; GFX10-NEXT: s_lshr_b32 s11, s9, 16
-; GFX10-NEXT: s_sub_i32 s9, s9, s10
-; GFX10-NEXT: s_sub_i32 s11, s11, s12
-; GFX10-NEXT: s_cmp_lt_i32 s6, s7
+; GFX10-NEXT: v_pk_sub_i16 v0, s0, s3 clamp
+; GFX10-NEXT: v_pk_sub_i16 v1, s1, s4 clamp
+; GFX10-NEXT: v_pk_sub_i16 v2, s2, s5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s6, s6, s7
-; GFX10-NEXT: s_cmp_lt_i32 s8, -1
-; GFX10-NEXT: s_cselect_b32 s8, s8, -1
-; GFX10-NEXT: s_ashr_i32 s3, s3, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s8
-; GFX10-NEXT: s_pack_ll_b32_b16 s8, s9, s11
-; GFX10-NEXT: s_lshr_b32 s9, s6, 16
-; GFX10-NEXT: s_mov_b32 s11, 0x8000
-; GFX10-NEXT: s_sext_i32_i16 s14, s8
-; GFX10-NEXT: s_sub_i32 s6, s6, s13
-; GFX10-NEXT: s_sub_i32 s9, s9, s11
-; GFX10-NEXT: s_ashr_i32 s8, s8, 16
-; GFX10-NEXT: s_cmp_gt_i32 s14, s15
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s9
-; GFX10-NEXT: s_cselect_b32 s14, s14, s15
-; GFX10-NEXT: s_cmp_gt_i32 s8, s3
-; GFX10-NEXT: s_sext_i32_i16 s9, s6
-; GFX10-NEXT: s_cselect_b32 s3, s8, s3
-; GFX10-NEXT: s_ashr_i32 s6, s6, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s14, s3
-; GFX10-NEXT: s_sext_i32_i16 s15, s4
-; GFX10-NEXT: s_sext_i32_i16 s8, s3
-; GFX10-NEXT: s_ashr_i32 s3, s3, 16
-; GFX10-NEXT: s_cmp_lt_i32 s8, s9
-; GFX10-NEXT: s_cselect_b32 s8, s8, s9
-; GFX10-NEXT: s_cmp_lt_i32 s3, s6
-; GFX10-NEXT: s_cselect_b32 s3, s3, s6
-; GFX10-NEXT: s_lshr_b32 s6, s0, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s8, s3
-; GFX10-NEXT: s_lshr_b32 s8, s3, 16
-; GFX10-NEXT: s_sub_i32 s0, s0, s3
-; GFX10-NEXT: s_sub_i32 s3, s6, s8
-; GFX10-NEXT: s_sext_i32_i16 s6, s1
-; GFX10-NEXT: s_ashr_i32 s8, s1, 16
-; GFX10-NEXT: s_cmp_gt_i32 s6, s7
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s3
-; GFX10-NEXT: s_cselect_b32 s9, s6, s7
-; GFX10-NEXT: s_cmp_gt_i32 s8, -1
-; GFX10-NEXT: s_cselect_b32 s14, s8, -1
-; GFX10-NEXT: s_pack_ll_b32_b16 s9, s9, s14
-; GFX10-NEXT: s_lshr_b32 s14, s9, 16
-; GFX10-NEXT: s_sub_i32 s9, s9, s10
-; GFX10-NEXT: s_sub_i32 s14, s14, s12
-; GFX10-NEXT: s_cmp_lt_i32 s6, s7
-; GFX10-NEXT: s_cselect_b32 s6, s6, s7
-; GFX10-NEXT: s_cmp_lt_i32 s8, -1
-; GFX10-NEXT: s_cselect_b32 s8, s8, -1
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s8
-; GFX10-NEXT: s_pack_ll_b32_b16 s8, s9, s14
-; GFX10-NEXT: s_lshr_b32 s9, s6, 16
-; GFX10-NEXT: s_sext_i32_i16 s14, s8
-; GFX10-NEXT: s_sub_i32 s6, s6, s13
-; GFX10-NEXT: s_sub_i32 s9, s9, s11
-; GFX10-NEXT: s_ashr_i32 s8, s8, 16
-; GFX10-NEXT: s_cmp_gt_i32 s14, s15
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s9
-; GFX10-NEXT: s_cselect_b32 s14, s14, s15
-; GFX10-NEXT: s_cmp_gt_i32 s8, s4
-; GFX10-NEXT: s_sext_i32_i16 s9, s6
-; GFX10-NEXT: s_cselect_b32 s4, s8, s4
-; GFX10-NEXT: s_ashr_i32 s6, s6, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s14, s4
-; GFX10-NEXT: s_sext_i32_i16 s8, s4
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_cmp_lt_i32 s8, s9
-; GFX10-NEXT: s_cselect_b32 s8, s8, s9
-; GFX10-NEXT: s_cmp_lt_i32 s4, s6
-; GFX10-NEXT: s_cselect_b32 s4, s4, s6
-; GFX10-NEXT: s_lshr_b32 s6, s1, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s8, s4
-; GFX10-NEXT: s_lshr_b32 s8, s4, 16
-; GFX10-NEXT: s_sub_i32 s1, s1, s4
-; GFX10-NEXT: s_sub_i32 s4, s6, s8
-; GFX10-NEXT: s_sext_i32_i16 s6, s2
-; GFX10-NEXT: s_ashr_i32 s8, s2, 16
-; GFX10-NEXT: s_cmp_gt_i32 s6, s7
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s4
-; GFX10-NEXT: s_cselect_b32 s9, s6, s7
-; GFX10-NEXT: s_cmp_gt_i32 s8, -1
-; GFX10-NEXT: s_cselect_b32 s14, s8, -1
-; GFX10-NEXT: s_pack_ll_b32_b16 s9, s9, s14
-; GFX10-NEXT: s_lshr_b32 s14, s9, 16
-; GFX10-NEXT: s_sub_i32 s9, s9, s10
-; GFX10-NEXT: s_sub_i32 s10, s14, s12
-; GFX10-NEXT: s_cmp_lt_i32 s6, s7
-; GFX10-NEXT: s_cselect_b32 s6, s6, s7
-; GFX10-NEXT: s_cmp_lt_i32 s8, -1
-; GFX10-NEXT: s_cselect_b32 s7, s8, -1
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s7
-; GFX10-NEXT: s_pack_ll_b32_b16 s7, s9, s10
-; GFX10-NEXT: s_lshr_b32 s8, s6, 16
-; GFX10-NEXT: s_sext_i32_i16 s9, s7
-; GFX10-NEXT: s_sext_i32_i16 s10, s5
-; GFX10-NEXT: s_sub_i32 s6, s6, s13
-; GFX10-NEXT: s_sub_i32 s8, s8, s11
-; GFX10-NEXT: s_ashr_i32 s7, s7, 16
-; GFX10-NEXT: s_ashr_i32 s5, s5, 16
-; GFX10-NEXT: s_cmp_gt_i32 s9, s10
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s6, s8
-; GFX10-NEXT: s_cselect_b32 s9, s9, s10
-; GFX10-NEXT: s_cmp_gt_i32 s7, s5
-; GFX10-NEXT: s_sext_i32_i16 s8, s6
-; GFX10-NEXT: s_cselect_b32 s5, s7, s5
-; GFX10-NEXT: s_ashr_i32 s6, s6, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s5, s9, s5
-; GFX10-NEXT: s_sext_i32_i16 s7, s5
-; GFX10-NEXT: s_ashr_i32 s5, s5, 16
-; GFX10-NEXT: s_cmp_lt_i32 s7, s8
-; GFX10-NEXT: s_cselect_b32 s7, s7, s8
-; GFX10-NEXT: s_cmp_lt_i32 s5, s6
-; GFX10-NEXT: s_cselect_b32 s5, s5, s6
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s7, s5
-; GFX10-NEXT: s_lshr_b32 s5, s2, 16
-; GFX10-NEXT: s_lshr_b32 s6, s3, 16
-; GFX10-NEXT: s_sub_i32 s2, s2, s3
-; GFX10-NEXT: s_sub_i32 s3, s5, s6
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s3
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: ; return to shader part epilog
%result = call <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x i32>
@@ -6343,71 +4238,21 @@ define <4 x float> @v_ssubsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX9-LABEL: v_ssubsat_v8i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_max_i16 v8, v0, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_mov_b32_e32 v9, 0x7fff7fff
-; GFX9-NEXT: v_pk_sub_i16 v8, v8, v9
-; GFX9-NEXT: v_pk_min_i16 v10, v0, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_mov_b32_e32 v11, 0x80008000
-; GFX9-NEXT: v_pk_max_i16 v4, v8, v4
-; GFX9-NEXT: v_pk_sub_i16 v10, v10, v11
-; GFX9-NEXT: v_pk_min_i16 v4, v4, v10
-; GFX9-NEXT: v_pk_sub_i16 v0, v0, v4
-; GFX9-NEXT: v_pk_max_i16 v4, v1, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_sub_i16 v4, v4, v9
-; GFX9-NEXT: v_pk_min_i16 v8, v1, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_max_i16 v4, v4, v5
-; GFX9-NEXT: v_pk_sub_i16 v8, v8, v11
-; GFX9-NEXT: v_pk_min_i16 v4, v4, v8
-; GFX9-NEXT: v_pk_sub_i16 v1, v1, v4
-; GFX9-NEXT: v_pk_max_i16 v4, v2, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_sub_i16 v4, v4, v9
-; GFX9-NEXT: v_pk_min_i16 v5, v2, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_sub_i16 v5, v5, v11
-; GFX9-NEXT: v_pk_max_i16 v4, v4, v6
-; GFX9-NEXT: v_pk_min_i16 v4, v4, v5
-; GFX9-NEXT: v_pk_sub_i16 v2, v2, v4
-; GFX9-NEXT: v_pk_max_i16 v4, v3, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_sub_i16 v4, v4, v9
-; GFX9-NEXT: v_pk_min_i16 v5, v3, -1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_sub_i16 v5, v5, v11
-; GFX9-NEXT: v_pk_max_i16 v4, v4, v7
-; GFX9-NEXT: v_pk_min_i16 v4, v4, v5
-; GFX9-NEXT: v_pk_sub_i16 v3, v3, v4
+; GFX9-NEXT: v_pk_sub_i16 v0, v0, v4 clamp
+; GFX9-NEXT: v_pk_sub_i16 v1, v1, v5 clamp
+; GFX9-NEXT: v_pk_sub_i16 v2, v2, v6 clamp
+; GFX9-NEXT: v_pk_sub_i16 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v8i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_max_i16 v8, v0, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_max_i16 v10, v1, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_max_i16 v12, v3, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_min_i16 v9, v0, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_min_i16 v11, v1, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_sub_i16 v15, v8, 0x7fff7fff
-; GFX10-NEXT: v_pk_max_i16 v8, v2, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_sub_i16 v10, v10, 0x7fff7fff
-; GFX10-NEXT: v_pk_sub_i16 v12, v12, 0x7fff7fff
-; GFX10-NEXT: v_pk_min_i16 v13, v2, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_min_i16 v14, v3, -1 op_sel_hi:[1,0]
-; GFX10-NEXT: v_pk_sub_i16 v8, v8, 0x7fff7fff
-; GFX10-NEXT: v_pk_max_i16 v4, v15, v4
-; GFX10-NEXT: v_pk_sub_i16 v9, v9, 0x80008000
-; GFX10-NEXT: v_pk_max_i16 v5, v10, v5
-; GFX10-NEXT: v_pk_sub_i16 v11, v11, 0x80008000
-; GFX10-NEXT: v_pk_max_i16 v15, v8, v6
-; GFX10-NEXT: v_pk_sub_i16 v10, v13, 0x80008000
-; GFX10-NEXT: v_pk_sub_i16 v8, v14, 0x80008000
-; GFX10-NEXT: v_pk_max_i16 v7, v12, v7
-; GFX10-NEXT: v_pk_min_i16 v19, v4, v9
-; GFX10-NEXT: v_pk_min_i16 v11, v5, v11
-; GFX10-NEXT: v_pk_min_i16 v15, v15, v10
+; GFX10-NEXT: v_pk_sub_i16 v0, v0, v4 clamp
+; GFX10-NEXT: v_pk_sub_i16 v1, v1, v5 clamp
+; GFX10-NEXT: v_pk_sub_i16 v2, v2, v6 clamp
+; GFX10-NEXT: v_pk_sub_i16 v3, v3, v7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_min_i16 v6, v7, v8
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, v19
-; GFX10-NEXT: v_pk_sub_i16 v1, v1, v11
-; GFX10-NEXT: v_pk_sub_i16 v2, v2, v15
-; GFX10-NEXT: v_pk_sub_i16 v3, v3, v6
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x float>
@@ -6711,365 +4556,31 @@ define amdgpu_ps <4 x i32> @s_ssubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inre
;
; GFX9-LABEL: s_ssubsat_v8i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_sext_i32_i16 s10, s0
-; GFX9-NEXT: s_ashr_i32 s11, s0, 16
-; GFX9-NEXT: s_sext_i32_i16 s12, -1
-; GFX9-NEXT: s_cmp_gt_i32 s10, s12
-; GFX9-NEXT: s_cselect_b32 s13, s10, s12
-; GFX9-NEXT: s_cmp_gt_i32 s11, -1
-; GFX9-NEXT: s_cselect_b32 s14, s11, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s14
-; GFX9-NEXT: s_mov_b32 s8, 0x7fff7fff
-; GFX9-NEXT: s_lshr_b32 s14, s13, 16
-; GFX9-NEXT: s_movk_i32 s15, 0x7fff
-; GFX9-NEXT: s_sub_i32 s13, s13, s8
-; GFX9-NEXT: s_sub_i32 s14, s14, s15
-; GFX9-NEXT: s_cmp_lt_i32 s10, s12
-; GFX9-NEXT: s_cselect_b32 s10, s10, s12
-; GFX9-NEXT: s_cmp_lt_i32 s11, -1
-; GFX9-NEXT: s_cselect_b32 s11, s11, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s11
-; GFX9-NEXT: s_pack_ll_b32_b16 s13, s13, s14
-; GFX9-NEXT: s_mov_b32 s9, 0x80008000
-; GFX9-NEXT: s_lshr_b32 s11, s10, 16
-; GFX9-NEXT: s_mov_b32 s14, 0x8000
-; GFX9-NEXT: s_sub_i32 s10, s10, s9
-; GFX9-NEXT: s_sub_i32 s11, s11, s14
-; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s11
-; GFX9-NEXT: s_sext_i32_i16 s11, s13
-; GFX9-NEXT: s_sext_i32_i16 s16, s4
-; GFX9-NEXT: s_ashr_i32 s13, s13, 16
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_cmp_gt_i32 s11, s16
-; GFX9-NEXT: s_cselect_b32 s11, s11, s16
-; GFX9-NEXT: s_cmp_gt_i32 s13, s4
-; GFX9-NEXT: s_cselect_b32 s4, s13, s4
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s11, s4
-; GFX9-NEXT: s_sext_i32_i16 s11, s4
-; GFX9-NEXT: s_sext_i32_i16 s13, s10
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_ashr_i32 s10, s10, 16
-; GFX9-NEXT: s_cmp_lt_i32 s11, s13
-; GFX9-NEXT: s_cselect_b32 s11, s11, s13
-; GFX9-NEXT: s_cmp_lt_i32 s4, s10
-; GFX9-NEXT: s_cselect_b32 s4, s4, s10
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s11, s4
-; GFX9-NEXT: s_lshr_b32 s10, s0, 16
-; GFX9-NEXT: s_lshr_b32 s11, s4, 16
-; GFX9-NEXT: s_sub_i32 s0, s0, s4
-; GFX9-NEXT: s_sub_i32 s4, s10, s11
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4
-; GFX9-NEXT: s_sext_i32_i16 s4, s1
-; GFX9-NEXT: s_ashr_i32 s10, s1, 16
-; GFX9-NEXT: s_cmp_gt_i32 s4, s12
-; GFX9-NEXT: s_cselect_b32 s11, s4, s12
-; GFX9-NEXT: s_cmp_gt_i32 s10, -1
-; GFX9-NEXT: s_cselect_b32 s13, s10, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s13
-; GFX9-NEXT: s_lshr_b32 s13, s11, 16
-; GFX9-NEXT: s_sub_i32 s11, s11, s8
-; GFX9-NEXT: s_sub_i32 s13, s13, s15
-; GFX9-NEXT: s_cmp_lt_i32 s4, s12
-; GFX9-NEXT: s_cselect_b32 s4, s4, s12
-; GFX9-NEXT: s_cmp_lt_i32 s10, -1
-; GFX9-NEXT: s_cselect_b32 s10, s10, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s10
-; GFX9-NEXT: s_lshr_b32 s10, s4, 16
-; GFX9-NEXT: s_pack_ll_b32_b16 s11, s11, s13
-; GFX9-NEXT: s_sub_i32 s4, s4, s9
-; GFX9-NEXT: s_sub_i32 s10, s10, s14
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s10
-; GFX9-NEXT: s_sext_i32_i16 s10, s11
-; GFX9-NEXT: s_sext_i32_i16 s13, s5
-; GFX9-NEXT: s_ashr_i32 s11, s11, 16
-; GFX9-NEXT: s_ashr_i32 s5, s5, 16
-; GFX9-NEXT: s_cmp_gt_i32 s10, s13
-; GFX9-NEXT: s_cselect_b32 s10, s10, s13
-; GFX9-NEXT: s_cmp_gt_i32 s11, s5
-; GFX9-NEXT: s_cselect_b32 s5, s11, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s10, s5
-; GFX9-NEXT: s_sext_i32_i16 s10, s5
-; GFX9-NEXT: s_sext_i32_i16 s11, s4
-; GFX9-NEXT: s_ashr_i32 s5, s5, 16
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_cmp_lt_i32 s10, s11
-; GFX9-NEXT: s_cselect_b32 s10, s10, s11
-; GFX9-NEXT: s_cmp_lt_i32 s5, s4
-; GFX9-NEXT: s_cselect_b32 s4, s5, s4
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s10, s4
-; GFX9-NEXT: s_lshr_b32 s5, s1, 16
-; GFX9-NEXT: s_lshr_b32 s10, s4, 16
-; GFX9-NEXT: s_sub_i32 s1, s1, s4
-; GFX9-NEXT: s_sub_i32 s4, s5, s10
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4
-; GFX9-NEXT: s_sext_i32_i16 s4, s2
-; GFX9-NEXT: s_ashr_i32 s5, s2, 16
-; GFX9-NEXT: s_cmp_gt_i32 s4, s12
-; GFX9-NEXT: s_cselect_b32 s10, s4, s12
-; GFX9-NEXT: s_cmp_gt_i32 s5, -1
-; GFX9-NEXT: s_cselect_b32 s11, s5, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s11
-; GFX9-NEXT: s_lshr_b32 s11, s10, 16
-; GFX9-NEXT: s_sub_i32 s10, s10, s8
-; GFX9-NEXT: s_sub_i32 s11, s11, s15
-; GFX9-NEXT: s_cmp_lt_i32 s4, s12
-; GFX9-NEXT: s_cselect_b32 s4, s4, s12
-; GFX9-NEXT: s_cmp_lt_i32 s5, -1
-; GFX9-NEXT: s_cselect_b32 s5, s5, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_lshr_b32 s5, s4, 16
-; GFX9-NEXT: s_pack_ll_b32_b16 s10, s10, s11
-; GFX9-NEXT: s_sub_i32 s4, s4, s9
-; GFX9-NEXT: s_sub_i32 s5, s5, s14
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_sext_i32_i16 s5, s10
-; GFX9-NEXT: s_sext_i32_i16 s11, s6
-; GFX9-NEXT: s_ashr_i32 s10, s10, 16
-; GFX9-NEXT: s_ashr_i32 s6, s6, 16
-; GFX9-NEXT: s_cmp_gt_i32 s5, s11
-; GFX9-NEXT: s_cselect_b32 s5, s5, s11
-; GFX9-NEXT: s_cmp_gt_i32 s10, s6
-; GFX9-NEXT: s_cselect_b32 s6, s10, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s6
-; GFX9-NEXT: s_sext_i32_i16 s6, s5
-; GFX9-NEXT: s_sext_i32_i16 s10, s4
-; GFX9-NEXT: s_ashr_i32 s5, s5, 16
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_cmp_lt_i32 s6, s10
-; GFX9-NEXT: s_cselect_b32 s6, s6, s10
-; GFX9-NEXT: s_cmp_lt_i32 s5, s4
-; GFX9-NEXT: s_cselect_b32 s4, s5, s4
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s4
-; GFX9-NEXT: s_lshr_b32 s5, s2, 16
-; GFX9-NEXT: s_lshr_b32 s6, s4, 16
-; GFX9-NEXT: s_sub_i32 s2, s2, s4
-; GFX9-NEXT: s_sub_i32 s4, s5, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4
-; GFX9-NEXT: s_sext_i32_i16 s4, s3
-; GFX9-NEXT: s_ashr_i32 s5, s3, 16
-; GFX9-NEXT: s_cmp_gt_i32 s4, s12
-; GFX9-NEXT: s_cselect_b32 s6, s4, s12
-; GFX9-NEXT: s_cmp_gt_i32 s5, -1
-; GFX9-NEXT: s_cselect_b32 s10, s5, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s10
-; GFX9-NEXT: s_lshr_b32 s10, s6, 16
-; GFX9-NEXT: s_sub_i32 s6, s6, s8
-; GFX9-NEXT: s_sub_i32 s8, s10, s15
-; GFX9-NEXT: s_cmp_lt_i32 s4, s12
-; GFX9-NEXT: s_cselect_b32 s4, s4, s12
-; GFX9-NEXT: s_cmp_lt_i32 s5, -1
-; GFX9-NEXT: s_cselect_b32 s5, s5, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_lshr_b32 s5, s4, 16
-; GFX9-NEXT: s_pack_ll_b32_b16 s6, s6, s8
-; GFX9-NEXT: s_sub_i32 s4, s4, s9
-; GFX9-NEXT: s_sub_i32 s5, s5, s14
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_sext_i32_i16 s5, s6
-; GFX9-NEXT: s_sext_i32_i16 s8, s7
-; GFX9-NEXT: s_ashr_i32 s6, s6, 16
-; GFX9-NEXT: s_ashr_i32 s7, s7, 16
-; GFX9-NEXT: s_cmp_gt_i32 s5, s8
-; GFX9-NEXT: s_cselect_b32 s5, s5, s8
-; GFX9-NEXT: s_cmp_gt_i32 s6, s7
-; GFX9-NEXT: s_cselect_b32 s6, s6, s7
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s6
-; GFX9-NEXT: s_sext_i32_i16 s6, s5
-; GFX9-NEXT: s_sext_i32_i16 s7, s4
-; GFX9-NEXT: s_ashr_i32 s5, s5, 16
-; GFX9-NEXT: s_ashr_i32 s4, s4, 16
-; GFX9-NEXT: s_cmp_lt_i32 s6, s7
-; GFX9-NEXT: s_cselect_b32 s6, s6, s7
-; GFX9-NEXT: s_cmp_lt_i32 s5, s4
-; GFX9-NEXT: s_cselect_b32 s4, s5, s4
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s6, s4
-; GFX9-NEXT: s_lshr_b32 s5, s3, 16
-; GFX9-NEXT: s_lshr_b32 s6, s4, 16
-; GFX9-NEXT: s_sub_i32 s3, s3, s4
-; GFX9-NEXT: s_sub_i32 s4, s5, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
+; GFX9-NEXT: v_pk_sub_i16 v1, s1, v1 clamp
+; GFX9-NEXT: v_pk_sub_i16 v2, s2, v2 clamp
+; GFX9-NEXT: v_pk_sub_i16 v3, s3, v3 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v8i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_sext_i32_i16 s8, s0
-; GFX10-NEXT: s_sext_i32_i16 s9, -1
-; GFX10-NEXT: s_ashr_i32 s10, s0, 16
-; GFX10-NEXT: s_cmp_gt_i32 s8, s9
-; GFX10-NEXT: s_movk_i32 s14, 0x7fff
-; GFX10-NEXT: s_cselect_b32 s11, s8, s9
-; GFX10-NEXT: s_cmp_gt_i32 s10, -1
-; GFX10-NEXT: s_mov_b32 s15, 0x80008000
-; GFX10-NEXT: s_cselect_b32 s12, s10, -1
-; GFX10-NEXT: s_sext_i32_i16 s17, s4
-; GFX10-NEXT: s_pack_ll_b32_b16 s11, s11, s12
-; GFX10-NEXT: s_mov_b32 s12, 0x7fff7fff
-; GFX10-NEXT: s_lshr_b32 s13, s11, 16
-; GFX10-NEXT: s_sub_i32 s11, s11, s12
-; GFX10-NEXT: s_sub_i32 s13, s13, s14
-; GFX10-NEXT: s_cmp_lt_i32 s8, s9
+; GFX10-NEXT: v_pk_sub_i16 v0, s0, s4 clamp
+; GFX10-NEXT: v_pk_sub_i16 v1, s1, s5 clamp
+; GFX10-NEXT: v_pk_sub_i16 v2, s2, s6 clamp
+; GFX10-NEXT: v_pk_sub_i16 v3, s3, s7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s8, s8, s9
-; GFX10-NEXT: s_cmp_lt_i32 s10, -1
-; GFX10-NEXT: s_cselect_b32 s10, s10, -1
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s8, s8, s10
-; GFX10-NEXT: s_pack_ll_b32_b16 s10, s11, s13
-; GFX10-NEXT: s_lshr_b32 s11, s8, 16
-; GFX10-NEXT: s_mov_b32 s13, 0x8000
-; GFX10-NEXT: s_sext_i32_i16 s16, s10
-; GFX10-NEXT: s_sub_i32 s8, s8, s15
-; GFX10-NEXT: s_sub_i32 s11, s11, s13
-; GFX10-NEXT: s_ashr_i32 s10, s10, 16
-; GFX10-NEXT: s_cmp_gt_i32 s16, s17
-; GFX10-NEXT: s_pack_ll_b32_b16 s8, s8, s11
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_cmp_gt_i32 s10, s4
-; GFX10-NEXT: s_sext_i32_i16 s11, s8
-; GFX10-NEXT: s_cselect_b32 s4, s10, s4
-; GFX10-NEXT: s_ashr_i32 s8, s8, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s16, s4
-; GFX10-NEXT: s_sext_i32_i16 s17, s5
-; GFX10-NEXT: s_sext_i32_i16 s10, s4
-; GFX10-NEXT: s_ashr_i32 s4, s4, 16
-; GFX10-NEXT: s_cmp_lt_i32 s10, s11
-; GFX10-NEXT: s_cselect_b32 s10, s10, s11
-; GFX10-NEXT: s_cmp_lt_i32 s4, s8
-; GFX10-NEXT: s_cselect_b32 s4, s4, s8
-; GFX10-NEXT: s_lshr_b32 s8, s0, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s10, s4
-; GFX10-NEXT: s_lshr_b32 s10, s4, 16
-; GFX10-NEXT: s_sub_i32 s0, s0, s4
-; GFX10-NEXT: s_sub_i32 s4, s8, s10
-; GFX10-NEXT: s_sext_i32_i16 s8, s1
-; GFX10-NEXT: s_ashr_i32 s10, s1, 16
-; GFX10-NEXT: s_cmp_gt_i32 s8, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4
-; GFX10-NEXT: s_cselect_b32 s11, s8, s9
-; GFX10-NEXT: s_cmp_gt_i32 s10, -1
-; GFX10-NEXT: s_cselect_b32 s16, s10, -1
-; GFX10-NEXT: s_pack_ll_b32_b16 s11, s11, s16
-; GFX10-NEXT: s_lshr_b32 s16, s11, 16
-; GFX10-NEXT: s_sub_i32 s11, s11, s12
-; GFX10-NEXT: s_sub_i32 s16, s16, s14
-; GFX10-NEXT: s_cmp_lt_i32 s8, s9
-; GFX10-NEXT: s_cselect_b32 s8, s8, s9
-; GFX10-NEXT: s_cmp_lt_i32 s10, -1
-; GFX10-NEXT: s_cselect_b32 s10, s10, -1
-; GFX10-NEXT: s_ashr_i32 s5, s5, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s8, s8, s10
-; GFX10-NEXT: s_pack_ll_b32_b16 s10, s11, s16
-; GFX10-NEXT: s_lshr_b32 s11, s8, 16
-; GFX10-NEXT: s_sext_i32_i16 s16, s10
-; GFX10-NEXT: s_sub_i32 s8, s8, s15
-; GFX10-NEXT: s_sub_i32 s11, s11, s13
-; GFX10-NEXT: s_ashr_i32 s10, s10, 16
-; GFX10-NEXT: s_cmp_gt_i32 s16, s17
-; GFX10-NEXT: s_pack_ll_b32_b16 s8, s8, s11
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_cmp_gt_i32 s10, s5
-; GFX10-NEXT: s_sext_i32_i16 s11, s8
-; GFX10-NEXT: s_cselect_b32 s5, s10, s5
-; GFX10-NEXT: s_ashr_i32 s8, s8, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s5, s16, s5
-; GFX10-NEXT: s_sext_i32_i16 s17, s6
-; GFX10-NEXT: s_sext_i32_i16 s10, s5
-; GFX10-NEXT: s_ashr_i32 s5, s5, 16
-; GFX10-NEXT: s_cmp_lt_i32 s10, s11
-; GFX10-NEXT: s_cselect_b32 s10, s10, s11
-; GFX10-NEXT: s_cmp_lt_i32 s5, s8
-; GFX10-NEXT: s_cselect_b32 s5, s5, s8
-; GFX10-NEXT: s_lshr_b32 s8, s1, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s5, s10, s5
-; GFX10-NEXT: s_lshr_b32 s10, s5, 16
-; GFX10-NEXT: s_sub_i32 s1, s1, s5
-; GFX10-NEXT: s_sub_i32 s5, s8, s10
-; GFX10-NEXT: s_sext_i32_i16 s8, s2
-; GFX10-NEXT: s_ashr_i32 s10, s2, 16
-; GFX10-NEXT: s_cmp_gt_i32 s8, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5
-; GFX10-NEXT: s_cselect_b32 s11, s8, s9
-; GFX10-NEXT: s_cmp_gt_i32 s10, -1
-; GFX10-NEXT: s_cselect_b32 s16, s10, -1
-; GFX10-NEXT: s_pack_ll_b32_b16 s11, s11, s16
-; GFX10-NEXT: s_lshr_b32 s16, s11, 16
-; GFX10-NEXT: s_sub_i32 s11, s11, s12
-; GFX10-NEXT: s_sub_i32 s16, s16, s14
-; GFX10-NEXT: s_cmp_lt_i32 s8, s9
-; GFX10-NEXT: s_cselect_b32 s8, s8, s9
-; GFX10-NEXT: s_cmp_lt_i32 s10, -1
-; GFX10-NEXT: s_cselect_b32 s10, s10, -1
-; GFX10-NEXT: s_ashr_i32 s6, s6, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s8, s8, s10
-; GFX10-NEXT: s_pack_ll_b32_b16 s10, s11, s16
-; GFX10-NEXT: s_lshr_b32 s11, s8, 16
-; GFX10-NEXT: s_sext_i32_i16 s16, s10
-; GFX10-NEXT: s_sub_i32 s8, s8, s15
-; GFX10-NEXT: s_sub_i32 s11, s11, s13
-; GFX10-NEXT: s_ashr_i32 s10, s10, 16
-; GFX10-NEXT: s_cmp_gt_i32 s16, s17
-; GFX10-NEXT: s_pack_ll_b32_b16 s8, s8, s11
-; GFX10-NEXT: s_cselect_b32 s16, s16, s17
-; GFX10-NEXT: s_cmp_gt_i32 s10, s6
-; GFX10-NEXT: s_sext_i32_i16 s11, s8
-; GFX10-NEXT: s_cselect_b32 s6, s10, s6
-; GFX10-NEXT: s_ashr_i32 s8, s8, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s16, s6
-; GFX10-NEXT: s_sext_i32_i16 s10, s6
-; GFX10-NEXT: s_ashr_i32 s6, s6, 16
-; GFX10-NEXT: s_cmp_lt_i32 s10, s11
-; GFX10-NEXT: s_cselect_b32 s10, s10, s11
-; GFX10-NEXT: s_cmp_lt_i32 s6, s8
-; GFX10-NEXT: s_cselect_b32 s6, s6, s8
-; GFX10-NEXT: s_lshr_b32 s8, s2, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s10, s6
-; GFX10-NEXT: s_lshr_b32 s10, s6, 16
-; GFX10-NEXT: s_sub_i32 s2, s2, s6
-; GFX10-NEXT: s_sub_i32 s6, s8, s10
-; GFX10-NEXT: s_sext_i32_i16 s8, s3
-; GFX10-NEXT: s_ashr_i32 s10, s3, 16
-; GFX10-NEXT: s_cmp_gt_i32 s8, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s6
-; GFX10-NEXT: s_cselect_b32 s11, s8, s9
-; GFX10-NEXT: s_cmp_gt_i32 s10, -1
-; GFX10-NEXT: s_cselect_b32 s16, s10, -1
-; GFX10-NEXT: s_pack_ll_b32_b16 s11, s11, s16
-; GFX10-NEXT: s_lshr_b32 s16, s11, 16
-; GFX10-NEXT: s_sub_i32 s11, s11, s12
-; GFX10-NEXT: s_sub_i32 s12, s16, s14
-; GFX10-NEXT: s_cmp_lt_i32 s8, s9
-; GFX10-NEXT: s_cselect_b32 s8, s8, s9
-; GFX10-NEXT: s_cmp_lt_i32 s10, -1
-; GFX10-NEXT: s_cselect_b32 s9, s10, -1
-; GFX10-NEXT: s_pack_ll_b32_b16 s8, s8, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s9, s11, s12
-; GFX10-NEXT: s_lshr_b32 s10, s8, 16
-; GFX10-NEXT: s_sext_i32_i16 s11, s9
-; GFX10-NEXT: s_sext_i32_i16 s12, s7
-; GFX10-NEXT: s_sub_i32 s8, s8, s15
-; GFX10-NEXT: s_sub_i32 s10, s10, s13
-; GFX10-NEXT: s_ashr_i32 s9, s9, 16
-; GFX10-NEXT: s_ashr_i32 s7, s7, 16
-; GFX10-NEXT: s_cmp_gt_i32 s11, s12
-; GFX10-NEXT: s_pack_ll_b32_b16 s8, s8, s10
-; GFX10-NEXT: s_cselect_b32 s11, s11, s12
-; GFX10-NEXT: s_cmp_gt_i32 s9, s7
-; GFX10-NEXT: s_sext_i32_i16 s10, s8
-; GFX10-NEXT: s_cselect_b32 s7, s9, s7
-; GFX10-NEXT: s_ashr_i32 s8, s8, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s7, s11, s7
-; GFX10-NEXT: s_sext_i32_i16 s9, s7
-; GFX10-NEXT: s_ashr_i32 s7, s7, 16
-; GFX10-NEXT: s_cmp_lt_i32 s9, s10
-; GFX10-NEXT: s_cselect_b32 s9, s9, s10
-; GFX10-NEXT: s_cmp_lt_i32 s7, s8
-; GFX10-NEXT: s_cselect_b32 s4, s7, s8
-; GFX10-NEXT: s_lshr_b32 s5, s3, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s9, s4
-; GFX10-NEXT: s_lshr_b32 s7, s4, 16
-; GFX10-NEXT: s_sub_i32 s3, s3, s4
-; GFX10-NEXT: s_sub_i32 s4, s5, s7
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s4
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: ; return to shader part epilog
%result = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x i32>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
index 3a742fbcbd91..cbabb07aa936 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
@@ -21,9 +21,7 @@ define i7 @v_uaddsat_i7(i7 %lhs, i7 %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 9, v1
-; GFX8-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX8-NEXT: v_min_u16_e32 v1, v2, v1
-; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp
; GFX8-NEXT: v_lshrrev_b16_e32 v0, 9, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -32,9 +30,7 @@ define i7 @v_uaddsat_i7(i7 %lhs, i7 %rhs) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 9, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 9, v1
-; GFX9-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX9-NEXT: v_min_u16_e32 v1, v2, v1
-; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp
; GFX9-NEXT: v_lshrrev_b16_e32 v0, 9, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -45,9 +41,7 @@ define i7 @v_uaddsat_i7(i7 %lhs, i7 %rhs) {
; GFX10-NEXT: v_lshlrev_b16_e64 v0, 9, v0
; GFX10-NEXT: v_lshlrev_b16_e64 v1, 9, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX10-NEXT: v_min_u16_e64 v1, v2, v1
-; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1
+; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 clamp
; GFX10-NEXT: v_lshrrev_b16_e64 v0, 9, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs)
@@ -69,31 +63,23 @@ define amdgpu_ps i7 @s_uaddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX8-LABEL: s_uaddsat_i7:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000
-; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s2
-; GFX8-NEXT: s_xor_b32 s3, s0, -1
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s3, s1
-; GFX8-NEXT: s_cselect_b32 s1, s3, s1
-; GFX8-NEXT: s_add_i32 s0, s0, s1
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_lshr_b32 s0, s0, s2
+; GFX8-NEXT: s_lshl_b32 s0, s0, s2
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_lshrrev_b16_e32 v0, 9, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_i7:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s2, 9, 0x100000
-; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
-; GFX9-NEXT: s_xor_b32 s3, s0, -1
-; GFX9-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s3, s1
-; GFX9-NEXT: s_cselect_b32 s1, s3, s1
-; GFX9-NEXT: s_add_i32 s0, s0, s1
-; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX9-NEXT: s_lshr_b32 s0, s0, s2
+; GFX9-NEXT: s_lshl_b32 s0, s0, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_add_u16_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_lshrrev_b16_e32 v0, 9, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_i7:
@@ -102,14 +88,9 @@ define amdgpu_ps i7 @s_uaddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_lshl_b32 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: s_xor_b32 s3, s0, -1
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX10-NEXT: s_cmp_lt_u32 s3, s1
-; GFX10-NEXT: s_cselect_b32 s1, s3, s1
-; GFX10-NEXT: s_add_i32 s0, s0, s1
-; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX10-NEXT: s_lshr_b32 s0, s0, s2
+; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, s1 clamp
+; GFX10-NEXT: v_lshrrev_b16_e64 v0, 9, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result
@@ -132,9 +113,7 @@ define i8 @v_uaddsat_i8(i8 %lhs, i8 %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX8-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX8-NEXT: v_min_u16_e32 v1, v2, v1
-; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp
; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -143,9 +122,7 @@ define i8 @v_uaddsat_i8(i8 %lhs, i8 %rhs) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX9-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX9-NEXT: v_min_u16_e32 v1, v2, v1
-; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp
; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -156,9 +133,7 @@ define i8 @v_uaddsat_i8(i8 %lhs, i8 %rhs) {
; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0
; GFX10-NEXT: v_lshlrev_b16_e64 v1, 8, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX10-NEXT: v_min_u16_e64 v1, v2, v1
-; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1
+; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 clamp
; GFX10-NEXT: v_lshrrev_b16_e64 v0, 8, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)
@@ -180,31 +155,23 @@ define amdgpu_ps i8 @s_uaddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX8-LABEL: s_uaddsat_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000
-; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s2
-; GFX8-NEXT: s_xor_b32 s3, s0, -1
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s3, s1
-; GFX8-NEXT: s_cselect_b32 s1, s3, s1
-; GFX8-NEXT: s_add_i32 s0, s0, s1
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_lshr_b32 s0, s0, s2
+; GFX8-NEXT: s_lshl_b32 s0, s0, s2
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s2, 8, 0x100000
-; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
-; GFX9-NEXT: s_xor_b32 s3, s0, -1
-; GFX9-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s3, s1
-; GFX9-NEXT: s_cselect_b32 s1, s3, s1
-; GFX9-NEXT: s_add_i32 s0, s0, s1
-; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX9-NEXT: s_lshr_b32 s0, s0, s2
+; GFX9-NEXT: s_lshl_b32 s0, s0, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_add_u16_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_i8:
@@ -213,14 +180,9 @@ define amdgpu_ps i8 @s_uaddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_lshl_b32 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: s_xor_b32 s3, s0, -1
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX10-NEXT: s_cmp_lt_u32 s3, s1
-; GFX10-NEXT: s_cselect_b32 s1, s3, s1
-; GFX10-NEXT: s_add_i32 s0, s0, s1
-; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX10-NEXT: s_lshr_b32 s0, s0, s2
+; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, s1 clamp
+; GFX10-NEXT: v_lshrrev_b16_e64 v0, 8, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result
@@ -256,16 +218,12 @@ define i16 @v_uaddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 8
; GFX8-NEXT: v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX8-NEXT: v_xor_b32_e32 v4, -1, v0
-; GFX8-NEXT: v_min_u16_e32 v1, v4, v1
-; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX8-NEXT: v_xor_b32_e32 v1, -1, v3
-; GFX8-NEXT: v_min_u16_e32 v1, v1, v2
+; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp
+; GFX8-NEXT: v_add_u16_e64 v1, v3, v2 clamp
; GFX8-NEXT: v_mov_b32_e32 v2, 0xff
-; GFX8-NEXT: v_add_u16_e32 v1, v3, v1
; GFX8-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
@@ -276,16 +234,12 @@ define i16 @v_uaddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX9-NEXT: v_xor_b32_e32 v4, -1, v0
-; GFX9-NEXT: v_min_u16_e32 v1, v4, v1
-; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX9-NEXT: v_xor_b32_e32 v1, -1, v2
-; GFX9-NEXT: v_min_u16_e32 v1, v1, v3
+; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp
; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: v_add_u16_e32 v1, v2, v1
+; GFX9-NEXT: v_add_u16_e64 v1, v2, v3 clamp
; GFX9-NEXT: v_and_b32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
@@ -296,21 +250,17 @@ define i16 @v_uaddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8
-; GFX10-NEXT: v_lshlrev_b16_e64 v2, 8, v0
-; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_lshlrev_b16_e64 v1, 8, v1
+; GFX10-NEXT: v_lshlrev_b16_e64 v3, 8, v1
+; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0
; GFX10-NEXT: s_movk_i32 s4, 0xff
-; GFX10-NEXT: v_xor_b32_e32 v4, -1, v2
-; GFX10-NEXT: v_xor_b32_e32 v5, -1, v0
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u16_e64 v1, v4, v1
-; GFX10-NEXT: v_min_u16_e64 v3, v5, v3
-; GFX10-NEXT: v_add_nc_u16_e64 v1, v2, v1
-; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v3
-; GFX10-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_and_b32_sdwa v0, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX10-NEXT: v_add_nc_u16_e64 v1, v2, v1 clamp
+; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v3 clamp
+; GFX10-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
@@ -348,98 +298,60 @@ define amdgpu_ps i16 @s_uaddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX8-LABEL: s_uaddsat_v2i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000
-; GFX8-NEXT: s_lshr_b32 s2, s0, 8
-; GFX8-NEXT: s_lshl_b32 s0, s0, s4
-; GFX8-NEXT: s_xor_b32 s5, s0, -1
; GFX8-NEXT: s_lshr_b32 s3, s1, 8
; GFX8-NEXT: s_lshl_b32 s1, s1, s4
-; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s5, s1
-; GFX8-NEXT: s_cselect_b32 s1, s5, s1
-; GFX8-NEXT: s_add_i32 s0, s0, s1
-; GFX8-NEXT: s_lshl_b32 s1, s2, s4
-; GFX8-NEXT: s_lshl_b32 s2, s3, s4
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_xor_b32 s3, s1, -1
-; GFX8-NEXT: s_lshr_b32 s0, s0, s4
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s3, s2
-; GFX8-NEXT: s_cselect_b32 s2, s3, s2
-; GFX8-NEXT: s_add_i32 s1, s1, s2
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_movk_i32 s2, 0xff
-; GFX8-NEXT: s_lshr_b32 s1, s1, s4
-; GFX8-NEXT: s_and_b32 s1, s1, s2
-; GFX8-NEXT: s_and_b32 s0, s0, s2
-; GFX8-NEXT: s_lshl_b32 s1, s1, s4
-; GFX8-NEXT: s_or_b32 s0, s0, s1
+; GFX8-NEXT: s_lshr_b32 s2, s0, 8
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: s_lshl_b32 s0, s0, s4
+; GFX8-NEXT: s_lshl_b32 s1, s3, s4
+; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: s_lshl_b32 s0, s2, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0xff
+; GFX8-NEXT: v_add_u16_e64 v1, s0, v1 clamp
+; GFX8-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_v2i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s4, 8, 0x100000
-; GFX9-NEXT: s_lshr_b32 s2, s0, 8
-; GFX9-NEXT: s_lshl_b32 s0, s0, s4
-; GFX9-NEXT: s_xor_b32 s5, s0, -1
; GFX9-NEXT: s_lshr_b32 s3, s1, 8
; GFX9-NEXT: s_lshl_b32 s1, s1, s4
-; GFX9-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s5, s1
-; GFX9-NEXT: s_cselect_b32 s1, s5, s1
-; GFX9-NEXT: s_add_i32 s0, s0, s1
-; GFX9-NEXT: s_lshl_b32 s1, s2, s4
-; GFX9-NEXT: s_lshl_b32 s2, s3, s4
-; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX9-NEXT: s_xor_b32 s3, s1, -1
-; GFX9-NEXT: s_lshr_b32 s0, s0, s4
-; GFX9-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX9-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s3, s2
-; GFX9-NEXT: s_cselect_b32 s2, s3, s2
-; GFX9-NEXT: s_add_i32 s1, s1, s2
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: s_movk_i32 s2, 0xff
-; GFX9-NEXT: s_lshr_b32 s1, s1, s4
-; GFX9-NEXT: s_and_b32 s1, s1, s2
-; GFX9-NEXT: s_and_b32 s0, s0, s2
-; GFX9-NEXT: s_lshl_b32 s1, s1, s4
-; GFX9-NEXT: s_or_b32 s0, s0, s1
+; GFX9-NEXT: s_lshr_b32 s2, s0, 8
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: s_lshl_b32 s0, s0, s4
+; GFX9-NEXT: s_lshl_b32 s1, s3, s4
+; GFX9-NEXT: v_add_u16_e64 v0, s0, v0 clamp
+; GFX9-NEXT: s_lshl_b32 s0, s2, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_add_u16_e64 v1, s0, v1 clamp
+; GFX9-NEXT: s_movk_i32 s0, 0xff
+; GFX9-NEXT: v_and_b32_sdwa v0, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_v2i8:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000
+; GFX10-NEXT: s_lshr_b32 s2, s0, 8
+; GFX10-NEXT: s_bfe_u32 s3, 8, 0x100000
+; GFX10-NEXT: s_lshr_b32 s4, s1, 8
+; GFX10-NEXT: s_lshl_b32 s0, s0, s3
+; GFX10-NEXT: s_lshl_b32 s1, s1, s3
+; GFX10-NEXT: s_lshl_b32 s2, s2, s3
+; GFX10-NEXT: s_lshl_b32 s3, s4, s3
+; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, s1 clamp
+; GFX10-NEXT: v_add_nc_u16_e64 v1, s2, s3 clamp
+; GFX10-NEXT: s_movk_i32 s0, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_lshl_b32 s3, s0, s2
-; GFX10-NEXT: s_lshl_b32 s5, s1, s2
-; GFX10-NEXT: s_xor_b32 s4, s3, -1
-; GFX10-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX10-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX10-NEXT: s_lshr_b32 s0, s0, 8
-; GFX10-NEXT: s_lshr_b32 s1, s1, 8
-; GFX10-NEXT: s_cmp_lt_u32 s4, s5
-; GFX10-NEXT: s_cselect_b32 s4, s4, s5
-; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_add_i32 s3, s3, s4
-; GFX10-NEXT: s_xor_b32 s4, s0, -1
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX10-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: s_lshr_b32 s3, s3, s2
-; GFX10-NEXT: s_cmp_lt_u32 s4, s1
-; GFX10-NEXT: s_cselect_b32 s1, s4, s1
-; GFX10-NEXT: s_add_i32 s0, s0, s1
-; GFX10-NEXT: s_movk_i32 s1, 0xff
-; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX10-NEXT: s_lshr_b32 s0, s0, s2
-; GFX10-NEXT: s_and_b32 s0, s0, s1
-; GFX10-NEXT: s_and_b32 s1, s3, s1
-; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_or_b32 s0, s1, s0
+; GFX10-NEXT: v_and_b32_sdwa v0, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
@@ -502,27 +414,19 @@ define i32 @v_uaddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX8-NEXT: v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 24, v0
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX8-NEXT: v_xor_b32_e32 v8, -1, v0
-; GFX8-NEXT: v_min_u16_e32 v1, v8, v1
-; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX8-NEXT: v_xor_b32_e32 v1, -1, v3
-; GFX8-NEXT: v_min_u16_e32 v1, v1, v2
+; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp
+; GFX8-NEXT: v_add_u16_e64 v1, v3, v2 clamp
; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v4
-; GFX8-NEXT: v_add_u16_e32 v1, v3, v1
; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v6
-; GFX8-NEXT: v_xor_b32_e32 v4, -1, v2
-; GFX8-NEXT: v_min_u16_e32 v3, v4, v3
-; GFX8-NEXT: v_add_u16_e32 v2, v2, v3
+; GFX8-NEXT: v_add_u16_e64 v2, v2, v3 clamp
; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v5
; GFX8-NEXT: v_lshlrev_b16_e32 v4, 8, v7
-; GFX8-NEXT: v_xor_b32_e32 v5, -1, v3
-; GFX8-NEXT: v_min_u16_e32 v4, v5, v4
-; GFX8-NEXT: v_add_u16_e32 v3, v3, v4
+; GFX8-NEXT: v_add_u16_e64 v3, v3, v4 clamp
; GFX8-NEXT: v_mov_b32_e32 v4, 0xff
; GFX8-NEXT: v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
@@ -539,33 +443,25 @@ define i32 @v_uaddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 24, v0
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1
+; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX9-NEXT: v_xor_b32_e32 v8, -1, v0
-; GFX9-NEXT: v_min_u16_e32 v1, v8, v1
-; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
-; GFX9-NEXT: v_xor_b32_e32 v1, -1, v2
-; GFX9-NEXT: v_min_u16_e32 v1, v1, v5
-; GFX9-NEXT: v_add_u16_e32 v1, v2, v1
+; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp
+; GFX9-NEXT: v_add_u16_e64 v1, v2, v5 clamp
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v6
-; GFX9-NEXT: v_xor_b32_e32 v5, -1, v2
-; GFX9-NEXT: v_min_u16_e32 v3, v5, v3
-; GFX9-NEXT: v_add_u16_e32 v2, v2, v3
-; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v4
; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v7
-; GFX9-NEXT: v_xor_b32_e32 v5, -1, v3
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX9-NEXT: v_min_u16_e32 v4, v5, v4
+; GFX9-NEXT: v_add_u16_e64 v2, v2, v3 clamp
+; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v4
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v7
; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX9-NEXT: v_add_u16_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u16_e64 v3, v3, v4 clamp
; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v1
; GFX9-NEXT: v_and_b32_sdwa v1, v2, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v2, v3, s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
@@ -577,36 +473,28 @@ define i32 @v_uaddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8
-; GFX10-NEXT: v_lshlrev_b16_e64 v4, 8, v0
+; GFX10-NEXT: v_lshlrev_b16_e64 v5, 8, v0
; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshlrev_b16_e64 v6, 8, v1
; GFX10-NEXT: s_mov_b32 s5, 16
-; GFX10-NEXT: s_mov_b32 s6, 24
-; GFX10-NEXT: v_lshrrev_b32_sdwa v6, s5, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_xor_b32_e32 v5, -1, v2
-; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s6, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_lshlrev_b16_e64 v7, 8, v1
-; GFX10-NEXT: v_xor_b32_e32 v8, -1, v4
-; GFX10-NEXT: v_xor_b32_e32 v11, -1, v6
-; GFX10-NEXT: v_min_u16_e64 v3, v5, v3
-; GFX10-NEXT: v_lshrrev_b32_sdwa v5, s5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s6, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_min_u16_e64 v7, v8, v7
-; GFX10-NEXT: s_movk_i32 s4, 0xff
-; GFX10-NEXT: v_add_nc_u16_e64 v2, v2, v3
-; GFX10-NEXT: v_xor_b32_e32 v3, -1, v0
-; GFX10-NEXT: v_min_u16_e64 v5, v11, v5
-; GFX10-NEXT: v_add_nc_u16_e64 v4, v4, v7
+; GFX10-NEXT: s_mov_b32 s4, 24
+; GFX10-NEXT: v_lshrrev_b32_sdwa v4, s5, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_add_nc_u16_e64 v2, v2, v3 clamp
+; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: s_movk_i32 s5, 0xff
+; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v2, v2, s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_add_nc_u16_e64 v5, v5, v6 clamp
+; GFX10-NEXT: v_add_nc_u16_e64 v3, v4, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_and_b32_sdwa v2, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_min_u16_e64 v1, v3, v1
-; GFX10-NEXT: v_add_nc_u16_e64 v3, v6, v5
-; GFX10-NEXT: v_lshrrev_b16_e64 v4, 8, v4
+; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 clamp
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1
-; GFX10-NEXT: v_and_b32_sdwa v1, v3, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_and_or_b32 v2, v4, s4, v2
-; GFX10-NEXT: v_and_b32_sdwa v0, v0, s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_lshrrev_b16_e64 v4, 8, v5
+; GFX10-NEXT: v_and_b32_sdwa v1, v3, s5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v0, v0, s5 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_or_b32 v2, v4, s5, v2
; GFX10-NEXT: v_or3_b32 v0, v2, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i32 %lhs.arg to <4 x i8>
@@ -669,188 +557,107 @@ define amdgpu_ps i32 @s_uaddsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX8-LABEL: s_uaddsat_v4i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000
-; GFX8-NEXT: s_lshr_b32 s2, s0, 8
-; GFX8-NEXT: s_lshr_b32 s3, s0, 16
-; GFX8-NEXT: s_lshr_b32 s4, s0, 24
-; GFX8-NEXT: s_lshl_b32 s0, s0, s8
-; GFX8-NEXT: s_xor_b32 s9, s0, -1
; GFX8-NEXT: s_lshr_b32 s5, s1, 8
; GFX8-NEXT: s_lshr_b32 s6, s1, 16
; GFX8-NEXT: s_lshr_b32 s7, s1, 24
; GFX8-NEXT: s_lshl_b32 s1, s1, s8
-; GFX8-NEXT: s_bfe_u32 s9, s9, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s9, s1
-; GFX8-NEXT: s_cselect_b32 s1, s9, s1
-; GFX8-NEXT: s_add_i32 s0, s0, s1
-; GFX8-NEXT: s_lshl_b32 s1, s2, s8
-; GFX8-NEXT: s_lshl_b32 s2, s5, s8
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_xor_b32 s5, s1, -1
-; GFX8-NEXT: s_lshr_b32 s0, s0, s8
-; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s5, s2
-; GFX8-NEXT: s_cselect_b32 s2, s5, s2
-; GFX8-NEXT: s_add_i32 s1, s1, s2
-; GFX8-NEXT: s_lshl_b32 s2, s3, s8
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_lshl_b32 s3, s6, s8
-; GFX8-NEXT: s_xor_b32 s5, s2, -1
-; GFX8-NEXT: s_lshr_b32 s1, s1, s8
-; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s5, s3
-; GFX8-NEXT: s_cselect_b32 s3, s5, s3
-; GFX8-NEXT: s_add_i32 s2, s2, s3
-; GFX8-NEXT: s_lshl_b32 s3, s4, s8
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_lshl_b32 s4, s7, s8
-; GFX8-NEXT: s_xor_b32 s5, s3, -1
-; GFX8-NEXT: s_lshr_b32 s2, s2, s8
-; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s5, s4
-; GFX8-NEXT: s_cselect_b32 s4, s5, s4
-; GFX8-NEXT: s_add_i32 s3, s3, s4
-; GFX8-NEXT: s_movk_i32 s4, 0xff
-; GFX8-NEXT: s_and_b32 s1, s1, s4
-; GFX8-NEXT: s_and_b32 s0, s0, s4
-; GFX8-NEXT: s_lshl_b32 s1, s1, 8
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_or_b32 s0, s0, s1
-; GFX8-NEXT: s_and_b32 s1, s2, s4
-; GFX8-NEXT: s_lshl_b32 s1, s1, 16
-; GFX8-NEXT: s_lshr_b32 s3, s3, s8
-; GFX8-NEXT: s_or_b32 s0, s0, s1
-; GFX8-NEXT: s_and_b32 s1, s3, s4
-; GFX8-NEXT: s_lshl_b32 s1, s1, 24
-; GFX8-NEXT: s_or_b32 s0, s0, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: s_lshl_b32 s1, s5, s8
+; GFX8-NEXT: s_lshr_b32 s2, s0, 8
+; GFX8-NEXT: s_lshr_b32 s3, s0, 16
+; GFX8-NEXT: s_lshr_b32 s4, s0, 24
+; GFX8-NEXT: s_lshl_b32 s0, s0, s8
+; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_lshl_b32 s0, s2, s8
+; GFX8-NEXT: v_add_u16_e64 v1, s0, v1 clamp
+; GFX8-NEXT: v_mov_b32_e32 v4, 0xff
+; GFX8-NEXT: s_lshl_b32 s1, s6, s8
+; GFX8-NEXT: v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: s_lshl_b32 s0, s3, s8
+; GFX8-NEXT: s_lshl_b32 s1, s7, s8
+; GFX8-NEXT: v_add_u16_e64 v2, s0, v2 clamp
+; GFX8-NEXT: s_lshl_b32 s0, s4, s8
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_and_b32_sdwa v1, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_add_u16_e64 v3, s0, v3 clamp
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_v4i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s8, 8, 0x100000
-; GFX9-NEXT: s_lshr_b32 s2, s0, 8
-; GFX9-NEXT: s_lshr_b32 s3, s0, 16
-; GFX9-NEXT: s_lshr_b32 s4, s0, 24
-; GFX9-NEXT: s_lshl_b32 s0, s0, s8
-; GFX9-NEXT: s_xor_b32 s9, s0, -1
; GFX9-NEXT: s_lshr_b32 s5, s1, 8
; GFX9-NEXT: s_lshr_b32 s6, s1, 16
; GFX9-NEXT: s_lshr_b32 s7, s1, 24
; GFX9-NEXT: s_lshl_b32 s1, s1, s8
-; GFX9-NEXT: s_bfe_u32 s9, s9, 0x100000
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s9, s1
-; GFX9-NEXT: s_cselect_b32 s1, s9, s1
-; GFX9-NEXT: s_add_i32 s0, s0, s1
-; GFX9-NEXT: s_lshl_b32 s1, s2, s8
-; GFX9-NEXT: s_lshl_b32 s2, s5, s8
-; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX9-NEXT: s_xor_b32 s5, s1, -1
-; GFX9-NEXT: s_lshr_b32 s0, s0, s8
-; GFX9-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX9-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s5, s2
-; GFX9-NEXT: s_cselect_b32 s2, s5, s2
-; GFX9-NEXT: s_add_i32 s1, s1, s2
-; GFX9-NEXT: s_lshl_b32 s2, s3, s8
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: s_lshl_b32 s3, s6, s8
-; GFX9-NEXT: s_xor_b32 s5, s2, -1
-; GFX9-NEXT: s_lshr_b32 s1, s1, s8
-; GFX9-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX9-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s5, s3
-; GFX9-NEXT: s_cselect_b32 s3, s5, s3
-; GFX9-NEXT: s_add_i32 s2, s2, s3
-; GFX9-NEXT: s_lshl_b32 s3, s4, s8
-; GFX9-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX9-NEXT: s_lshl_b32 s4, s7, s8
-; GFX9-NEXT: s_xor_b32 s5, s3, -1
-; GFX9-NEXT: s_lshr_b32 s2, s2, s8
-; GFX9-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX9-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s5, s4
-; GFX9-NEXT: s_cselect_b32 s4, s5, s4
-; GFX9-NEXT: s_add_i32 s3, s3, s4
-; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: s_and_b32 s1, s1, s4
-; GFX9-NEXT: s_and_b32 s0, s0, s4
-; GFX9-NEXT: s_lshl_b32 s1, s1, 8
-; GFX9-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: s_and_b32 s1, s2, s4
-; GFX9-NEXT: s_lshl_b32 s1, s1, 16
-; GFX9-NEXT: s_lshr_b32 s3, s3, s8
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: s_and_b32 s1, s3, s4
-; GFX9-NEXT: s_lshl_b32 s1, s1, 24
-; GFX9-NEXT: s_or_b32 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: s_lshl_b32 s1, s5, s8
+; GFX9-NEXT: s_lshr_b32 s2, s0, 8
+; GFX9-NEXT: s_lshr_b32 s3, s0, 16
+; GFX9-NEXT: s_lshr_b32 s4, s0, 24
+; GFX9-NEXT: s_lshl_b32 s0, s0, s8
+; GFX9-NEXT: v_add_u16_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: s_lshl_b32 s0, s2, s8
+; GFX9-NEXT: s_lshl_b32 s1, s6, s8
+; GFX9-NEXT: v_add_u16_e64 v1, s0, v1 clamp
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-NEXT: s_lshl_b32 s0, s3, s8
+; GFX9-NEXT: s_lshl_b32 s1, s7, s8
+; GFX9-NEXT: v_add_u16_e64 v2, s0, v2 clamp
+; GFX9-NEXT: s_lshl_b32 s0, s4, s8
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_add_u16_e64 v3, s0, v3 clamp
+; GFX9-NEXT: s_movk_i32 s0, 0xff
+; GFX9-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v1
+; GFX9-NEXT: v_and_b32_sdwa v1, v2, s0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_sdwa v2, v3, s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_v4i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s5, 8, 0x100000
; GFX10-NEXT: s_lshr_b32 s2, s0, 8
+; GFX10-NEXT: s_lshr_b32 s6, s1, 8
+; GFX10-NEXT: s_lshl_b32 s2, s2, s5
+; GFX10-NEXT: s_lshl_b32 s6, s6, s5
; GFX10-NEXT: s_lshr_b32 s3, s0, 16
+; GFX10-NEXT: v_add_nc_u16_e64 v1, s2, s6 clamp
; GFX10-NEXT: s_lshr_b32 s4, s0, 24
+; GFX10-NEXT: s_movk_i32 s2, 0xff
; GFX10-NEXT: s_lshl_b32 s0, s0, s5
-; GFX10-NEXT: s_lshl_b32 s9, s1, s5
-; GFX10-NEXT: s_xor_b32 s8, s0, -1
-; GFX10-NEXT: s_bfe_u32 s9, s9, 0x100000
-; GFX10-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX10-NEXT: s_lshr_b32 s6, s1, 8
-; GFX10-NEXT: s_lshr_b32 s7, s1, 16
+; GFX10-NEXT: s_lshl_b32 s7, s1, s5
+; GFX10-NEXT: v_and_b32_sdwa v1, v1, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, s7 clamp
+; GFX10-NEXT: s_lshr_b32 s0, s1, 16
; GFX10-NEXT: s_lshr_b32 s1, s1, 24
-; GFX10-NEXT: s_cmp_lt_u32 s8, s9
-; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s8, s8, s9
-; GFX10-NEXT: s_lshl_b32 s2, s2, s5
-; GFX10-NEXT: s_add_i32 s0, s0, s8
-; GFX10-NEXT: s_xor_b32 s8, s2, -1
-; GFX10-NEXT: s_lshl_b32 s6, s6, s5
-; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX10-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX10-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX10-NEXT: s_lshr_b32 s0, s0, s5
-; GFX10-NEXT: s_cmp_lt_u32 s8, s6
-; GFX10-NEXT: s_cselect_b32 s6, s8, s6
; GFX10-NEXT: s_lshl_b32 s3, s3, s5
-; GFX10-NEXT: s_add_i32 s2, s2, s6
-; GFX10-NEXT: s_xor_b32 s6, s3, -1
-; GFX10-NEXT: s_lshl_b32 s7, s7, s5
-; GFX10-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX10-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX10-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX10-NEXT: s_lshr_b32 s2, s2, s5
-; GFX10-NEXT: s_cmp_lt_u32 s6, s7
-; GFX10-NEXT: s_cselect_b32 s6, s6, s7
+; GFX10-NEXT: s_lshl_b32 s0, s0, s5
; GFX10-NEXT: s_lshl_b32 s4, s4, s5
-; GFX10-NEXT: s_add_i32 s3, s3, s6
-; GFX10-NEXT: s_xor_b32 s6, s4, -1
; GFX10-NEXT: s_lshl_b32 s1, s1, s5
-; GFX10-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX10-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: s_lshr_b32 s3, s3, s5
-; GFX10-NEXT: s_cmp_lt_u32 s6, s1
-; GFX10-NEXT: s_cselect_b32 s1, s6, s1
-; GFX10-NEXT: s_add_i32 s4, s4, s1
-; GFX10-NEXT: s_bfe_u32 s1, s4, 0x100000
-; GFX10-NEXT: s_movk_i32 s4, 0xff
-; GFX10-NEXT: s_lshr_b32 s1, s1, s5
-; GFX10-NEXT: s_and_b32 s2, s2, s4
-; GFX10-NEXT: s_and_b32 s0, s0, s4
-; GFX10-NEXT: s_lshl_b32 s2, s2, 8
-; GFX10-NEXT: s_and_b32 s3, s3, s4
-; GFX10-NEXT: s_and_b32 s1, s1, s4
-; GFX10-NEXT: s_or_b32 s0, s0, s2
-; GFX10-NEXT: s_lshl_b32 s2, s3, 16
-; GFX10-NEXT: s_lshl_b32 s1, s1, 24
-; GFX10-NEXT: s_or_b32 s0, s0, s2
-; GFX10-NEXT: s_or_b32 s0, s0, s1
+; GFX10-NEXT: v_lshrrev_b16_e64 v0, 8, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX10-NEXT: v_add_nc_u16_e64 v2, s3, s0 clamp
+; GFX10-NEXT: v_add_nc_u16_e64 v3, s4, s1 clamp
+; GFX10-NEXT: ; implicit-def: $vcc_hi
+; GFX10-NEXT: v_and_or_b32 v0, v0, s2, v1
+; GFX10-NEXT: v_and_b32_sdwa v1, v2, s2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v2, v3, s2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
@@ -876,9 +683,7 @@ define i24 @v_uaddsat_i24(i24 %lhs, i24 %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX8-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX8-NEXT: v_min_u32_e32 v1, v2, v1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
+; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v1 clamp
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -887,9 +692,7 @@ define i24 @v_uaddsat_i24(i24 %lhs, i24 %rhs) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX9-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX9-NEXT: v_min_u32_e32 v1, v2, v1
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u32_e64 v0, v0, v1 clamp
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -900,9 +703,7 @@ define i24 @v_uaddsat_i24(i24 %lhs, i24 %rhs) {
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX10-NEXT: v_min_u32_e32 v1, v2, v1
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
+; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v1 clamp
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.uadd.sat.i24(i24 %lhs, i24 %rhs)
@@ -923,36 +724,32 @@ define amdgpu_ps i24 @s_uaddsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
;
; GFX8-LABEL: s_uaddsat_i24:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_lshl_b32 s0, s0, 8
; GFX8-NEXT: s_lshl_b32 s1, s1, 8
-; GFX8-NEXT: s_not_b32 s2, s0
-; GFX8-NEXT: s_cmp_lt_u32 s2, s1
-; GFX8-NEXT: s_cselect_b32 s1, s2, s1
-; GFX8-NEXT: s_add_i32 s0, s0, s1
-; GFX8-NEXT: s_lshr_b32 s0, s0, 8
+; GFX8-NEXT: s_lshl_b32 s0, s0, 8
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_add_u32_e64 v0, s[0:1], s0, v0 clamp
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_i24:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshl_b32 s0, s0, 8
; GFX9-NEXT: s_lshl_b32 s1, s1, 8
-; GFX9-NEXT: s_not_b32 s2, s0
-; GFX9-NEXT: s_cmp_lt_u32 s2, s1
-; GFX9-NEXT: s_cselect_b32 s1, s2, s1
-; GFX9-NEXT: s_add_i32 s0, s0, s1
-; GFX9-NEXT: s_lshr_b32 s0, s0, 8
+; GFX9-NEXT: s_lshl_b32 s0, s0, 8
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshl_b32 s0, s0, 8
; GFX10-NEXT: s_lshl_b32 s1, s1, 8
-; GFX10-NEXT: s_not_b32 s2, s0
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cmp_lt_u32 s2, s1
-; GFX10-NEXT: s_cselect_b32 s1, s2, s1
-; GFX10-NEXT: s_add_i32 s0, s0, s1
-; GFX10-NEXT: s_lshr_b32 s0, s0, 8
+; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s1 clamp
+; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i24 @llvm.uadd.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result
@@ -970,27 +767,21 @@ define i32 @v_uaddsat_i32(i32 %lhs, i32 %rhs) {
; GFX8-LABEL: v_uaddsat_i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX8-NEXT: v_min_u32_e32 v1, v2, v1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
+; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v1 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uaddsat_i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX9-NEXT: v_min_u32_e32 v1, v2, v1
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u32_e64 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uaddsat_i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v2, -1, v0
+; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u32_e32 v1, v2, v1
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
@@ -1007,27 +798,23 @@ define amdgpu_ps i32 @s_uaddsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
;
; GFX8-LABEL: s_uaddsat_i32:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_not_b32 s2, s0
-; GFX8-NEXT: s_cmp_lt_u32 s2, s1
-; GFX8-NEXT: s_cselect_b32 s1, s2, s1
-; GFX8-NEXT: s_add_i32 s0, s0, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_add_u32_e64 v0, s[0:1], s0, v0 clamp
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_not_b32 s2, s0
-; GFX9-NEXT: s_cmp_lt_u32 s2, s1
-; GFX9-NEXT: s_cselect_b32 s1, s2, s1
-; GFX9-NEXT: s_add_i32 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_not_b32 s2, s0
+; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cmp_lt_u32 s2, s1
-; GFX10-NEXT: s_cselect_b32 s1, s2, s1
-; GFX10-NEXT: s_add_i32 s0, s0, s1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
@@ -1043,24 +830,18 @@ define amdgpu_ps float @uaddsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
;
; GFX8-LABEL: uaddsat_i32_sv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_not_b32 s1, s0
-; GFX8-NEXT: v_min_u32_e32 v0, s1, v0
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
+; GFX8-NEXT: v_add_u32_e64 v0, s[0:1], s0, v0 clamp
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: uaddsat_i32_sv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_not_b32 s1, s0
-; GFX9-NEXT: v_min_u32_e32 v0, s1, v0
-; GFX9-NEXT: v_add_u32_e32 v0, s0, v0
+; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: uaddsat_i32_sv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_not_b32 s1, s0
+; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, v0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u32_e32 v0, s1, v0
-; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
@@ -1077,24 +858,18 @@ define amdgpu_ps float @uaddsat_i32_vs(i32 %lhs, i32 inreg %rhs) {
;
; GFX8-LABEL: uaddsat_i32_vs:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_xor_b32_e32 v1, -1, v0
-; GFX8-NEXT: v_min_u32_e32 v1, s0, v1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v1
+; GFX8-NEXT: v_add_u32_e64 v0, s[0:1], v0, s0 clamp
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: uaddsat_i32_vs:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_xor_b32_e32 v1, -1, v0
-; GFX9-NEXT: v_min_u32_e32 v1, s0, v1
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u32_e64 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: uaddsat_i32_vs:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_xor_b32_e32 v1, -1, v0
+; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, s0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u32_e32 v1, s0, v1
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
@@ -1116,36 +891,24 @@ define <2 x i32> @v_uaddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX8-LABEL: v_uaddsat_v2i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v4, -1, v0
-; GFX8-NEXT: v_min_u32_e32 v2, v4, v2
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
-; GFX8-NEXT: v_xor_b32_e32 v2, -1, v1
-; GFX8-NEXT: v_min_u32_e32 v2, v2, v3
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v2
+; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v2 clamp
+; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v3 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uaddsat_v2i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_xor_b32_e32 v4, -1, v0
-; GFX9-NEXT: v_min_u32_e32 v2, v4, v2
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
-; GFX9-NEXT: v_xor_b32_e32 v2, -1, v1
-; GFX9-NEXT: v_min_u32_e32 v2, v2, v3
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v2
+; GFX9-NEXT: v_add_u32_e64 v0, v0, v2 clamp
+; GFX9-NEXT: v_add_u32_e64 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uaddsat_v2i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v4, -1, v0
-; GFX10-NEXT: v_xor_b32_e32 v5, -1, v1
+; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v2 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u32_e32 v2, v4, v2
-; GFX10-NEXT: v_min_u32_e32 v3, v5, v3
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
@@ -1166,39 +929,31 @@ define amdgpu_ps <2 x i32> @s_uaddsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inre
;
; GFX8-LABEL: s_uaddsat_v2i32:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_not_b32 s4, s0
-; GFX8-NEXT: s_cmp_lt_u32 s4, s2
-; GFX8-NEXT: s_cselect_b32 s2, s4, s2
-; GFX8-NEXT: s_add_i32 s0, s0, s2
-; GFX8-NEXT: s_not_b32 s2, s1
-; GFX8-NEXT: s_cmp_lt_u32 s2, s3
-; GFX8-NEXT: s_cselect_b32 s2, s2, s3
-; GFX8-NEXT: s_add_i32 s1, s1, s2
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], s0, v0 clamp
+; GFX8-NEXT: v_add_u32_e64 v1, s[0:1], s1, v1 clamp
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_v2i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_not_b32 s4, s0
-; GFX9-NEXT: s_cmp_lt_u32 s4, s2
-; GFX9-NEXT: s_cselect_b32 s2, s4, s2
-; GFX9-NEXT: s_add_i32 s0, s0, s2
-; GFX9-NEXT: s_not_b32 s2, s1
-; GFX9-NEXT: s_cmp_lt_u32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s2, s3
-; GFX9-NEXT: s_add_i32 s1, s1, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_add_u32_e64 v1, s1, v1 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_v2i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_not_b32 s4, s0
+; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s2 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cmp_lt_u32 s4, s2
-; GFX10-NEXT: s_cselect_b32 s2, s4, s2
-; GFX10-NEXT: s_not_b32 s4, s1
-; GFX10-NEXT: s_add_i32 s0, s0, s2
-; GFX10-NEXT: s_cmp_lt_u32 s4, s3
-; GFX10-NEXT: s_cselect_b32 s2, s4, s3
-; GFX10-NEXT: s_add_i32 s1, s1, s2
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
@@ -1222,45 +977,27 @@ define <3 x i32> @v_uaddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX8-LABEL: v_uaddsat_v3i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v6, -1, v0
-; GFX8-NEXT: v_min_u32_e32 v3, v6, v3
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v3
-; GFX8-NEXT: v_xor_b32_e32 v3, -1, v1
-; GFX8-NEXT: v_min_u32_e32 v3, v3, v4
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
-; GFX8-NEXT: v_xor_b32_e32 v3, -1, v2
-; GFX8-NEXT: v_min_u32_e32 v3, v3, v5
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
+; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v3 clamp
+; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v4 clamp
+; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v5 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uaddsat_v3i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_xor_b32_e32 v6, -1, v0
-; GFX9-NEXT: v_min_u32_e32 v3, v6, v3
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v3
-; GFX9-NEXT: v_xor_b32_e32 v3, -1, v1
-; GFX9-NEXT: v_min_u32_e32 v3, v3, v4
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT: v_xor_b32_e32 v3, -1, v2
-; GFX9-NEXT: v_min_u32_e32 v3, v3, v5
-; GFX9-NEXT: v_add_u32_e32 v2, v2, v3
+; GFX9-NEXT: v_add_u32_e64 v0, v0, v3 clamp
+; GFX9-NEXT: v_add_u32_e64 v1, v1, v4 clamp
+; GFX9-NEXT: v_add_u32_e64 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uaddsat_v3i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v6, -1, v0
-; GFX10-NEXT: v_xor_b32_e32 v7, -1, v1
-; GFX10-NEXT: v_xor_b32_e32 v8, -1, v2
+; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v3 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v4 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u32_e32 v3, v6, v3
-; GFX10-NEXT: v_min_u32_e32 v4, v7, v4
-; GFX10-NEXT: v_min_u32_e32 v5, v8, v5
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v3
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v4
-; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
@@ -1285,51 +1022,39 @@ define amdgpu_ps <3 x i32> @s_uaddsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inre
;
; GFX8-LABEL: s_uaddsat_v3i32:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_not_b32 s6, s0
-; GFX8-NEXT: s_cmp_lt_u32 s6, s3
-; GFX8-NEXT: s_cselect_b32 s3, s6, s3
-; GFX8-NEXT: s_add_i32 s0, s0, s3
-; GFX8-NEXT: s_not_b32 s3, s1
-; GFX8-NEXT: s_cmp_lt_u32 s3, s4
-; GFX8-NEXT: s_cselect_b32 s3, s3, s4
-; GFX8-NEXT: s_add_i32 s1, s1, s3
-; GFX8-NEXT: s_not_b32 s3, s2
-; GFX8-NEXT: s_cmp_lt_u32 s3, s5
-; GFX8-NEXT: s_cselect_b32 s3, s3, s5
-; GFX8-NEXT: s_add_i32 s2, s2, s3
+; GFX8-NEXT: v_mov_b32_e32 v0, s3
+; GFX8-NEXT: v_mov_b32_e32 v1, s4
+; GFX8-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NEXT: v_add_u32_e64 v0, s[6:7], s0, v0 clamp
+; GFX8-NEXT: v_add_u32_e64 v1, s[0:1], s1, v1 clamp
+; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], s2, v2 clamp
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_v3i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_not_b32 s6, s0
-; GFX9-NEXT: s_cmp_lt_u32 s6, s3
-; GFX9-NEXT: s_cselect_b32 s3, s6, s3
-; GFX9-NEXT: s_add_i32 s0, s0, s3
-; GFX9-NEXT: s_not_b32 s3, s1
-; GFX9-NEXT: s_cmp_lt_u32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s3, s3, s4
-; GFX9-NEXT: s_add_i32 s1, s1, s3
-; GFX9-NEXT: s_not_b32 s3, s2
-; GFX9-NEXT: s_cmp_lt_u32 s3, s5
-; GFX9-NEXT: s_cselect_b32 s3, s3, s5
-; GFX9-NEXT: s_add_i32 s2, s2, s3
+; GFX9-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_add_u32_e64 v1, s1, v1 clamp
+; GFX9-NEXT: v_add_u32_e64 v2, s2, v2 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_v3i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_not_b32 s6, s0
+; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s3 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s4 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v2, s2, s5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cmp_lt_u32 s6, s3
-; GFX10-NEXT: s_cselect_b32 s3, s6, s3
-; GFX10-NEXT: s_not_b32 s6, s1
-; GFX10-NEXT: s_add_i32 s0, s0, s3
-; GFX10-NEXT: s_cmp_lt_u32 s6, s4
-; GFX10-NEXT: s_cselect_b32 s3, s6, s4
-; GFX10-NEXT: s_not_b32 s4, s2
-; GFX10-NEXT: s_add_i32 s1, s1, s3
-; GFX10-NEXT: s_cmp_lt_u32 s4, s5
-; GFX10-NEXT: s_cselect_b32 s3, s4, s5
-; GFX10-NEXT: s_add_i32 s2, s2, s3
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: ; return to shader part epilog
%result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
@@ -1356,54 +1081,30 @@ define <4 x i32> @v_uaddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX8-LABEL: v_uaddsat_v4i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v8, -1, v0
-; GFX8-NEXT: v_min_u32_e32 v4, v8, v4
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v4
-; GFX8-NEXT: v_xor_b32_e32 v4, -1, v1
-; GFX8-NEXT: v_min_u32_e32 v4, v4, v5
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v4
-; GFX8-NEXT: v_xor_b32_e32 v4, -1, v2
-; GFX8-NEXT: v_min_u32_e32 v4, v4, v6
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v4
-; GFX8-NEXT: v_xor_b32_e32 v4, -1, v3
-; GFX8-NEXT: v_min_u32_e32 v4, v4, v7
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v4
+; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v4 clamp
+; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v5 clamp
+; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v6 clamp
+; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v7 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uaddsat_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_xor_b32_e32 v8, -1, v0
-; GFX9-NEXT: v_min_u32_e32 v4, v8, v4
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v4
-; GFX9-NEXT: v_xor_b32_e32 v4, -1, v1
-; GFX9-NEXT: v_min_u32_e32 v4, v4, v5
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v4
-; GFX9-NEXT: v_xor_b32_e32 v4, -1, v2
-; GFX9-NEXT: v_min_u32_e32 v4, v4, v6
-; GFX9-NEXT: v_add_u32_e32 v2, v2, v4
-; GFX9-NEXT: v_xor_b32_e32 v4, -1, v3
-; GFX9-NEXT: v_min_u32_e32 v4, v4, v7
-; GFX9-NEXT: v_add_u32_e32 v3, v3, v4
+; GFX9-NEXT: v_add_u32_e64 v0, v0, v4 clamp
+; GFX9-NEXT: v_add_u32_e64 v1, v1, v5 clamp
+; GFX9-NEXT: v_add_u32_e64 v2, v2, v6 clamp
+; GFX9-NEXT: v_add_u32_e64 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uaddsat_v4i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v15, -1, v0
-; GFX10-NEXT: v_xor_b32_e32 v19, -1, v1
-; GFX10-NEXT: v_xor_b32_e32 v23, -1, v2
-; GFX10-NEXT: v_xor_b32_e32 v10, -1, v3
+; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v4 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v5 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v6 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u32_e32 v11, v15, v4
-; GFX10-NEXT: v_min_u32_e32 v15, v19, v5
-; GFX10-NEXT: v_min_u32_e32 v19, v23, v6
-; GFX10-NEXT: v_min_u32_e32 v6, v10, v7
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v11
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v15
-; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v19
-; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v6
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
@@ -1432,63 +1133,47 @@ define amdgpu_ps <4 x i32> @s_uaddsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inre
;
; GFX8-LABEL: s_uaddsat_v4i32:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_not_b32 s8, s0
-; GFX8-NEXT: s_cmp_lt_u32 s8, s4
-; GFX8-NEXT: s_cselect_b32 s4, s8, s4
-; GFX8-NEXT: s_add_i32 s0, s0, s4
-; GFX8-NEXT: s_not_b32 s4, s1
-; GFX8-NEXT: s_cmp_lt_u32 s4, s5
-; GFX8-NEXT: s_cselect_b32 s4, s4, s5
-; GFX8-NEXT: s_add_i32 s1, s1, s4
-; GFX8-NEXT: s_not_b32 s4, s2
-; GFX8-NEXT: s_cmp_lt_u32 s4, s6
-; GFX8-NEXT: s_cselect_b32 s4, s4, s6
-; GFX8-NEXT: s_add_i32 s2, s2, s4
-; GFX8-NEXT: s_not_b32 s4, s3
-; GFX8-NEXT: s_cmp_lt_u32 s4, s7
-; GFX8-NEXT: s_cselect_b32 s4, s4, s7
-; GFX8-NEXT: s_add_i32 s3, s3, s4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_add_u32_e64 v0, s[8:9], s0, v0 clamp
+; GFX8-NEXT: v_add_u32_e64 v1, s[0:1], s1, v1 clamp
+; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], s2, v2 clamp
+; GFX8-NEXT: v_add_u32_e64 v3, s[0:1], s3, v3 clamp
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
+; GFX8-NEXT: v_readfirstlane_b32 s3, v3
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_v4i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_not_b32 s8, s0
-; GFX9-NEXT: s_cmp_lt_u32 s8, s4
-; GFX9-NEXT: s_cselect_b32 s4, s8, s4
-; GFX9-NEXT: s_add_i32 s0, s0, s4
-; GFX9-NEXT: s_not_b32 s4, s1
-; GFX9-NEXT: s_cmp_lt_u32 s4, s5
-; GFX9-NEXT: s_cselect_b32 s4, s4, s5
-; GFX9-NEXT: s_add_i32 s1, s1, s4
-; GFX9-NEXT: s_not_b32 s4, s2
-; GFX9-NEXT: s_cmp_lt_u32 s4, s6
-; GFX9-NEXT: s_cselect_b32 s4, s4, s6
-; GFX9-NEXT: s_add_i32 s2, s2, s4
-; GFX9-NEXT: s_not_b32 s4, s3
-; GFX9-NEXT: s_cmp_lt_u32 s4, s7
-; GFX9-NEXT: s_cselect_b32 s4, s4, s7
-; GFX9-NEXT: s_add_i32 s3, s3, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_add_u32_e64 v1, s1, v1 clamp
+; GFX9-NEXT: v_add_u32_e64 v2, s2, v2 clamp
+; GFX9-NEXT: v_add_u32_e64 v3, s3, v3 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_v4i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_not_b32 s8, s0
+; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s4 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s5 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v2, s2, s6 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v3, s3, s7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cmp_lt_u32 s8, s4
-; GFX10-NEXT: s_cselect_b32 s4, s8, s4
-; GFX10-NEXT: s_not_b32 s8, s1
-; GFX10-NEXT: s_add_i32 s0, s0, s4
-; GFX10-NEXT: s_cmp_lt_u32 s8, s5
-; GFX10-NEXT: s_cselect_b32 s4, s8, s5
-; GFX10-NEXT: s_not_b32 s5, s2
-; GFX10-NEXT: s_add_i32 s1, s1, s4
-; GFX10-NEXT: s_cmp_lt_u32 s5, s6
-; GFX10-NEXT: s_cselect_b32 s4, s5, s6
-; GFX10-NEXT: s_not_b32 s5, s3
-; GFX10-NEXT: s_add_i32 s2, s2, s4
-; GFX10-NEXT: s_cmp_lt_u32 s5, s7
-; GFX10-NEXT: s_cselect_b32 s4, s5, s7
-; GFX10-NEXT: s_add_i32 s3, s3, s4
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: ; return to shader part epilog
%result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
@@ -1518,62 +1203,32 @@ define <5 x i32> @v_uaddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX8-LABEL: v_uaddsat_v5i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v10, -1, v0
-; GFX8-NEXT: v_min_u32_e32 v5, v10, v5
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v5
-; GFX8-NEXT: v_xor_b32_e32 v5, -1, v1
-; GFX8-NEXT: v_min_u32_e32 v5, v5, v6
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v5
-; GFX8-NEXT: v_xor_b32_e32 v5, -1, v2
-; GFX8-NEXT: v_min_u32_e32 v5, v5, v7
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5
-; GFX8-NEXT: v_xor_b32_e32 v5, -1, v3
-; GFX8-NEXT: v_min_u32_e32 v5, v5, v8
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v5
-; GFX8-NEXT: v_xor_b32_e32 v5, -1, v4
-; GFX8-NEXT: v_min_u32_e32 v5, v5, v9
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v5
+; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v5 clamp
+; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v6 clamp
+; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v7 clamp
+; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v8 clamp
+; GFX8-NEXT: v_add_u32_e64 v4, s[4:5], v4, v9 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uaddsat_v5i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_xor_b32_e32 v10, -1, v0
-; GFX9-NEXT: v_min_u32_e32 v5, v10, v5
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v5
-; GFX9-NEXT: v_xor_b32_e32 v5, -1, v1
-; GFX9-NEXT: v_min_u32_e32 v5, v5, v6
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v5
-; GFX9-NEXT: v_xor_b32_e32 v5, -1, v2
-; GFX9-NEXT: v_min_u32_e32 v5, v5, v7
-; GFX9-NEXT: v_add_u32_e32 v2, v2, v5
-; GFX9-NEXT: v_xor_b32_e32 v5, -1, v3
-; GFX9-NEXT: v_min_u32_e32 v5, v5, v8
-; GFX9-NEXT: v_add_u32_e32 v3, v3, v5
-; GFX9-NEXT: v_xor_b32_e32 v5, -1, v4
-; GFX9-NEXT: v_min_u32_e32 v5, v5, v9
-; GFX9-NEXT: v_add_u32_e32 v4, v4, v5
+; GFX9-NEXT: v_add_u32_e64 v0, v0, v5 clamp
+; GFX9-NEXT: v_add_u32_e64 v1, v1, v6 clamp
+; GFX9-NEXT: v_add_u32_e64 v2, v2, v7 clamp
+; GFX9-NEXT: v_add_u32_e64 v3, v3, v8 clamp
+; GFX9-NEXT: v_add_u32_e64 v4, v4, v9 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uaddsat_v5i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v10, -1, v0
-; GFX10-NEXT: v_xor_b32_e32 v11, -1, v1
-; GFX10-NEXT: v_xor_b32_e32 v12, -1, v2
-; GFX10-NEXT: v_xor_b32_e32 v13, -1, v3
-; GFX10-NEXT: v_xor_b32_e32 v14, -1, v4
-; GFX10-NEXT: v_min_u32_e32 v5, v10, v5
-; GFX10-NEXT: v_min_u32_e32 v6, v11, v6
-; GFX10-NEXT: v_min_u32_e32 v7, v12, v7
-; GFX10-NEXT: v_min_u32_e32 v8, v13, v8
-; GFX10-NEXT: v_min_u32_e32 v9, v14, v9
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v5
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v6
-; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v7
-; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v8
-; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v9
+; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v5 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v6 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v7 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v8 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v4, v4, v9 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
@@ -1607,75 +1262,55 @@ define amdgpu_ps <5 x i32> @s_uaddsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inre
;
; GFX8-LABEL: s_uaddsat_v5i32:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_not_b32 s10, s0
-; GFX8-NEXT: s_cmp_lt_u32 s10, s5
-; GFX8-NEXT: s_cselect_b32 s5, s10, s5
-; GFX8-NEXT: s_add_i32 s0, s0, s5
-; GFX8-NEXT: s_not_b32 s5, s1
-; GFX8-NEXT: s_cmp_lt_u32 s5, s6
-; GFX8-NEXT: s_cselect_b32 s5, s5, s6
-; GFX8-NEXT: s_add_i32 s1, s1, s5
-; GFX8-NEXT: s_not_b32 s5, s2
-; GFX8-NEXT: s_cmp_lt_u32 s5, s7
-; GFX8-NEXT: s_cselect_b32 s5, s5, s7
-; GFX8-NEXT: s_add_i32 s2, s2, s5
-; GFX8-NEXT: s_not_b32 s5, s3
-; GFX8-NEXT: s_cmp_lt_u32 s5, s8
-; GFX8-NEXT: s_cselect_b32 s5, s5, s8
-; GFX8-NEXT: s_add_i32 s3, s3, s5
-; GFX8-NEXT: s_not_b32 s5, s4
-; GFX8-NEXT: s_cmp_lt_u32 s5, s9
-; GFX8-NEXT: s_cselect_b32 s5, s5, s9
-; GFX8-NEXT: s_add_i32 s4, s4, s5
+; GFX8-NEXT: v_mov_b32_e32 v0, s5
+; GFX8-NEXT: v_mov_b32_e32 v1, s6
+; GFX8-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NEXT: v_mov_b32_e32 v3, s8
+; GFX8-NEXT: v_mov_b32_e32 v4, s9
+; GFX8-NEXT: v_add_u32_e64 v0, s[10:11], s0, v0 clamp
+; GFX8-NEXT: v_add_u32_e64 v1, s[0:1], s1, v1 clamp
+; GFX8-NEXT: v_add_u32_e64 v2, s[0:1], s2, v2 clamp
+; GFX8-NEXT: v_add_u32_e64 v3, s[0:1], s3, v3 clamp
+; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], s4, v4 clamp
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
+; GFX8-NEXT: v_readfirstlane_b32 s3, v3
+; GFX8-NEXT: v_readfirstlane_b32 s4, v4
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_v5i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_not_b32 s10, s0
-; GFX9-NEXT: s_cmp_lt_u32 s10, s5
-; GFX9-NEXT: s_cselect_b32 s5, s10, s5
-; GFX9-NEXT: s_add_i32 s0, s0, s5
-; GFX9-NEXT: s_not_b32 s5, s1
-; GFX9-NEXT: s_cmp_lt_u32 s5, s6
-; GFX9-NEXT: s_cselect_b32 s5, s5, s6
-; GFX9-NEXT: s_add_i32 s1, s1, s5
-; GFX9-NEXT: s_not_b32 s5, s2
-; GFX9-NEXT: s_cmp_lt_u32 s5, s7
-; GFX9-NEXT: s_cselect_b32 s5, s5, s7
-; GFX9-NEXT: s_add_i32 s2, s2, s5
-; GFX9-NEXT: s_not_b32 s5, s3
-; GFX9-NEXT: s_cmp_lt_u32 s5, s8
-; GFX9-NEXT: s_cselect_b32 s5, s5, s8
-; GFX9-NEXT: s_add_i32 s3, s3, s5
-; GFX9-NEXT: s_not_b32 s5, s4
-; GFX9-NEXT: s_cmp_lt_u32 s5, s9
-; GFX9-NEXT: s_cselect_b32 s5, s5, s9
-; GFX9-NEXT: s_add_i32 s4, s4, s5
+; GFX9-NEXT: v_mov_b32_e32 v0, s5
+; GFX9-NEXT: v_mov_b32_e32 v1, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s7
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
+; GFX9-NEXT: v_mov_b32_e32 v4, s9
+; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_add_u32_e64 v1, s1, v1 clamp
+; GFX9-NEXT: v_add_u32_e64 v2, s2, v2 clamp
+; GFX9-NEXT: v_add_u32_e64 v3, s3, v3 clamp
+; GFX9-NEXT: v_add_u32_e64 v4, s4, v4 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
+; GFX9-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_v5i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_not_b32 s10, s0
+; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s5 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s6 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v2, s2, s7 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v3, s3, s8 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v4, s4, s9 clamp
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10-NEXT: v_readfirstlane_b32 s4, v4
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cmp_lt_u32 s10, s5
-; GFX10-NEXT: s_cselect_b32 s5, s10, s5
-; GFX10-NEXT: s_not_b32 s10, s1
-; GFX10-NEXT: s_add_i32 s0, s0, s5
-; GFX10-NEXT: s_cmp_lt_u32 s10, s6
-; GFX10-NEXT: s_cselect_b32 s5, s10, s6
-; GFX10-NEXT: s_not_b32 s6, s2
-; GFX10-NEXT: s_add_i32 s1, s1, s5
-; GFX10-NEXT: s_cmp_lt_u32 s6, s7
-; GFX10-NEXT: s_cselect_b32 s5, s6, s7
-; GFX10-NEXT: s_not_b32 s6, s3
-; GFX10-NEXT: s_add_i32 s2, s2, s5
-; GFX10-NEXT: s_cmp_lt_u32 s6, s8
-; GFX10-NEXT: s_cselect_b32 s5, s6, s8
-; GFX10-NEXT: s_not_b32 s6, s4
-; GFX10-NEXT: s_add_i32 s3, s3, s5
-; GFX10-NEXT: s_cmp_lt_u32 s6, s9
-; GFX10-NEXT: s_cselect_b32 s5, s6, s9
-; GFX10-NEXT: s_add_i32 s4, s4, s5
; GFX10-NEXT: ; return to shader part epilog
%result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result
@@ -1738,162 +1373,66 @@ define <16 x i32> @v_uaddsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
; GFX8-LABEL: v_uaddsat_v16i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v32, -1, v0
-; GFX8-NEXT: v_min_u32_e32 v16, v32, v16
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v1
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v17
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v2
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v18
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v3
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v19
-; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v4
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v20
-; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v5
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v21
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v6
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v22
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v7
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v23
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v8
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v24
-; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v9
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v25
-; GFX8-NEXT: v_add_u32_e32 v9, vcc, v9, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v10
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v26
-; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v11
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v27
-; GFX8-NEXT: v_add_u32_e32 v11, vcc, v11, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v12
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v28
-; GFX8-NEXT: v_add_u32_e32 v12, vcc, v12, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v13
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v29
-; GFX8-NEXT: v_add_u32_e32 v13, vcc, v13, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v14
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v30
-; GFX8-NEXT: v_add_u32_e32 v14, vcc, v14, v16
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v15
-; GFX8-NEXT: v_min_u32_e32 v16, v16, v31
-; GFX8-NEXT: v_add_u32_e32 v15, vcc, v15, v16
+; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v16 clamp
+; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v1, v17 clamp
+; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v2, v18 clamp
+; GFX8-NEXT: v_add_u32_e64 v3, s[4:5], v3, v19 clamp
+; GFX8-NEXT: v_add_u32_e64 v4, s[4:5], v4, v20 clamp
+; GFX8-NEXT: v_add_u32_e64 v5, s[4:5], v5, v21 clamp
+; GFX8-NEXT: v_add_u32_e64 v6, s[4:5], v6, v22 clamp
+; GFX8-NEXT: v_add_u32_e64 v7, s[4:5], v7, v23 clamp
+; GFX8-NEXT: v_add_u32_e64 v8, s[4:5], v8, v24 clamp
+; GFX8-NEXT: v_add_u32_e64 v9, s[4:5], v9, v25 clamp
+; GFX8-NEXT: v_add_u32_e64 v10, s[4:5], v10, v26 clamp
+; GFX8-NEXT: v_add_u32_e64 v11, s[4:5], v11, v27 clamp
+; GFX8-NEXT: v_add_u32_e64 v12, s[4:5], v12, v28 clamp
+; GFX8-NEXT: v_add_u32_e64 v13, s[4:5], v13, v29 clamp
+; GFX8-NEXT: v_add_u32_e64 v14, s[4:5], v14, v30 clamp
+; GFX8-NEXT: v_add_u32_e64 v15, s[4:5], v15, v31 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uaddsat_v16i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_xor_b32_e32 v32, -1, v0
-; GFX9-NEXT: v_min_u32_e32 v16, v32, v16
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v1
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v17
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v2
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v18
-; GFX9-NEXT: v_add_u32_e32 v2, v2, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v3
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v19
-; GFX9-NEXT: v_add_u32_e32 v3, v3, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v4
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v20
-; GFX9-NEXT: v_add_u32_e32 v4, v4, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v5
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v21
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v6
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v22
-; GFX9-NEXT: v_add_u32_e32 v6, v6, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v7
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v23
-; GFX9-NEXT: v_add_u32_e32 v7, v7, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v8
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v24
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v9
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v25
-; GFX9-NEXT: v_add_u32_e32 v9, v9, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v10
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v26
-; GFX9-NEXT: v_add_u32_e32 v10, v10, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v11
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v27
-; GFX9-NEXT: v_add_u32_e32 v11, v11, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v12
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v28
-; GFX9-NEXT: v_add_u32_e32 v12, v12, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v13
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v29
-; GFX9-NEXT: v_add_u32_e32 v13, v13, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v14
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v30
-; GFX9-NEXT: v_add_u32_e32 v14, v14, v16
-; GFX9-NEXT: v_xor_b32_e32 v16, -1, v15
-; GFX9-NEXT: v_min_u32_e32 v16, v16, v31
-; GFX9-NEXT: v_add_u32_e32 v15, v15, v16
+; GFX9-NEXT: v_add_u32_e64 v0, v0, v16 clamp
+; GFX9-NEXT: v_add_u32_e64 v1, v1, v17 clamp
+; GFX9-NEXT: v_add_u32_e64 v2, v2, v18 clamp
+; GFX9-NEXT: v_add_u32_e64 v3, v3, v19 clamp
+; GFX9-NEXT: v_add_u32_e64 v4, v4, v20 clamp
+; GFX9-NEXT: v_add_u32_e64 v5, v5, v21 clamp
+; GFX9-NEXT: v_add_u32_e64 v6, v6, v22 clamp
+; GFX9-NEXT: v_add_u32_e64 v7, v7, v23 clamp
+; GFX9-NEXT: v_add_u32_e64 v8, v8, v24 clamp
+; GFX9-NEXT: v_add_u32_e64 v9, v9, v25 clamp
+; GFX9-NEXT: v_add_u32_e64 v10, v10, v26 clamp
+; GFX9-NEXT: v_add_u32_e64 v11, v11, v27 clamp
+; GFX9-NEXT: v_add_u32_e64 v12, v12, v28 clamp
+; GFX9-NEXT: v_add_u32_e64 v13, v13, v29 clamp
+; GFX9-NEXT: v_add_u32_e64 v14, v14, v30 clamp
+; GFX9-NEXT: v_add_u32_e64 v15, v15, v31 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uaddsat_v16i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v35, -1, v0
-; GFX10-NEXT: v_xor_b32_e32 v32, -1, v2
-; GFX10-NEXT: v_xor_b32_e32 v33, -1, v3
-; GFX10-NEXT: v_xor_b32_e32 v34, -1, v4
+; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, v16 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v1, v1, v17 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, v18 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v3, v3, v19 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v4, v4, v20 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v5, v5, v21 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v6, v6, v22 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v7, v7, v23 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v8, v8, v24 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v9, v9, v25 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v10, v10, v26 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v11, v11, v27 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v12, v12, v28 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v13, v13, v29 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v14, v14, v30 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v15, v15, v31 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u32_e32 v35, v35, v16
-; GFX10-NEXT: v_xor_b32_e32 v16, -1, v1
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v35
-; GFX10-NEXT: v_xor_b32_e32 v35, -1, v5
-; GFX10-NEXT: v_min_u32_e32 v16, v16, v17
-; GFX10-NEXT: v_min_u32_e32 v17, v32, v18
-; GFX10-NEXT: v_min_u32_e32 v18, v33, v19
-; GFX10-NEXT: v_min_u32_e32 v19, v34, v20
-; GFX10-NEXT: v_min_u32_e32 v20, v35, v21
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v16
-; GFX10-NEXT: v_xor_b32_e32 v16, -1, v6
-; GFX10-NEXT: v_add_nc_u32_e32 v2, v2, v17
-; GFX10-NEXT: v_xor_b32_e32 v17, -1, v7
-; GFX10-NEXT: v_add_nc_u32_e32 v3, v3, v18
-; GFX10-NEXT: v_xor_b32_e32 v18, -1, v8
-; GFX10-NEXT: v_add_nc_u32_e32 v4, v4, v19
-; GFX10-NEXT: v_xor_b32_e32 v19, -1, v9
-; GFX10-NEXT: v_add_nc_u32_e32 v5, v5, v20
-; GFX10-NEXT: v_xor_b32_e32 v20, -1, v10
-; GFX10-NEXT: v_min_u32_e32 v16, v16, v22
-; GFX10-NEXT: v_min_u32_e32 v17, v17, v23
-; GFX10-NEXT: v_min_u32_e32 v18, v18, v24
-; GFX10-NEXT: v_min_u32_e32 v19, v19, v25
-; GFX10-NEXT: v_min_u32_e32 v20, v20, v26
-; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v16
-; GFX10-NEXT: v_xor_b32_e32 v16, -1, v11
-; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v17
-; GFX10-NEXT: v_xor_b32_e32 v17, -1, v12
-; GFX10-NEXT: v_add_nc_u32_e32 v8, v8, v18
-; GFX10-NEXT: v_xor_b32_e32 v18, -1, v13
-; GFX10-NEXT: v_add_nc_u32_e32 v9, v9, v19
-; GFX10-NEXT: v_xor_b32_e32 v19, -1, v14
-; GFX10-NEXT: v_add_nc_u32_e32 v10, v10, v20
-; GFX10-NEXT: v_xor_b32_e32 v20, -1, v15
-; GFX10-NEXT: v_min_u32_e32 v16, v16, v27
-; GFX10-NEXT: v_min_u32_e32 v17, v17, v28
-; GFX10-NEXT: v_min_u32_e32 v18, v18, v29
-; GFX10-NEXT: v_min_u32_e32 v19, v19, v30
-; GFX10-NEXT: v_min_u32_e32 v20, v20, v31
-; GFX10-NEXT: v_add_nc_u32_e32 v11, v11, v16
-; GFX10-NEXT: v_add_nc_u32_e32 v12, v12, v17
-; GFX10-NEXT: v_add_nc_u32_e32 v13, v13, v18
-; GFX10-NEXT: v_add_nc_u32_e32 v14, v14, v19
-; GFX10-NEXT: v_add_nc_u32_e32 v15, v15, v20
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
@@ -1970,207 +1509,143 @@ define amdgpu_ps <16 x i32> @s_uaddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32>
;
; GFX8-LABEL: s_uaddsat_v16i32:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_not_b32 s32, s0
-; GFX8-NEXT: s_cmp_lt_u32 s32, s16
-; GFX8-NEXT: s_cselect_b32 s16, s32, s16
-; GFX8-NEXT: s_add_i32 s0, s0, s16
-; GFX8-NEXT: s_not_b32 s16, s1
-; GFX8-NEXT: s_cmp_lt_u32 s16, s17
-; GFX8-NEXT: s_cselect_b32 s16, s16, s17
-; GFX8-NEXT: s_add_i32 s1, s1, s16
-; GFX8-NEXT: s_not_b32 s16, s2
-; GFX8-NEXT: s_cmp_lt_u32 s16, s18
-; GFX8-NEXT: s_cselect_b32 s16, s16, s18
-; GFX8-NEXT: s_add_i32 s2, s2, s16
-; GFX8-NEXT: s_not_b32 s16, s3
-; GFX8-NEXT: s_cmp_lt_u32 s16, s19
-; GFX8-NEXT: s_cselect_b32 s16, s16, s19
-; GFX8-NEXT: s_add_i32 s3, s3, s16
-; GFX8-NEXT: s_not_b32 s16, s4
-; GFX8-NEXT: s_cmp_lt_u32 s16, s20
-; GFX8-NEXT: s_cselect_b32 s16, s16, s20
-; GFX8-NEXT: s_add_i32 s4, s4, s16
-; GFX8-NEXT: s_not_b32 s16, s5
-; GFX8-NEXT: s_cmp_lt_u32 s16, s21
-; GFX8-NEXT: s_cselect_b32 s16, s16, s21
-; GFX8-NEXT: s_add_i32 s5, s5, s16
-; GFX8-NEXT: s_not_b32 s16, s6
-; GFX8-NEXT: s_cmp_lt_u32 s16, s22
-; GFX8-NEXT: s_cselect_b32 s16, s16, s22
-; GFX8-NEXT: s_add_i32 s6, s6, s16
-; GFX8-NEXT: s_not_b32 s16, s7
-; GFX8-NEXT: s_cmp_lt_u32 s16, s23
-; GFX8-NEXT: s_cselect_b32 s16, s16, s23
-; GFX8-NEXT: s_add_i32 s7, s7, s16
-; GFX8-NEXT: s_not_b32 s16, s8
-; GFX8-NEXT: s_cmp_lt_u32 s16, s24
-; GFX8-NEXT: s_cselect_b32 s16, s16, s24
-; GFX8-NEXT: s_add_i32 s8, s8, s16
-; GFX8-NEXT: s_not_b32 s16, s9
-; GFX8-NEXT: s_cmp_lt_u32 s16, s25
-; GFX8-NEXT: s_cselect_b32 s16, s16, s25
-; GFX8-NEXT: s_add_i32 s9, s9, s16
-; GFX8-NEXT: s_not_b32 s16, s10
-; GFX8-NEXT: s_cmp_lt_u32 s16, s26
-; GFX8-NEXT: s_cselect_b32 s16, s16, s26
-; GFX8-NEXT: s_add_i32 s10, s10, s16
-; GFX8-NEXT: s_not_b32 s16, s11
-; GFX8-NEXT: s_cmp_lt_u32 s16, s27
-; GFX8-NEXT: s_cselect_b32 s16, s16, s27
-; GFX8-NEXT: s_add_i32 s11, s11, s16
-; GFX8-NEXT: s_not_b32 s16, s12
-; GFX8-NEXT: s_cmp_lt_u32 s16, s28
-; GFX8-NEXT: s_cselect_b32 s16, s16, s28
-; GFX8-NEXT: s_add_i32 s12, s12, s16
-; GFX8-NEXT: s_not_b32 s16, s13
-; GFX8-NEXT: s_cmp_lt_u32 s16, s29
-; GFX8-NEXT: s_cselect_b32 s16, s16, s29
-; GFX8-NEXT: s_add_i32 s13, s13, s16
-; GFX8-NEXT: s_not_b32 s16, s14
-; GFX8-NEXT: s_cmp_lt_u32 s16, s30
-; GFX8-NEXT: s_cselect_b32 s16, s16, s30
-; GFX8-NEXT: s_add_i32 s14, s14, s16
-; GFX8-NEXT: s_not_b32 s16, s15
-; GFX8-NEXT: s_cmp_lt_u32 s16, s31
-; GFX8-NEXT: s_cselect_b32 s16, s16, s31
-; GFX8-NEXT: s_add_i32 s15, s15, s16
+; GFX8-NEXT: v_mov_b32_e32 v0, s16
+; GFX8-NEXT: v_mov_b32_e32 v1, s17
+; GFX8-NEXT: v_mov_b32_e32 v2, s18
+; GFX8-NEXT: v_mov_b32_e32 v3, s19
+; GFX8-NEXT: v_mov_b32_e32 v4, s20
+; GFX8-NEXT: v_mov_b32_e32 v5, s21
+; GFX8-NEXT: v_mov_b32_e32 v6, s22
+; GFX8-NEXT: v_mov_b32_e32 v7, s23
+; GFX8-NEXT: v_mov_b32_e32 v8, s24
+; GFX8-NEXT: v_mov_b32_e32 v9, s25
+; GFX8-NEXT: v_mov_b32_e32 v10, s26
+; GFX8-NEXT: v_mov_b32_e32 v11, s27
+; GFX8-NEXT: v_mov_b32_e32 v12, s28
+; GFX8-NEXT: v_mov_b32_e32 v13, s29
+; GFX8-NEXT: v_mov_b32_e32 v14, s30
+; GFX8-NEXT: v_mov_b32_e32 v15, s31
+; GFX8-NEXT: v_add_u32_e64 v0, s[32:33], s0, v0 clamp
+; GFX8-NEXT: v_add_u32_e64 v1, s[16:17], s1, v1 clamp
+; GFX8-NEXT: v_add_u32_e64 v2, s[16:17], s2, v2 clamp
+; GFX8-NEXT: v_add_u32_e64 v3, s[2:3], s3, v3 clamp
+; GFX8-NEXT: v_add_u32_e64 v4, s[2:3], s4, v4 clamp
+; GFX8-NEXT: v_add_u32_e64 v5, s[2:3], s5, v5 clamp
+; GFX8-NEXT: v_add_u32_e64 v6, s[2:3], s6, v6 clamp
+; GFX8-NEXT: v_add_u32_e64 v7, s[2:3], s7, v7 clamp
+; GFX8-NEXT: v_add_u32_e64 v8, s[2:3], s8, v8 clamp
+; GFX8-NEXT: v_add_u32_e64 v9, s[2:3], s9, v9 clamp
+; GFX8-NEXT: v_add_u32_e64 v10, s[2:3], s10, v10 clamp
+; GFX8-NEXT: v_add_u32_e64 v11, s[2:3], s11, v11 clamp
+; GFX8-NEXT: v_add_u32_e64 v12, s[2:3], s12, v12 clamp
+; GFX8-NEXT: v_add_u32_e64 v13, s[2:3], s13, v13 clamp
+; GFX8-NEXT: v_add_u32_e64 v14, s[2:3], s14, v14 clamp
+; GFX8-NEXT: v_add_u32_e64 v15, s[2:3], s15, v15 clamp
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
+; GFX8-NEXT: v_readfirstlane_b32 s3, v3
+; GFX8-NEXT: v_readfirstlane_b32 s4, v4
+; GFX8-NEXT: v_readfirstlane_b32 s5, v5
+; GFX8-NEXT: v_readfirstlane_b32 s6, v6
+; GFX8-NEXT: v_readfirstlane_b32 s7, v7
+; GFX8-NEXT: v_readfirstlane_b32 s8, v8
+; GFX8-NEXT: v_readfirstlane_b32 s9, v9
+; GFX8-NEXT: v_readfirstlane_b32 s10, v10
+; GFX8-NEXT: v_readfirstlane_b32 s11, v11
+; GFX8-NEXT: v_readfirstlane_b32 s12, v12
+; GFX8-NEXT: v_readfirstlane_b32 s13, v13
+; GFX8-NEXT: v_readfirstlane_b32 s14, v14
+; GFX8-NEXT: v_readfirstlane_b32 s15, v15
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_v16i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_not_b32 s32, s0
-; GFX9-NEXT: s_cmp_lt_u32 s32, s16
-; GFX9-NEXT: s_cselect_b32 s16, s32, s16
-; GFX9-NEXT: s_add_i32 s0, s0, s16
-; GFX9-NEXT: s_not_b32 s16, s1
-; GFX9-NEXT: s_cmp_lt_u32 s16, s17
-; GFX9-NEXT: s_cselect_b32 s16, s16, s17
-; GFX9-NEXT: s_add_i32 s1, s1, s16
-; GFX9-NEXT: s_not_b32 s16, s2
-; GFX9-NEXT: s_cmp_lt_u32 s16, s18
-; GFX9-NEXT: s_cselect_b32 s16, s16, s18
-; GFX9-NEXT: s_add_i32 s2, s2, s16
-; GFX9-NEXT: s_not_b32 s16, s3
-; GFX9-NEXT: s_cmp_lt_u32 s16, s19
-; GFX9-NEXT: s_cselect_b32 s16, s16, s19
-; GFX9-NEXT: s_add_i32 s3, s3, s16
-; GFX9-NEXT: s_not_b32 s16, s4
-; GFX9-NEXT: s_cmp_lt_u32 s16, s20
-; GFX9-NEXT: s_cselect_b32 s16, s16, s20
-; GFX9-NEXT: s_add_i32 s4, s4, s16
-; GFX9-NEXT: s_not_b32 s16, s5
-; GFX9-NEXT: s_cmp_lt_u32 s16, s21
-; GFX9-NEXT: s_cselect_b32 s16, s16, s21
-; GFX9-NEXT: s_add_i32 s5, s5, s16
-; GFX9-NEXT: s_not_b32 s16, s6
-; GFX9-NEXT: s_cmp_lt_u32 s16, s22
-; GFX9-NEXT: s_cselect_b32 s16, s16, s22
-; GFX9-NEXT: s_add_i32 s6, s6, s16
-; GFX9-NEXT: s_not_b32 s16, s7
-; GFX9-NEXT: s_cmp_lt_u32 s16, s23
-; GFX9-NEXT: s_cselect_b32 s16, s16, s23
-; GFX9-NEXT: s_add_i32 s7, s7, s16
-; GFX9-NEXT: s_not_b32 s16, s8
-; GFX9-NEXT: s_cmp_lt_u32 s16, s24
-; GFX9-NEXT: s_cselect_b32 s16, s16, s24
-; GFX9-NEXT: s_add_i32 s8, s8, s16
-; GFX9-NEXT: s_not_b32 s16, s9
-; GFX9-NEXT: s_cmp_lt_u32 s16, s25
-; GFX9-NEXT: s_cselect_b32 s16, s16, s25
-; GFX9-NEXT: s_add_i32 s9, s9, s16
-; GFX9-NEXT: s_not_b32 s16, s10
-; GFX9-NEXT: s_cmp_lt_u32 s16, s26
-; GFX9-NEXT: s_cselect_b32 s16, s16, s26
-; GFX9-NEXT: s_add_i32 s10, s10, s16
-; GFX9-NEXT: s_not_b32 s16, s11
-; GFX9-NEXT: s_cmp_lt_u32 s16, s27
-; GFX9-NEXT: s_cselect_b32 s16, s16, s27
-; GFX9-NEXT: s_add_i32 s11, s11, s16
-; GFX9-NEXT: s_not_b32 s16, s12
-; GFX9-NEXT: s_cmp_lt_u32 s16, s28
-; GFX9-NEXT: s_cselect_b32 s16, s16, s28
-; GFX9-NEXT: s_add_i32 s12, s12, s16
-; GFX9-NEXT: s_not_b32 s16, s13
-; GFX9-NEXT: s_cmp_lt_u32 s16, s29
-; GFX9-NEXT: s_cselect_b32 s16, s16, s29
-; GFX9-NEXT: s_add_i32 s13, s13, s16
-; GFX9-NEXT: s_not_b32 s16, s14
-; GFX9-NEXT: s_cmp_lt_u32 s16, s30
-; GFX9-NEXT: s_cselect_b32 s16, s16, s30
-; GFX9-NEXT: s_add_i32 s14, s14, s16
-; GFX9-NEXT: s_not_b32 s16, s15
-; GFX9-NEXT: s_cmp_lt_u32 s16, s31
-; GFX9-NEXT: s_cselect_b32 s16, s16, s31
-; GFX9-NEXT: s_add_i32 s15, s15, s16
+; GFX9-NEXT: v_mov_b32_e32 v0, s16
+; GFX9-NEXT: v_mov_b32_e32 v1, s17
+; GFX9-NEXT: v_mov_b32_e32 v2, s18
+; GFX9-NEXT: v_mov_b32_e32 v3, s19
+; GFX9-NEXT: v_mov_b32_e32 v4, s20
+; GFX9-NEXT: v_mov_b32_e32 v5, s21
+; GFX9-NEXT: v_mov_b32_e32 v6, s22
+; GFX9-NEXT: v_mov_b32_e32 v7, s23
+; GFX9-NEXT: v_mov_b32_e32 v8, s24
+; GFX9-NEXT: v_mov_b32_e32 v9, s25
+; GFX9-NEXT: v_mov_b32_e32 v10, s26
+; GFX9-NEXT: v_mov_b32_e32 v11, s27
+; GFX9-NEXT: v_mov_b32_e32 v12, s28
+; GFX9-NEXT: v_mov_b32_e32 v13, s29
+; GFX9-NEXT: v_mov_b32_e32 v14, s30
+; GFX9-NEXT: v_mov_b32_e32 v15, s31
+; GFX9-NEXT: v_add_u32_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_add_u32_e64 v1, s1, v1 clamp
+; GFX9-NEXT: v_add_u32_e64 v2, s2, v2 clamp
+; GFX9-NEXT: v_add_u32_e64 v3, s3, v3 clamp
+; GFX9-NEXT: v_add_u32_e64 v4, s4, v4 clamp
+; GFX9-NEXT: v_add_u32_e64 v5, s5, v5 clamp
+; GFX9-NEXT: v_add_u32_e64 v6, s6, v6 clamp
+; GFX9-NEXT: v_add_u32_e64 v7, s7, v7 clamp
+; GFX9-NEXT: v_add_u32_e64 v8, s8, v8 clamp
+; GFX9-NEXT: v_add_u32_e64 v9, s9, v9 clamp
+; GFX9-NEXT: v_add_u32_e64 v10, s10, v10 clamp
+; GFX9-NEXT: v_add_u32_e64 v11, s11, v11 clamp
+; GFX9-NEXT: v_add_u32_e64 v12, s12, v12 clamp
+; GFX9-NEXT: v_add_u32_e64 v13, s13, v13 clamp
+; GFX9-NEXT: v_add_u32_e64 v14, s14, v14 clamp
+; GFX9-NEXT: v_add_u32_e64 v15, s15, v15 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
+; GFX9-NEXT: v_readfirstlane_b32 s4, v4
+; GFX9-NEXT: v_readfirstlane_b32 s5, v5
+; GFX9-NEXT: v_readfirstlane_b32 s6, v6
+; GFX9-NEXT: v_readfirstlane_b32 s7, v7
+; GFX9-NEXT: v_readfirstlane_b32 s8, v8
+; GFX9-NEXT: v_readfirstlane_b32 s9, v9
+; GFX9-NEXT: v_readfirstlane_b32 s10, v10
+; GFX9-NEXT: v_readfirstlane_b32 s11, v11
+; GFX9-NEXT: v_readfirstlane_b32 s12, v12
+; GFX9-NEXT: v_readfirstlane_b32 s13, v13
+; GFX9-NEXT: v_readfirstlane_b32 s14, v14
+; GFX9-NEXT: v_readfirstlane_b32 s15, v15
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_v16i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_not_b32 s46, s0
+; GFX10-NEXT: v_add_nc_u32_e64 v0, s0, s16 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v1, s1, s17 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v2, s2, s18 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v3, s3, s19 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v4, s4, s20 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v5, s5, s21 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v6, s6, s22 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v7, s7, s23 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v8, s8, s24 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v9, s9, s25 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v10, s10, s26 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v11, s11, s27 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v12, s12, s28 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v13, s13, s29 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v14, s14, s30 clamp
+; GFX10-NEXT: v_add_nc_u32_e64 v15, s15, s31 clamp
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10-NEXT: v_readfirstlane_b32 s8, v8
+; GFX10-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10-NEXT: v_readfirstlane_b32 s10, v10
+; GFX10-NEXT: v_readfirstlane_b32 s11, v11
+; GFX10-NEXT: v_readfirstlane_b32 s12, v12
+; GFX10-NEXT: v_readfirstlane_b32 s13, v13
+; GFX10-NEXT: v_readfirstlane_b32 s14, v14
+; GFX10-NEXT: v_readfirstlane_b32 s15, v15
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cmp_lt_u32 s46, s16
-; GFX10-NEXT: s_cselect_b32 s46, s46, s16
-; GFX10-NEXT: s_not_b32 s47, s1
-; GFX10-NEXT: s_add_i32 s0, s0, s46
-; GFX10-NEXT: s_cmp_lt_u32 s47, s17
-; GFX10-NEXT: s_cselect_b32 s46, s47, s17
-; GFX10-NEXT: s_not_b32 s17, s2
-; GFX10-NEXT: s_add_i32 s1, s1, s46
-; GFX10-NEXT: s_cmp_lt_u32 s17, s18
-; GFX10-NEXT: s_cselect_b32 s16, s17, s18
-; GFX10-NEXT: s_not_b32 s17, s3
-; GFX10-NEXT: s_add_i32 s2, s2, s16
-; GFX10-NEXT: s_cmp_lt_u32 s17, s19
-; GFX10-NEXT: s_cselect_b32 s16, s17, s19
-; GFX10-NEXT: s_not_b32 s17, s4
-; GFX10-NEXT: s_add_i32 s3, s3, s16
-; GFX10-NEXT: s_cmp_lt_u32 s17, s20
-; GFX10-NEXT: s_cselect_b32 s16, s17, s20
-; GFX10-NEXT: s_not_b32 s17, s5
-; GFX10-NEXT: s_add_i32 s4, s4, s16
-; GFX10-NEXT: s_cmp_lt_u32 s17, s21
-; GFX10-NEXT: s_cselect_b32 s16, s17, s21
-; GFX10-NEXT: s_not_b32 s17, s6
-; GFX10-NEXT: s_add_i32 s5, s5, s16
-; GFX10-NEXT: s_cmp_lt_u32 s17, s22
-; GFX10-NEXT: s_cselect_b32 s16, s17, s22
-; GFX10-NEXT: s_not_b32 s17, s7
-; GFX10-NEXT: s_add_i32 s6, s6, s16
-; GFX10-NEXT: s_cmp_lt_u32 s17, s23
-; GFX10-NEXT: s_cselect_b32 s16, s17, s23
-; GFX10-NEXT: s_not_b32 s17, s8
-; GFX10-NEXT: s_add_i32 s7, s7, s16
-; GFX10-NEXT: s_cmp_lt_u32 s17, s24
-; GFX10-NEXT: s_cselect_b32 s16, s17, s24
-; GFX10-NEXT: s_not_b32 s17, s9
-; GFX10-NEXT: s_add_i32 s8, s8, s16
-; GFX10-NEXT: s_cmp_lt_u32 s17, s25
-; GFX10-NEXT: s_cselect_b32 s16, s17, s25
-; GFX10-NEXT: s_not_b32 s17, s10
-; GFX10-NEXT: s_add_i32 s9, s9, s16
-; GFX10-NEXT: s_cmp_lt_u32 s17, s26
-; GFX10-NEXT: s_cselect_b32 s16, s17, s26
-; GFX10-NEXT: s_not_b32 s17, s11
-; GFX10-NEXT: s_add_i32 s10, s10, s16
-; GFX10-NEXT: s_cmp_lt_u32 s17, s27
-; GFX10-NEXT: s_cselect_b32 s16, s17, s27
-; GFX10-NEXT: s_not_b32 s17, s12
-; GFX10-NEXT: s_add_i32 s11, s11, s16
-; GFX10-NEXT: s_cmp_lt_u32 s17, s28
-; GFX10-NEXT: s_cselect_b32 s16, s17, s28
-; GFX10-NEXT: s_not_b32 s17, s13
-; GFX10-NEXT: s_add_i32 s12, s12, s16
-; GFX10-NEXT: s_cmp_lt_u32 s17, s29
-; GFX10-NEXT: s_cselect_b32 s16, s17, s29
-; GFX10-NEXT: s_not_b32 s17, s14
-; GFX10-NEXT: s_add_i32 s13, s13, s16
-; GFX10-NEXT: s_cmp_lt_u32 s17, s30
-; GFX10-NEXT: s_cselect_b32 s16, s17, s30
-; GFX10-NEXT: s_not_b32 s17, s15
-; GFX10-NEXT: s_add_i32 s14, s14, s16
-; GFX10-NEXT: s_cmp_lt_u32 s17, s31
-; GFX10-NEXT: s_cselect_b32 s16, s17, s31
-; GFX10-NEXT: s_add_i32 s15, s15, s16
; GFX10-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
@@ -2191,27 +1666,21 @@ define i16 @v_uaddsat_i16(i16 %lhs, i16 %rhs) {
; GFX8-LABEL: v_uaddsat_i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX8-NEXT: v_min_u16_e32 v1, v2, v1
-; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uaddsat_i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX9-NEXT: v_min_u16_e32 v1, v2, v1
-; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e64 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uaddsat_i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v2, -1, v0
+; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u16_e64 v1, v2, v1
-; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
@@ -2231,33 +1700,23 @@ define amdgpu_ps i16 @s_uaddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
;
; GFX8-LABEL: s_uaddsat_i16:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_xor_b32 s2, s0, -1
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s2, s1
-; GFX8-NEXT: s_cselect_b32 s1, s2, s1
-; GFX8-NEXT: s_add_i32 s0, s0, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_xor_b32 s2, s0, -1
-; GFX9-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s2, s1
-; GFX9-NEXT: s_cselect_b32 s1, s2, s1
-; GFX9-NEXT: s_add_i32 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_add_u16_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_xor_b32 s2, s0, -1
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: s_bfe_u32 s2, s2, 0x100000
+; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cmp_lt_u32 s2, s1
-; GFX10-NEXT: s_cselect_b32 s1, s2, s1
-; GFX10-NEXT: s_add_i32 s0, s0, s1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
@@ -2276,24 +1735,18 @@ define amdgpu_ps half @uaddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
;
; GFX8-LABEL: uaddsat_i16_sv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_xor_b32 s1, s0, -1
-; GFX8-NEXT: v_min_u16_e32 v0, s1, v0
-; GFX8-NEXT: v_add_u16_e32 v0, s0, v0
+; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: uaddsat_i16_sv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_xor_b32 s1, s0, -1
-; GFX9-NEXT: v_min_u16_e32 v0, s1, v0
-; GFX9-NEXT: v_add_u16_e32 v0, s0, v0
+; GFX9-NEXT: v_add_u16_e64 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: uaddsat_i16_sv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_xor_b32 s1, s0, -1
+; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, v0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u16_e64 v0, s1, v0
-; GFX10-NEXT: v_add_nc_u16_e64 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
@@ -2313,24 +1766,18 @@ define amdgpu_ps half @uaddsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
;
; GFX8-LABEL: uaddsat_i16_vs:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_xor_b32_e32 v1, -1, v0
-; GFX8-NEXT: v_min_u16_e32 v1, s0, v1
-; GFX8-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_add_u16_e64 v0, v0, s0 clamp
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: uaddsat_i16_vs:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_xor_b32_e32 v1, -1, v0
-; GFX9-NEXT: v_min_u16_e32 v1, s0, v1
-; GFX9-NEXT: v_add_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_add_u16_e64 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: uaddsat_i16_vs:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_xor_b32_e32 v1, -1, v0
+; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, s0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u16_e64 v1, v1, s0
-; GFX10-NEXT: v_add_nc_u16_e64 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
@@ -2358,32 +1805,25 @@ define <2 x i16> @v_uaddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX8-LABEL: v_uaddsat_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX8-NEXT: v_xor_b32_e32 v3, -1, v0
-; GFX8-NEXT: v_xor_b32_e32 v4, -1, v2
-; GFX8-NEXT: v_min_u16_e32 v3, v3, v1
-; GFX8-NEXT: v_min_u16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_add_u16_e32 v0, v0, v3
-; GFX8-NEXT: v_add_u16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_add_u16_e64 v2, v0, v1 clamp
+; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v1, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uaddsat_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_xor_b32_e32 v2, -1, v0
-; GFX9-NEXT: v_pk_min_u16 v1, v2, v1
-; GFX9-NEXT: v_pk_add_u16 v0, v0, v1
+; GFX9-NEXT: v_pk_add_u16 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uaddsat_v2i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v2, -1, v0
+; GFX10-NEXT: v_pk_add_u16 v0, v0, v1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_min_u16 v1, v2, v1
-; GFX10-NEXT: v_pk_add_u16 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result
@@ -2415,65 +1855,30 @@ define amdgpu_ps i32 @s_uaddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs
;
; GFX8-LABEL: s_uaddsat_v2i16:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_xor_b32 s4, s0, -1
; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s4, s1
-; GFX8-NEXT: s_cselect_b32 s1, s4, s1
-; GFX8-NEXT: s_add_i32 s0, s0, s1
-; GFX8-NEXT: s_xor_b32 s1, s2, -1
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s1, s3
-; GFX8-NEXT: s_cselect_b32 s1, s1, s3
-; GFX8-NEXT: s_add_i32 s2, s2, s1
-; GFX8-NEXT: s_bfe_u32 s1, s2, 0x100000
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_lshl_b32 s1, s1, 16
-; GFX8-NEXT: s_or_b32 s0, s0, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_add_u16_e64 v1, s2, v1 clamp
+; GFX8-NEXT: v_mov_b32_e32 v2, 16
+; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_v2i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_xor_b32 s2, s0, -1
-; GFX9-NEXT: s_mov_b32 s4, 0xffff
-; GFX9-NEXT: s_lshr_b32 s3, s2, 16
-; GFX9-NEXT: s_lshr_b32 s5, s1, 16
-; GFX9-NEXT: s_and_b32 s2, s2, s4
-; GFX9-NEXT: s_and_b32 s1, s1, s4
-; GFX9-NEXT: s_cmp_lt_u32 s2, s1
-; GFX9-NEXT: s_cselect_b32 s1, s2, s1
-; GFX9-NEXT: s_cmp_lt_u32 s3, s5
-; GFX9-NEXT: s_cselect_b32 s2, s3, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2
-; GFX9-NEXT: s_lshr_b32 s2, s0, 16
-; GFX9-NEXT: s_lshr_b32 s3, s1, 16
-; GFX9-NEXT: s_add_i32 s0, s0, s1
-; GFX9-NEXT: s_add_i32 s2, s2, s3
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_v2i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_xor_b32 s2, s0, -1
-; GFX10-NEXT: s_mov_b32 s3, 0xffff
-; GFX10-NEXT: s_lshr_b32 s4, s2, 16
-; GFX10-NEXT: s_and_b32 s2, s2, s3
-; GFX10-NEXT: s_and_b32 s3, s1, s3
-; GFX10-NEXT: s_lshr_b32 s1, s1, 16
-; GFX10-NEXT: s_cmp_lt_u32 s2, s3
+; GFX10-NEXT: v_pk_add_u16 v0, s0, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s2, s2, s3
-; GFX10-NEXT: s_cmp_lt_u32 s4, s1
-; GFX10-NEXT: s_cselect_b32 s1, s4, s1
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s2, s1
-; GFX10-NEXT: s_lshr_b32 s2, s0, 16
-; GFX10-NEXT: s_lshr_b32 s3, s1, 16
-; GFX10-NEXT: s_add_i32 s0, s0, s1
-; GFX10-NEXT: s_add_i32 s2, s2, s3
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to i32
@@ -2504,31 +1909,24 @@ define amdgpu_ps float @uaddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
;
; GFX8-LABEL: uaddsat_v2i16_sv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_xor_b32 s2, s0, -1
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
-; GFX8-NEXT: v_min_u16_e32 v1, s2, v0
-; GFX8-NEXT: s_xor_b32 s2, s1, -1
-; GFX8-NEXT: v_mov_b32_e32 v2, s2
-; GFX8-NEXT: v_min_u16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_mov_b32_e32 v2, s1
-; GFX8-NEXT: v_add_u16_e32 v1, s0, v1
-; GFX8-NEXT: v_add_u16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_add_u16_e64 v1, s0, v0 clamp
+; GFX8-NEXT: v_add_u16_sdwa v0, v2, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v2, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: uaddsat_v2i16_sv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_xor_b32 s1, s0, -1
-; GFX9-NEXT: v_pk_min_u16 v0, s1, v0
-; GFX9-NEXT: v_pk_add_u16 v0, s0, v0
+; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: uaddsat_v2i16_sv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_xor_b32 s1, s0, -1
+; GFX10-NEXT: v_pk_add_u16 v0, s0, v0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_min_u16 v0, s1, v0
-; GFX10-NEXT: v_pk_add_u16 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
@@ -2559,30 +1957,24 @@ define amdgpu_ps float @uaddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
;
; GFX8-LABEL: uaddsat_v2i16_vs:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX8-NEXT: v_xor_b32_e32 v2, -1, v0
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
-; GFX8-NEXT: v_xor_b32_e32 v3, -1, v1
-; GFX8-NEXT: v_min_u16_e32 v2, s0, v2
-; GFX8-NEXT: v_min_u16_e32 v3, s1, v3
-; GFX8-NEXT: v_add_u16_e32 v0, v0, v2
-; GFX8-NEXT: v_add_u16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: v_add_u16_e64 v1, v0, s0 clamp
+; GFX8-NEXT: v_add_u16_sdwa v0, v0, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v2, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: uaddsat_v2i16_vs:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_xor_b32_e32 v1, -1, v0
-; GFX9-NEXT: v_pk_min_u16 v1, v1, s0
-; GFX9-NEXT: v_pk_add_u16 v0, v0, v1
+; GFX9-NEXT: v_pk_add_u16 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: uaddsat_v2i16_vs:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_xor_b32_e32 v1, -1, v0
+; GFX10-NEXT: v_pk_add_u16 v0, v0, s0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_min_u16 v1, v1, s0
-; GFX10-NEXT: v_pk_add_u16 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
@@ -2642,46 +2034,31 @@ define <2 x float> @v_uaddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX8-LABEL: v_uaddsat_v4i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX8-NEXT: v_xor_b32_e32 v6, -1, v0
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX8-NEXT: v_xor_b32_e32 v7, -1, v4
-; GFX8-NEXT: v_min_u16_e32 v6, v6, v2
-; GFX8-NEXT: v_min_u16_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_xor_b32_e32 v7, -1, v1
-; GFX8-NEXT: v_xor_b32_e32 v8, -1, v5
-; GFX8-NEXT: v_min_u16_e32 v7, v7, v3
-; GFX8-NEXT: v_min_u16_sdwa v3, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_add_u16_e32 v0, v0, v6
-; GFX8-NEXT: v_add_u16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_add_u16_e32 v1, v1, v7
-; GFX8-NEXT: v_add_u16_sdwa v2, v5, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_add_u16_e64 v4, v0, v2 clamp
+; GFX8-NEXT: v_add_u16_sdwa v0, v0, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_add_u16_e64 v2, v1, v3 clamp
+; GFX8-NEXT: v_add_u16_sdwa v1, v1, v3 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v3, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uaddsat_v4i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_xor_b32_e32 v4, -1, v0
-; GFX9-NEXT: v_pk_min_u16 v2, v4, v2
-; GFX9-NEXT: v_pk_add_u16 v0, v0, v2
-; GFX9-NEXT: v_xor_b32_e32 v2, -1, v1
-; GFX9-NEXT: v_pk_min_u16 v2, v2, v3
-; GFX9-NEXT: v_pk_add_u16 v1, v1, v2
+; GFX9-NEXT: v_pk_add_u16 v0, v0, v2 clamp
+; GFX9-NEXT: v_pk_add_u16 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uaddsat_v4i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v4, -1, v0
-; GFX10-NEXT: v_xor_b32_e32 v5, -1, v1
+; GFX10-NEXT: v_pk_add_u16 v0, v0, v2 clamp
+; GFX10-NEXT: v_pk_add_u16 v1, v1, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_min_u16 v2, v4, v2
-; GFX10-NEXT: v_pk_min_u16 v3, v5, v3
-; GFX10-NEXT: v_pk_add_u16 v0, v0, v2
-; GFX10-NEXT: v_pk_add_u16 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x float>
@@ -2732,113 +2109,44 @@ define amdgpu_ps <2 x i32> @s_uaddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inre
;
; GFX8-LABEL: s_uaddsat_v4i16:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_xor_b32 s8, s0, -1
; GFX8-NEXT: s_lshr_b32 s6, s2, 16
+; GFX8-NEXT: s_lshr_b32 s7, s3, 16
; GFX8-NEXT: s_lshr_b32 s4, s0, 16
+; GFX8-NEXT: v_mov_b32_e32 v1, s6
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: s_lshr_b32 s5, s1, 16
-; GFX8-NEXT: s_lshr_b32 s7, s3, 16
-; GFX8-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s8, s2
-; GFX8-NEXT: s_cselect_b32 s2, s8, s2
-; GFX8-NEXT: s_add_i32 s0, s0, s2
-; GFX8-NEXT: s_xor_b32 s2, s4, -1
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s2, s6
-; GFX8-NEXT: s_cselect_b32 s2, s2, s6
-; GFX8-NEXT: s_add_i32 s4, s4, s2
-; GFX8-NEXT: s_xor_b32 s2, s1, -1
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s2, s3
-; GFX8-NEXT: s_cselect_b32 s2, s2, s3
-; GFX8-NEXT: s_add_i32 s1, s1, s2
-; GFX8-NEXT: s_xor_b32 s2, s5, -1
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_bfe_u32 s3, s7, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s2, s3
-; GFX8-NEXT: s_cselect_b32 s2, s2, s3
-; GFX8-NEXT: s_add_i32 s5, s5, s2
-; GFX8-NEXT: s_bfe_u32 s2, s4, 0x100000
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_lshl_b32 s2, s2, 16
-; GFX8-NEXT: s_or_b32 s0, s0, s2
-; GFX8-NEXT: s_bfe_u32 s2, s5, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_lshl_b32 s2, s2, 16
-; GFX8-NEXT: s_or_b32 s1, s1, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_add_u16_e64 v1, s4, v1 clamp
+; GFX8-NEXT: v_mov_b32_e32 v4, 16
+; GFX8-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_add_u16_e64 v3, s5, v3 clamp
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_add_u16_e64 v2, s1, v2 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_v4i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_xor_b32 s4, s0, -1
-; GFX9-NEXT: s_mov_b32 s6, 0xffff
-; GFX9-NEXT: s_lshr_b32 s5, s4, 16
-; GFX9-NEXT: s_lshr_b32 s7, s2, 16
-; GFX9-NEXT: s_and_b32 s4, s4, s6
-; GFX9-NEXT: s_and_b32 s2, s2, s6
-; GFX9-NEXT: s_cmp_lt_u32 s4, s2
-; GFX9-NEXT: s_cselect_b32 s2, s4, s2
-; GFX9-NEXT: s_cmp_lt_u32 s5, s7
-; GFX9-NEXT: s_cselect_b32 s4, s5, s7
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4
-; GFX9-NEXT: s_lshr_b32 s4, s0, 16
-; GFX9-NEXT: s_lshr_b32 s5, s2, 16
-; GFX9-NEXT: s_add_i32 s0, s0, s2
-; GFX9-NEXT: s_add_i32 s4, s4, s5
-; GFX9-NEXT: s_xor_b32 s2, s1, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4
-; GFX9-NEXT: s_lshr_b32 s4, s2, 16
-; GFX9-NEXT: s_lshr_b32 s5, s3, 16
-; GFX9-NEXT: s_and_b32 s2, s2, s6
-; GFX9-NEXT: s_and_b32 s3, s3, s6
-; GFX9-NEXT: s_cmp_lt_u32 s2, s3
-; GFX9-NEXT: s_cselect_b32 s2, s2, s3
-; GFX9-NEXT: s_cmp_lt_u32 s4, s5
-; GFX9-NEXT: s_cselect_b32 s3, s4, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3
-; GFX9-NEXT: s_lshr_b32 s3, s1, 16
-; GFX9-NEXT: s_lshr_b32 s4, s2, 16
-; GFX9-NEXT: s_add_i32 s1, s1, s2
-; GFX9-NEXT: s_add_i32 s3, s3, s4
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp
+; GFX9-NEXT: v_pk_add_u16 v1, s1, v1 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_v4i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_xor_b32 s4, s0, -1
-; GFX10-NEXT: s_mov_b32 s5, 0xffff
-; GFX10-NEXT: s_lshr_b32 s6, s4, 16
-; GFX10-NEXT: s_and_b32 s7, s2, s5
-; GFX10-NEXT: s_and_b32 s4, s4, s5
-; GFX10-NEXT: s_lshr_b32 s2, s2, 16
-; GFX10-NEXT: s_cmp_lt_u32 s4, s7
+; GFX10-NEXT: v_pk_add_u16 v0, s0, s2 clamp
+; GFX10-NEXT: v_pk_add_u16 v1, s1, s3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s4, s4, s7
-; GFX10-NEXT: s_cmp_lt_u32 s6, s2
-; GFX10-NEXT: s_cselect_b32 s2, s6, s2
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s4, s2
-; GFX10-NEXT: s_lshr_b32 s4, s0, 16
-; GFX10-NEXT: s_lshr_b32 s6, s2, 16
-; GFX10-NEXT: s_add_i32 s0, s0, s2
-; GFX10-NEXT: s_xor_b32 s2, s1, -1
-; GFX10-NEXT: s_add_i32 s4, s4, s6
-; GFX10-NEXT: s_lshr_b32 s6, s2, 16
-; GFX10-NEXT: s_and_b32 s2, s2, s5
-; GFX10-NEXT: s_and_b32 s5, s3, s5
-; GFX10-NEXT: s_lshr_b32 s3, s3, 16
-; GFX10-NEXT: s_cmp_lt_u32 s2, s5
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4
-; GFX10-NEXT: s_cselect_b32 s2, s2, s5
-; GFX10-NEXT: s_cmp_lt_u32 s6, s3
-; GFX10-NEXT: s_cselect_b32 s3, s6, s3
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s3
-; GFX10-NEXT: s_lshr_b32 s3, s1, 16
-; GFX10-NEXT: s_lshr_b32 s5, s2, 16
-; GFX10-NEXT: s_add_i32 s1, s1, s2
-; GFX10-NEXT: s_add_i32 s3, s3, s5
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x i32>
@@ -2914,60 +2222,38 @@ define <3 x float> @v_uaddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX8-LABEL: v_uaddsat_v6i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX8-NEXT: v_xor_b32_e32 v9, -1, v0
-; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX8-NEXT: v_xor_b32_e32 v10, -1, v6
-; GFX8-NEXT: v_min_u16_e32 v9, v9, v3
-; GFX8-NEXT: v_min_u16_sdwa v3, v10, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_xor_b32_e32 v10, -1, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX8-NEXT: v_xor_b32_e32 v11, -1, v7
-; GFX8-NEXT: v_min_u16_e32 v10, v10, v4
-; GFX8-NEXT: v_min_u16_sdwa v4, v11, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_xor_b32_e32 v11, -1, v2
-; GFX8-NEXT: v_xor_b32_e32 v12, -1, v8
-; GFX8-NEXT: v_add_u16_e32 v0, v0, v9
-; GFX8-NEXT: v_add_u16_sdwa v3, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_min_u16_e32 v11, v11, v5
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
-; GFX8-NEXT: v_min_u16_sdwa v5, v12, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_add_u16_e32 v1, v1, v10
-; GFX8-NEXT: v_add_u16_sdwa v3, v7, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX8-NEXT: v_add_u16_e32 v2, v2, v11
-; GFX8-NEXT: v_add_u16_sdwa v3, v8, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX8-NEXT: v_add_u16_e64 v6, v0, v3 clamp
+; GFX8-NEXT: v_add_u16_sdwa v0, v0, v3 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_add_u16_e64 v3, v1, v4 clamp
+; GFX8-NEXT: v_add_u16_sdwa v1, v1, v4 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_add_u16_e64 v4, v2, v5 clamp
+; GFX8-NEXT: v_add_u16_sdwa v2, v2, v5 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v5, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v3, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uaddsat_v6i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_xor_b32_e32 v6, -1, v0
-; GFX9-NEXT: v_pk_min_u16 v3, v6, v3
-; GFX9-NEXT: v_pk_add_u16 v0, v0, v3
-; GFX9-NEXT: v_xor_b32_e32 v3, -1, v1
-; GFX9-NEXT: v_pk_min_u16 v3, v3, v4
-; GFX9-NEXT: v_pk_add_u16 v1, v1, v3
-; GFX9-NEXT: v_xor_b32_e32 v3, -1, v2
-; GFX9-NEXT: v_pk_min_u16 v3, v3, v5
-; GFX9-NEXT: v_pk_add_u16 v2, v2, v3
+; GFX9-NEXT: v_pk_add_u16 v0, v0, v3 clamp
+; GFX9-NEXT: v_pk_add_u16 v1, v1, v4 clamp
+; GFX9-NEXT: v_pk_add_u16 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uaddsat_v6i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v6, -1, v0
-; GFX10-NEXT: v_xor_b32_e32 v7, -1, v1
-; GFX10-NEXT: v_xor_b32_e32 v8, -1, v2
+; GFX10-NEXT: v_pk_add_u16 v0, v0, v3 clamp
+; GFX10-NEXT: v_pk_add_u16 v1, v1, v4 clamp
+; GFX10-NEXT: v_pk_add_u16 v2, v2, v5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_min_u16 v3, v6, v3
-; GFX10-NEXT: v_pk_min_u16 v4, v7, v4
-; GFX10-NEXT: v_pk_min_u16 v5, v8, v5
-; GFX10-NEXT: v_pk_add_u16 v0, v0, v3
-; GFX10-NEXT: v_pk_add_u16 v1, v1, v4
-; GFX10-NEXT: v_pk_add_u16 v2, v2, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x i16> @llvm.uadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x float>
@@ -3036,161 +2322,58 @@ define amdgpu_ps <3 x i32> @s_uaddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inre
;
; GFX8-LABEL: s_uaddsat_v6i16:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_xor_b32 s12, s0, -1
; GFX8-NEXT: s_lshr_b32 s9, s3, 16
+; GFX8-NEXT: s_lshr_b32 s10, s4, 16
; GFX8-NEXT: s_lshr_b32 s6, s0, 16
+; GFX8-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NEXT: v_mov_b32_e32 v0, s3
+; GFX8-NEXT: s_lshr_b32 s11, s5, 16
; GFX8-NEXT: s_lshr_b32 s7, s1, 16
+; GFX8-NEXT: v_mov_b32_e32 v3, s10
+; GFX8-NEXT: v_add_u16_e64 v1, s6, v1 clamp
+; GFX8-NEXT: v_mov_b32_e32 v6, 16
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_lshr_b32 s8, s2, 16
-; GFX8-NEXT: s_lshr_b32 s10, s4, 16
-; GFX8-NEXT: s_lshr_b32 s11, s5, 16
-; GFX8-NEXT: s_bfe_u32 s12, s12, 0x100000
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s12, s3
-; GFX8-NEXT: s_cselect_b32 s3, s12, s3
-; GFX8-NEXT: s_add_i32 s0, s0, s3
-; GFX8-NEXT: s_xor_b32 s3, s6, -1
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_bfe_u32 s9, s9, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s3, s9
-; GFX8-NEXT: s_cselect_b32 s3, s3, s9
-; GFX8-NEXT: s_add_i32 s6, s6, s3
-; GFX8-NEXT: s_xor_b32 s3, s1, -1
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s3, s4
-; GFX8-NEXT: s_cselect_b32 s3, s3, s4
-; GFX8-NEXT: s_add_i32 s1, s1, s3
-; GFX8-NEXT: s_xor_b32 s3, s7, -1
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_bfe_u32 s4, s10, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s3, s4
-; GFX8-NEXT: s_cselect_b32 s3, s3, s4
-; GFX8-NEXT: s_add_i32 s7, s7, s3
-; GFX8-NEXT: s_xor_b32 s3, s2, -1
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_bfe_u32 s4, s5, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s3, s4
-; GFX8-NEXT: s_cselect_b32 s3, s3, s4
-; GFX8-NEXT: s_add_i32 s2, s2, s3
-; GFX8-NEXT: s_xor_b32 s3, s8, -1
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_bfe_u32 s4, s11, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s3, s4
-; GFX8-NEXT: s_cselect_b32 s3, s3, s4
-; GFX8-NEXT: s_add_i32 s8, s8, s3
-; GFX8-NEXT: s_bfe_u32 s3, s6, 0x100000
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_lshl_b32 s3, s3, 16
-; GFX8-NEXT: s_or_b32 s0, s0, s3
-; GFX8-NEXT: s_bfe_u32 s3, s7, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_lshl_b32 s3, s3, 16
-; GFX8-NEXT: s_or_b32 s1, s1, s3
-; GFX8-NEXT: s_bfe_u32 s3, s8, 0x100000
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_lshl_b32 s3, s3, 16
-; GFX8-NEXT: s_or_b32 s2, s2, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s11
+; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_add_u16_e64 v3, s7, v3 clamp
+; GFX8-NEXT: v_mov_b32_e32 v4, s5
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_add_u16_e64 v2, s1, v2 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_add_u16_e64 v5, s8, v5 clamp
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_add_u16_e64 v4, s2, v4 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_v6i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_xor_b32 s6, s0, -1
-; GFX9-NEXT: s_mov_b32 s8, 0xffff
-; GFX9-NEXT: s_lshr_b32 s7, s6, 16
-; GFX9-NEXT: s_lshr_b32 s9, s3, 16
-; GFX9-NEXT: s_and_b32 s6, s6, s8
-; GFX9-NEXT: s_and_b32 s3, s3, s8
-; GFX9-NEXT: s_cmp_lt_u32 s6, s3
-; GFX9-NEXT: s_cselect_b32 s3, s6, s3
-; GFX9-NEXT: s_cmp_lt_u32 s7, s9
-; GFX9-NEXT: s_cselect_b32 s6, s7, s9
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s6
-; GFX9-NEXT: s_lshr_b32 s6, s0, 16
-; GFX9-NEXT: s_lshr_b32 s7, s3, 16
-; GFX9-NEXT: s_add_i32 s0, s0, s3
-; GFX9-NEXT: s_add_i32 s6, s6, s7
-; GFX9-NEXT: s_xor_b32 s3, s1, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s6
-; GFX9-NEXT: s_lshr_b32 s6, s3, 16
-; GFX9-NEXT: s_lshr_b32 s7, s4, 16
-; GFX9-NEXT: s_and_b32 s3, s3, s8
-; GFX9-NEXT: s_and_b32 s4, s4, s8
-; GFX9-NEXT: s_cmp_lt_u32 s3, s4
-; GFX9-NEXT: s_cselect_b32 s3, s3, s4
-; GFX9-NEXT: s_cmp_lt_u32 s6, s7
-; GFX9-NEXT: s_cselect_b32 s4, s6, s7
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4
-; GFX9-NEXT: s_lshr_b32 s4, s1, 16
-; GFX9-NEXT: s_lshr_b32 s6, s3, 16
-; GFX9-NEXT: s_add_i32 s1, s1, s3
-; GFX9-NEXT: s_add_i32 s4, s4, s6
-; GFX9-NEXT: s_xor_b32 s3, s2, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4
-; GFX9-NEXT: s_lshr_b32 s4, s3, 16
-; GFX9-NEXT: s_lshr_b32 s6, s5, 16
-; GFX9-NEXT: s_and_b32 s3, s3, s8
-; GFX9-NEXT: s_and_b32 s5, s5, s8
-; GFX9-NEXT: s_cmp_lt_u32 s3, s5
-; GFX9-NEXT: s_cselect_b32 s3, s3, s5
-; GFX9-NEXT: s_cmp_lt_u32 s4, s6
-; GFX9-NEXT: s_cselect_b32 s4, s4, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4
-; GFX9-NEXT: s_lshr_b32 s4, s2, 16
-; GFX9-NEXT: s_lshr_b32 s5, s3, 16
-; GFX9-NEXT: s_add_i32 s2, s2, s3
-; GFX9-NEXT: s_add_i32 s4, s4, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp
+; GFX9-NEXT: v_pk_add_u16 v1, s1, v1 clamp
+; GFX9-NEXT: v_pk_add_u16 v2, s2, v2 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_v6i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_xor_b32 s6, s0, -1
-; GFX10-NEXT: s_mov_b32 s7, 0xffff
-; GFX10-NEXT: s_lshr_b32 s8, s6, 16
-; GFX10-NEXT: s_and_b32 s9, s3, s7
-; GFX10-NEXT: s_and_b32 s6, s6, s7
-; GFX10-NEXT: s_lshr_b32 s3, s3, 16
-; GFX10-NEXT: s_cmp_lt_u32 s6, s9
+; GFX10-NEXT: v_pk_add_u16 v0, s0, s3 clamp
+; GFX10-NEXT: v_pk_add_u16 v1, s1, s4 clamp
+; GFX10-NEXT: v_pk_add_u16 v2, s2, s5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s6, s6, s9
-; GFX10-NEXT: s_cmp_lt_u32 s8, s3
-; GFX10-NEXT: s_cselect_b32 s3, s8, s3
-; GFX10-NEXT: s_and_b32 s9, s4, s7
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s6, s3
-; GFX10-NEXT: s_lshr_b32 s6, s0, 16
-; GFX10-NEXT: s_lshr_b32 s8, s3, 16
-; GFX10-NEXT: s_add_i32 s0, s0, s3
-; GFX10-NEXT: s_xor_b32 s3, s1, -1
-; GFX10-NEXT: s_add_i32 s6, s6, s8
-; GFX10-NEXT: s_lshr_b32 s8, s3, 16
-; GFX10-NEXT: s_and_b32 s3, s3, s7
-; GFX10-NEXT: s_lshr_b32 s4, s4, 16
-; GFX10-NEXT: s_cmp_lt_u32 s3, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s6
-; GFX10-NEXT: s_cselect_b32 s3, s3, s9
-; GFX10-NEXT: s_cmp_lt_u32 s8, s4
-; GFX10-NEXT: s_cselect_b32 s4, s8, s4
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s4
-; GFX10-NEXT: s_lshr_b32 s4, s1, 16
-; GFX10-NEXT: s_lshr_b32 s8, s3, 16
-; GFX10-NEXT: s_add_i32 s1, s1, s3
-; GFX10-NEXT: s_xor_b32 s3, s2, -1
-; GFX10-NEXT: s_add_i32 s4, s4, s8
-; GFX10-NEXT: s_lshr_b32 s8, s3, 16
-; GFX10-NEXT: s_and_b32 s3, s3, s7
-; GFX10-NEXT: s_and_b32 s7, s5, s7
-; GFX10-NEXT: s_lshr_b32 s5, s5, 16
-; GFX10-NEXT: s_cmp_lt_u32 s3, s7
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s4
-; GFX10-NEXT: s_cselect_b32 s3, s3, s7
-; GFX10-NEXT: s_cmp_lt_u32 s8, s5
-; GFX10-NEXT: s_cselect_b32 s5, s8, s5
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s5
-; GFX10-NEXT: s_lshr_b32 s5, s2, 16
-; GFX10-NEXT: s_lshr_b32 s6, s3, 16
-; GFX10-NEXT: s_add_i32 s2, s2, s3
-; GFX10-NEXT: s_add_i32 s5, s5, s6
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s5
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: ; return to shader part epilog
%result = call <6 x i16> @llvm.uadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x i32>
@@ -3271,74 +2454,44 @@ define <4 x float> @v_uaddsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX8-LABEL: v_uaddsat_v8i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX8-NEXT: v_xor_b32_e32 v12, -1, v0
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX8-NEXT: v_xor_b32_e32 v13, -1, v8
-; GFX8-NEXT: v_min_u16_e32 v12, v12, v4
-; GFX8-NEXT: v_min_u16_sdwa v4, v13, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_xor_b32_e32 v13, -1, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX8-NEXT: v_xor_b32_e32 v14, -1, v9
-; GFX8-NEXT: v_min_u16_e32 v13, v13, v5
-; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX8-NEXT: v_min_u16_sdwa v5, v14, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_xor_b32_e32 v14, -1, v2
-; GFX8-NEXT: v_xor_b32_e32 v15, -1, v10
-; GFX8-NEXT: v_add_u16_e32 v0, v0, v12
-; GFX8-NEXT: v_add_u16_sdwa v4, v8, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_min_u16_e32 v14, v14, v6
-; GFX8-NEXT: v_min_u16_sdwa v6, v15, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_xor_b32_e32 v15, -1, v3
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX8-NEXT: v_xor_b32_e32 v16, -1, v11
-; GFX8-NEXT: v_add_u16_e32 v1, v1, v13
-; GFX8-NEXT: v_add_u16_sdwa v4, v9, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_min_u16_e32 v15, v15, v7
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX8-NEXT: v_min_u16_sdwa v7, v16, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_add_u16_e32 v2, v2, v14
-; GFX8-NEXT: v_add_u16_sdwa v4, v10, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX8-NEXT: v_add_u16_e32 v3, v3, v15
-; GFX8-NEXT: v_add_u16_sdwa v4, v11, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX8-NEXT: v_add_u16_e64 v8, v0, v4 clamp
+; GFX8-NEXT: v_add_u16_sdwa v0, v0, v4 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_add_u16_e64 v4, v1, v5 clamp
+; GFX8-NEXT: v_add_u16_sdwa v1, v1, v5 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_add_u16_e64 v5, v2, v6 clamp
+; GFX8-NEXT: v_add_u16_sdwa v2, v2, v6 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_add_u16_e64 v6, v3, v7 clamp
+; GFX8-NEXT: v_add_u16_sdwa v3, v3, v7 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v7, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_mov_b32_e32 v7, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uaddsat_v8i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_xor_b32_e32 v8, -1, v0
-; GFX9-NEXT: v_pk_min_u16 v4, v8, v4
-; GFX9-NEXT: v_pk_add_u16 v0, v0, v4
-; GFX9-NEXT: v_xor_b32_e32 v4, -1, v1
-; GFX9-NEXT: v_pk_min_u16 v4, v4, v5
-; GFX9-NEXT: v_pk_add_u16 v1, v1, v4
-; GFX9-NEXT: v_xor_b32_e32 v4, -1, v2
-; GFX9-NEXT: v_pk_min_u16 v4, v4, v6
-; GFX9-NEXT: v_pk_add_u16 v2, v2, v4
-; GFX9-NEXT: v_xor_b32_e32 v4, -1, v3
-; GFX9-NEXT: v_pk_min_u16 v4, v4, v7
-; GFX9-NEXT: v_pk_add_u16 v3, v3, v4
+; GFX9-NEXT: v_pk_add_u16 v0, v0, v4 clamp
+; GFX9-NEXT: v_pk_add_u16 v1, v1, v5 clamp
+; GFX9-NEXT: v_pk_add_u16 v2, v2, v6 clamp
+; GFX9-NEXT: v_pk_add_u16 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uaddsat_v8i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v15, -1, v0
-; GFX10-NEXT: v_xor_b32_e32 v19, -1, v1
-; GFX10-NEXT: v_xor_b32_e32 v23, -1, v2
-; GFX10-NEXT: v_xor_b32_e32 v10, -1, v3
+; GFX10-NEXT: v_pk_add_u16 v0, v0, v4 clamp
+; GFX10-NEXT: v_pk_add_u16 v1, v1, v5 clamp
+; GFX10-NEXT: v_pk_add_u16 v2, v2, v6 clamp
+; GFX10-NEXT: v_pk_add_u16 v3, v3, v7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_min_u16 v11, v15, v4
-; GFX10-NEXT: v_pk_min_u16 v15, v19, v5
-; GFX10-NEXT: v_pk_min_u16 v19, v23, v6
-; GFX10-NEXT: v_pk_min_u16 v6, v10, v7
-; GFX10-NEXT: v_pk_add_u16 v0, v0, v11
-; GFX10-NEXT: v_pk_add_u16 v1, v1, v15
-; GFX10-NEXT: v_pk_add_u16 v2, v2, v19
-; GFX10-NEXT: v_pk_add_u16 v3, v3, v6
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x float>
@@ -3425,209 +2578,72 @@ define amdgpu_ps <4 x i32> @s_uaddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inre
;
; GFX8-LABEL: s_uaddsat_v8i16:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_xor_b32 s16, s0, -1
; GFX8-NEXT: s_lshr_b32 s12, s4, 16
+; GFX8-NEXT: s_lshr_b32 s13, s5, 16
; GFX8-NEXT: s_lshr_b32 s8, s0, 16
+; GFX8-NEXT: v_mov_b32_e32 v1, s12
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: s_lshr_b32 s14, s6, 16
+; GFX8-NEXT: s_lshr_b32 s15, s7, 16
; GFX8-NEXT: s_lshr_b32 s9, s1, 16
+; GFX8-NEXT: v_mov_b32_e32 v3, s13
+; GFX8-NEXT: v_add_u16_e64 v1, s8, v1 clamp
+; GFX8-NEXT: v_mov_b32_e32 v8, 16
+; GFX8-NEXT: v_mov_b32_e32 v2, s5
; GFX8-NEXT: s_lshr_b32 s10, s2, 16
+; GFX8-NEXT: v_mov_b32_e32 v5, s14
; GFX8-NEXT: s_lshr_b32 s11, s3, 16
-; GFX8-NEXT: s_lshr_b32 s13, s5, 16
-; GFX8-NEXT: s_lshr_b32 s14, s6, 16
-; GFX8-NEXT: s_lshr_b32 s15, s7, 16
-; GFX8-NEXT: s_bfe_u32 s16, s16, 0x100000
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s16, s4
-; GFX8-NEXT: s_cselect_b32 s4, s16, s4
-; GFX8-NEXT: s_add_i32 s0, s0, s4
-; GFX8-NEXT: s_xor_b32 s4, s8, -1
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_bfe_u32 s12, s12, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s4, s12
-; GFX8-NEXT: s_cselect_b32 s4, s4, s12
-; GFX8-NEXT: s_add_i32 s8, s8, s4
-; GFX8-NEXT: s_xor_b32 s4, s1, -1
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s4, s5
-; GFX8-NEXT: s_cselect_b32 s4, s4, s5
-; GFX8-NEXT: s_add_i32 s1, s1, s4
-; GFX8-NEXT: s_xor_b32 s4, s9, -1
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_bfe_u32 s5, s13, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s4, s5
-; GFX8-NEXT: s_cselect_b32 s4, s4, s5
-; GFX8-NEXT: s_add_i32 s9, s9, s4
-; GFX8-NEXT: s_xor_b32 s4, s2, -1
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_bfe_u32 s5, s6, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s4, s5
-; GFX8-NEXT: s_cselect_b32 s4, s4, s5
-; GFX8-NEXT: s_add_i32 s2, s2, s4
-; GFX8-NEXT: s_xor_b32 s4, s10, -1
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_bfe_u32 s5, s14, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s4, s5
-; GFX8-NEXT: s_cselect_b32 s4, s4, s5
-; GFX8-NEXT: s_add_i32 s10, s10, s4
-; GFX8-NEXT: s_xor_b32 s4, s3, -1
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_bfe_u32 s5, s7, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s4, s5
-; GFX8-NEXT: s_cselect_b32 s4, s4, s5
-; GFX8-NEXT: s_add_i32 s3, s3, s4
-; GFX8-NEXT: s_xor_b32 s4, s11, -1
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_bfe_u32 s5, s15, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s4, s5
-; GFX8-NEXT: s_cselect_b32 s4, s4, s5
-; GFX8-NEXT: s_add_i32 s11, s11, s4
-; GFX8-NEXT: s_bfe_u32 s4, s8, 0x100000
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_lshl_b32 s4, s4, 16
-; GFX8-NEXT: s_or_b32 s0, s0, s4
-; GFX8-NEXT: s_bfe_u32 s4, s9, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_lshl_b32 s4, s4, 16
-; GFX8-NEXT: s_or_b32 s1, s1, s4
-; GFX8-NEXT: s_bfe_u32 s4, s10, 0x100000
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_lshl_b32 s4, s4, 16
-; GFX8-NEXT: s_or_b32 s2, s2, s4
-; GFX8-NEXT: s_bfe_u32 s4, s11, 0x100000
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_lshl_b32 s4, s4, 16
-; GFX8-NEXT: s_or_b32 s3, s3, s4
+; GFX8-NEXT: v_mov_b32_e32 v7, s15
+; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_add_u16_e64 v3, s9, v3 clamp
+; GFX8-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NEXT: v_mov_b32_e32 v6, s7
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_add_u16_e64 v2, s1, v2 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_add_u16_e64 v7, s11, v7 clamp
+; GFX8-NEXT: v_add_u16_e64 v5, s10, v5 clamp
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_add_u16_e64 v4, s2, v4 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v8, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_add_u16_e64 v6, s3, v6 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
+; GFX8-NEXT: v_readfirstlane_b32 s3, v3
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_uaddsat_v8i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_xor_b32 s8, s0, -1
-; GFX9-NEXT: s_mov_b32 s10, 0xffff
-; GFX9-NEXT: s_lshr_b32 s9, s8, 16
-; GFX9-NEXT: s_lshr_b32 s11, s4, 16
-; GFX9-NEXT: s_and_b32 s8, s8, s10
-; GFX9-NEXT: s_and_b32 s4, s4, s10
-; GFX9-NEXT: s_cmp_lt_u32 s8, s4
-; GFX9-NEXT: s_cselect_b32 s4, s8, s4
-; GFX9-NEXT: s_cmp_lt_u32 s9, s11
-; GFX9-NEXT: s_cselect_b32 s8, s9, s11
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s8
-; GFX9-NEXT: s_lshr_b32 s8, s0, 16
-; GFX9-NEXT: s_lshr_b32 s9, s4, 16
-; GFX9-NEXT: s_add_i32 s0, s0, s4
-; GFX9-NEXT: s_add_i32 s8, s8, s9
-; GFX9-NEXT: s_xor_b32 s4, s1, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s8
-; GFX9-NEXT: s_lshr_b32 s8, s4, 16
-; GFX9-NEXT: s_lshr_b32 s9, s5, 16
-; GFX9-NEXT: s_and_b32 s4, s4, s10
-; GFX9-NEXT: s_and_b32 s5, s5, s10
-; GFX9-NEXT: s_cmp_lt_u32 s4, s5
-; GFX9-NEXT: s_cselect_b32 s4, s4, s5
-; GFX9-NEXT: s_cmp_lt_u32 s8, s9
-; GFX9-NEXT: s_cselect_b32 s5, s8, s9
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_lshr_b32 s5, s1, 16
-; GFX9-NEXT: s_lshr_b32 s8, s4, 16
-; GFX9-NEXT: s_add_i32 s1, s1, s4
-; GFX9-NEXT: s_add_i32 s5, s5, s8
-; GFX9-NEXT: s_xor_b32 s4, s2, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s5
-; GFX9-NEXT: s_lshr_b32 s5, s4, 16
-; GFX9-NEXT: s_lshr_b32 s8, s6, 16
-; GFX9-NEXT: s_and_b32 s4, s4, s10
-; GFX9-NEXT: s_and_b32 s6, s6, s10
-; GFX9-NEXT: s_cmp_lt_u32 s4, s6
-; GFX9-NEXT: s_cselect_b32 s4, s4, s6
-; GFX9-NEXT: s_cmp_lt_u32 s5, s8
-; GFX9-NEXT: s_cselect_b32 s5, s5, s8
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_lshr_b32 s5, s2, 16
-; GFX9-NEXT: s_lshr_b32 s6, s4, 16
-; GFX9-NEXT: s_add_i32 s2, s2, s4
-; GFX9-NEXT: s_add_i32 s5, s5, s6
-; GFX9-NEXT: s_xor_b32 s4, s3, -1
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s5
-; GFX9-NEXT: s_lshr_b32 s5, s4, 16
-; GFX9-NEXT: s_lshr_b32 s6, s7, 16
-; GFX9-NEXT: s_and_b32 s4, s4, s10
-; GFX9-NEXT: s_and_b32 s7, s7, s10
-; GFX9-NEXT: s_cmp_lt_u32 s4, s7
-; GFX9-NEXT: s_cselect_b32 s4, s4, s7
-; GFX9-NEXT: s_cmp_lt_u32 s5, s6
-; GFX9-NEXT: s_cselect_b32 s5, s5, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_lshr_b32 s5, s3, 16
-; GFX9-NEXT: s_lshr_b32 s6, s4, 16
-; GFX9-NEXT: s_add_i32 s3, s3, s4
-; GFX9-NEXT: s_add_i32 s5, s5, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s5
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-NEXT: v_pk_add_u16 v0, s0, v0 clamp
+; GFX9-NEXT: v_pk_add_u16 v1, s1, v1 clamp
+; GFX9-NEXT: v_pk_add_u16 v2, s2, v2 clamp
+; GFX9-NEXT: v_pk_add_u16 v3, s3, v3 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_uaddsat_v8i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_xor_b32 s8, s0, -1
-; GFX10-NEXT: s_mov_b32 s9, 0xffff
-; GFX10-NEXT: s_lshr_b32 s10, s8, 16
-; GFX10-NEXT: s_and_b32 s11, s4, s9
-; GFX10-NEXT: s_and_b32 s8, s8, s9
-; GFX10-NEXT: s_lshr_b32 s4, s4, 16
-; GFX10-NEXT: s_cmp_lt_u32 s8, s11
+; GFX10-NEXT: v_pk_add_u16 v0, s0, s4 clamp
+; GFX10-NEXT: v_pk_add_u16 v1, s1, s5 clamp
+; GFX10-NEXT: v_pk_add_u16 v2, s2, s6 clamp
+; GFX10-NEXT: v_pk_add_u16 v3, s3, s7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s8, s8, s11
-; GFX10-NEXT: s_cmp_lt_u32 s10, s4
-; GFX10-NEXT: s_cselect_b32 s4, s10, s4
-; GFX10-NEXT: s_and_b32 s11, s5, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s8, s4
-; GFX10-NEXT: s_lshr_b32 s8, s0, 16
-; GFX10-NEXT: s_lshr_b32 s10, s4, 16
-; GFX10-NEXT: s_add_i32 s0, s0, s4
-; GFX10-NEXT: s_xor_b32 s4, s1, -1
-; GFX10-NEXT: s_add_i32 s8, s8, s10
-; GFX10-NEXT: s_lshr_b32 s10, s4, 16
-; GFX10-NEXT: s_and_b32 s4, s4, s9
-; GFX10-NEXT: s_lshr_b32 s5, s5, 16
-; GFX10-NEXT: s_cmp_lt_u32 s4, s11
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s8
-; GFX10-NEXT: s_cselect_b32 s4, s4, s11
-; GFX10-NEXT: s_cmp_lt_u32 s10, s5
-; GFX10-NEXT: s_cselect_b32 s5, s10, s5
-; GFX10-NEXT: s_and_b32 s11, s6, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX10-NEXT: s_lshr_b32 s5, s1, 16
-; GFX10-NEXT: s_lshr_b32 s10, s4, 16
-; GFX10-NEXT: s_add_i32 s1, s1, s4
-; GFX10-NEXT: s_xor_b32 s4, s2, -1
-; GFX10-NEXT: s_add_i32 s5, s5, s10
-; GFX10-NEXT: s_lshr_b32 s10, s4, 16
-; GFX10-NEXT: s_and_b32 s4, s4, s9
-; GFX10-NEXT: s_lshr_b32 s6, s6, 16
-; GFX10-NEXT: s_cmp_lt_u32 s4, s11
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5
-; GFX10-NEXT: s_cselect_b32 s4, s4, s11
-; GFX10-NEXT: s_cmp_lt_u32 s10, s6
-; GFX10-NEXT: s_cselect_b32 s6, s10, s6
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s6
-; GFX10-NEXT: s_lshr_b32 s6, s2, 16
-; GFX10-NEXT: s_lshr_b32 s10, s4, 16
-; GFX10-NEXT: s_add_i32 s2, s2, s4
-; GFX10-NEXT: s_xor_b32 s4, s3, -1
-; GFX10-NEXT: s_add_i32 s6, s6, s10
-; GFX10-NEXT: s_lshr_b32 s10, s4, 16
-; GFX10-NEXT: s_and_b32 s4, s4, s9
-; GFX10-NEXT: s_and_b32 s9, s7, s9
-; GFX10-NEXT: s_lshr_b32 s7, s7, 16
-; GFX10-NEXT: s_cmp_lt_u32 s4, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s6
-; GFX10-NEXT: s_cselect_b32 s4, s4, s9
-; GFX10-NEXT: s_cmp_lt_u32 s10, s7
-; GFX10-NEXT: s_cselect_b32 s7, s10, s7
-; GFX10-NEXT: s_lshr_b32 s5, s3, 16
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s4, s7
-; GFX10-NEXT: s_lshr_b32 s7, s4, 16
-; GFX10-NEXT: s_add_i32 s3, s3, s4
-; GFX10-NEXT: s_add_i32 s5, s5, s7
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s5
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: ; return to shader part epilog
%result = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x i32>
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
index b111fd31851c..8553853ff00c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
@@ -20,8 +20,7 @@ define i7 @v_usubsat_i7(i7 %lhs, i7 %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 9, v1
-; GFX8-NEXT: v_min_u16_e32 v1, v0, v1
-; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
; GFX8-NEXT: v_lshrrev_b16_e32 v0, 9, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -30,8 +29,7 @@ define i7 @v_usubsat_i7(i7 %lhs, i7 %rhs) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 9, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 9, v1
-; GFX9-NEXT: v_min_u16_e32 v1, v0, v1
-; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
; GFX9-NEXT: v_lshrrev_b16_e32 v0, 9, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -42,8 +40,7 @@ define i7 @v_usubsat_i7(i7 %lhs, i7 %rhs) {
; GFX10-NEXT: v_lshlrev_b16_e64 v0, 9, v0
; GFX10-NEXT: v_lshlrev_b16_e64 v1, 9, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u16_e64 v1, v0, v1
-; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1
+; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 clamp
; GFX10-NEXT: v_lshrrev_b16_e64 v0, 9, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs)
@@ -66,13 +63,10 @@ define amdgpu_ps i7 @s_usubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000
; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_lshl_b32 s0, s0, s2
-; GFX8-NEXT: s_bfe_u32 s3, s0, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s3, s1
-; GFX8-NEXT: s_cselect_b32 s1, s3, s1
-; GFX8-NEXT: s_sub_i32 s0, s0, s1
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_lshr_b32 s0, s0, s2
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_lshrrev_b16_e32 v0, 9, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_i7:
@@ -80,28 +74,21 @@ define amdgpu_ps i7 @s_usubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX9-NEXT: s_bfe_u32 s2, 9, 0x100000
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
; GFX9-NEXT: s_lshl_b32 s0, s0, s2
-; GFX9-NEXT: s_bfe_u32 s3, s0, 0x100000
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s3, s1
-; GFX9-NEXT: s_cselect_b32 s1, s3, s1
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
-; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX9-NEXT: s_lshr_b32 s0, s0, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_lshrrev_b16_e32 v0, 9, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_i7:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s2, 9, 0x100000
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: s_bfe_u32 s3, s0, 0x100000
-; GFX10-NEXT: s_cmp_lt_u32 s3, s1
-; GFX10-NEXT: s_cselect_b32 s1, s3, s1
-; GFX10-NEXT: s_sub_i32 s0, s0, s1
-; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX10-NEXT: s_lshr_b32 s0, s0, s2
+; GFX10-NEXT: s_lshl_b32 s1, s1, s2
+; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, s1 clamp
+; GFX10-NEXT: v_lshrrev_b16_e64 v0, 9, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result
@@ -123,8 +110,7 @@ define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX8-NEXT: v_min_u16_e32 v1, v0, v1
-; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -133,8 +119,7 @@ define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX9-NEXT: v_min_u16_e32 v1, v0, v1
-; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -145,8 +130,7 @@ define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) {
; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0
; GFX10-NEXT: v_lshlrev_b16_e64 v1, 8, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u16_e64 v1, v0, v1
-; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1
+; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 clamp
; GFX10-NEXT: v_lshrrev_b16_e64 v0, 8, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
@@ -169,13 +153,10 @@ define amdgpu_ps i8 @s_usubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000
; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_lshl_b32 s0, s0, s2
-; GFX8-NEXT: s_bfe_u32 s3, s0, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s3, s1
-; GFX8-NEXT: s_cselect_b32 s1, s3, s1
-; GFX8-NEXT: s_sub_i32 s0, s0, s1
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_lshr_b32 s0, s0, s2
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_i8:
@@ -183,28 +164,21 @@ define amdgpu_ps i8 @s_usubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX9-NEXT: s_bfe_u32 s2, 8, 0x100000
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
; GFX9-NEXT: s_lshl_b32 s0, s0, s2
-; GFX9-NEXT: s_bfe_u32 s3, s0, 0x100000
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s3, s1
-; GFX9-NEXT: s_cselect_b32 s1, s3, s1
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
-; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX9-NEXT: s_lshr_b32 s0, s0, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: s_bfe_u32 s3, s0, 0x100000
-; GFX10-NEXT: s_cmp_lt_u32 s3, s1
-; GFX10-NEXT: s_cselect_b32 s1, s3, s1
-; GFX10-NEXT: s_sub_i32 s0, s0, s1
-; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX10-NEXT: s_lshr_b32 s0, s0, s2
+; GFX10-NEXT: s_lshl_b32 s1, s1, s2
+; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, s1 clamp
+; GFX10-NEXT: v_lshrrev_b16_e64 v0, 8, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result
@@ -241,11 +215,9 @@ define i16 @v_usubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX8-NEXT: v_min_u16_e32 v1, v0, v1
-; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
-; GFX8-NEXT: v_min_u16_e32 v1, v3, v2
+; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
+; GFX8-NEXT: v_sub_u16_e64 v1, v3, v2 clamp
; GFX8-NEXT: v_mov_b32_e32 v2, 0xff
-; GFX8-NEXT: v_sub_u16_e32 v1, v3, v1
; GFX8-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
@@ -259,11 +231,9 @@ define i16 @v_usubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX9-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX9-NEXT: v_min_u16_e32 v1, v0, v1
-; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1
-; GFX9-NEXT: v_min_u16_e32 v1, v2, v3
+; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: v_sub_u16_e32 v1, v2, v1
+; GFX9-NEXT: v_sub_u16_e64 v1, v2, v3 clamp
; GFX9-NEXT: v_and_b32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
@@ -280,10 +250,8 @@ define i16 @v_usubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX10-NEXT: v_lshlrev_b16_e64 v0, 8, v0
; GFX10-NEXT: s_movk_i32 s4, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u16_e64 v1, v2, v1
-; GFX10-NEXT: v_min_u16_e64 v3, v0, v3
-; GFX10-NEXT: v_sub_nc_u16_e64 v1, v2, v1
-; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v3
+; GFX10-NEXT: v_sub_nc_u16_e64 v1, v2, v1 clamp
+; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v3 clamp
; GFX10-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_and_b32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
@@ -322,92 +290,60 @@ define amdgpu_ps i16 @s_usubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX8-LABEL: s_usubsat_v2i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000
-; GFX8-NEXT: s_lshr_b32 s2, s0, 8
; GFX8-NEXT: s_lshr_b32 s3, s1, 8
; GFX8-NEXT: s_lshl_b32 s1, s1, s4
+; GFX8-NEXT: s_lshr_b32 s2, s0, 8
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
; GFX8-NEXT: s_lshl_b32 s0, s0, s4
-; GFX8-NEXT: s_bfe_u32 s5, s0, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s5, s1
-; GFX8-NEXT: s_cselect_b32 s1, s5, s1
-; GFX8-NEXT: s_sub_i32 s0, s0, s1
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_lshl_b32 s1, s2, s4
-; GFX8-NEXT: s_lshl_b32 s2, s3, s4
-; GFX8-NEXT: s_lshr_b32 s0, s0, s4
-; GFX8-NEXT: s_bfe_u32 s3, s1, 0x100000
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s3, s2
-; GFX8-NEXT: s_cselect_b32 s2, s3, s2
-; GFX8-NEXT: s_sub_i32 s1, s1, s2
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_movk_i32 s2, 0xff
-; GFX8-NEXT: s_lshr_b32 s1, s1, s4
-; GFX8-NEXT: s_and_b32 s1, s1, s2
-; GFX8-NEXT: s_and_b32 s0, s0, s2
-; GFX8-NEXT: s_lshl_b32 s1, s1, s4
-; GFX8-NEXT: s_or_b32 s0, s0, s1
+; GFX8-NEXT: s_lshl_b32 s1, s3, s4
+; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: s_lshl_b32 s0, s2, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0xff
+; GFX8-NEXT: v_sub_u16_e64 v1, s0, v1 clamp
+; GFX8-NEXT: v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_sdwa v1, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_v2i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s4, 8, 0x100000
-; GFX9-NEXT: s_lshr_b32 s2, s0, 8
; GFX9-NEXT: s_lshr_b32 s3, s1, 8
; GFX9-NEXT: s_lshl_b32 s1, s1, s4
+; GFX9-NEXT: s_lshr_b32 s2, s0, 8
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: s_lshl_b32 s0, s0, s4
-; GFX9-NEXT: s_bfe_u32 s5, s0, 0x100000
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s5, s1
-; GFX9-NEXT: s_cselect_b32 s1, s5, s1
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
-; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX9-NEXT: s_lshl_b32 s1, s2, s4
-; GFX9-NEXT: s_lshl_b32 s2, s3, s4
-; GFX9-NEXT: s_lshr_b32 s0, s0, s4
-; GFX9-NEXT: s_bfe_u32 s3, s1, 0x100000
-; GFX9-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s3, s2
-; GFX9-NEXT: s_cselect_b32 s2, s3, s2
-; GFX9-NEXT: s_sub_i32 s1, s1, s2
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: s_movk_i32 s2, 0xff
-; GFX9-NEXT: s_lshr_b32 s1, s1, s4
-; GFX9-NEXT: s_and_b32 s1, s1, s2
-; GFX9-NEXT: s_and_b32 s0, s0, s2
-; GFX9-NEXT: s_lshl_b32 s1, s1, s4
-; GFX9-NEXT: s_or_b32 s0, s0, s1
+; GFX9-NEXT: s_lshl_b32 s1, s3, s4
+; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
+; GFX9-NEXT: s_lshl_b32 s0, s2, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: v_sub_u16_e64 v1, s0, v1 clamp
+; GFX9-NEXT: s_movk_i32 s0, 0xff
+; GFX9-NEXT: v_and_b32_sdwa v0, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_v2i8:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000
-; GFX10-NEXT: s_lshr_b32 s3, s0, 8
-; GFX10-NEXT: s_lshl_b32 s4, s1, s2
-; GFX10-NEXT: s_lshl_b32 s0, s0, s2
-; GFX10-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX10-NEXT: s_bfe_u32 s5, s0, 0x100000
-; GFX10-NEXT: s_lshr_b32 s1, s1, 8
-; GFX10-NEXT: s_cmp_lt_u32 s5, s4
+; GFX10-NEXT: s_lshr_b32 s2, s0, 8
+; GFX10-NEXT: s_bfe_u32 s3, 8, 0x100000
+; GFX10-NEXT: s_lshr_b32 s4, s1, 8
+; GFX10-NEXT: s_lshl_b32 s0, s0, s3
+; GFX10-NEXT: s_lshl_b32 s1, s1, s3
+; GFX10-NEXT: s_lshl_b32 s2, s2, s3
+; GFX10-NEXT: s_lshl_b32 s3, s4, s3
+; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, s1 clamp
+; GFX10-NEXT: v_sub_nc_u16_e64 v1, s2, s3 clamp
+; GFX10-NEXT: s_movk_i32 s0, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s4, s5, s4
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: s_sub_i32 s0, s0, s4
-; GFX10-NEXT: s_lshl_b32 s3, s3, s2
-; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX10-NEXT: s_bfe_u32 s4, s3, 0x100000
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: s_lshr_b32 s0, s0, s2
-; GFX10-NEXT: s_cmp_lt_u32 s4, s1
-; GFX10-NEXT: s_cselect_b32 s1, s4, s1
-; GFX10-NEXT: s_sub_i32 s1, s3, s1
-; GFX10-NEXT: s_movk_i32 s3, 0xff
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: s_and_b32 s0, s0, s3
-; GFX10-NEXT: s_lshr_b32 s1, s1, s2
-; GFX10-NEXT: s_and_b32 s1, s1, s3
-; GFX10-NEXT: s_lshl_b32 s1, s1, s2
-; GFX10-NEXT: s_or_b32 s0, s0, s1
+; GFX10-NEXT: v_and_b32_sdwa v0, v0, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
@@ -471,18 +407,14 @@ define i32 @v_usubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX8-NEXT: v_min_u16_e32 v1, v0, v1
-; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
-; GFX8-NEXT: v_min_u16_e32 v1, v3, v2
-; GFX8-NEXT: v_sub_u16_e32 v1, v3, v1
+; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
+; GFX8-NEXT: v_sub_u16_e64 v1, v3, v2 clamp
; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v4
; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v6
-; GFX8-NEXT: v_min_u16_e32 v3, v2, v3
-; GFX8-NEXT: v_sub_u16_e32 v2, v2, v3
+; GFX8-NEXT: v_sub_u16_e64 v2, v2, v3 clamp
; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v5
; GFX8-NEXT: v_lshlrev_b16_e32 v4, 8, v7
-; GFX8-NEXT: v_min_u16_e32 v4, v3, v4
-; GFX8-NEXT: v_sub_u16_e32 v3, v3, v4
+; GFX8-NEXT: v_sub_u16_e64 v3, v3, v4 clamp
; GFX8-NEXT: v_mov_b32_e32 v4, 0xff
; GFX8-NEXT: v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
@@ -506,22 +438,18 @@ define i32 @v_usubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
-; GFX9-NEXT: v_min_u16_e32 v1, v0, v1
-; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1
-; GFX9-NEXT: v_min_u16_e32 v1, v2, v5
-; GFX9-NEXT: v_sub_u16_e32 v1, v2, v1
+; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
+; GFX9-NEXT: v_sub_u16_e64 v1, v2, v5 clamp
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v3
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v6
-; GFX9-NEXT: v_min_u16_e32 v3, v2, v3
-; GFX9-NEXT: v_sub_u16_e32 v2, v2, v3
-; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v4
-; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v7
; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: v_min_u16_e32 v4, v3, v4
; GFX9-NEXT: v_and_b32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_sub_u16_e64 v2, v2, v3 clamp
+; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v4
+; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v7
; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX9-NEXT: v_sub_u16_e32 v3, v3, v4
+; GFX9-NEXT: v_sub_u16_e64 v3, v3, v4 clamp
; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v1
; GFX9-NEXT: v_and_b32_sdwa v1, v2, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_sdwa v2, v3, s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
@@ -533,32 +461,28 @@ define i32 @v_usubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8
-; GFX10-NEXT: v_lshlrev_b16_e64 v4, 8, v0
+; GFX10-NEXT: v_lshlrev_b16_e64 v5, 8, v0
; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_lshlrev_b16_e64 v5, 8, v1
-; GFX10-NEXT: s_mov_b32 s4, 16
-; GFX10-NEXT: s_mov_b32 s5, 24
-; GFX10-NEXT: v_lshrrev_b32_sdwa v6, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_min_u16_e64 v3, v2, v3
-; GFX10-NEXT: v_lshrrev_b32_sdwa v7, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_min_u16_e64 v5, v4, v5
-; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s5, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_sub_nc_u16_e64 v2, v2, v3
-; GFX10-NEXT: s_movk_i32 s4, 0xff
-; GFX10-NEXT: v_min_u16_e64 v3, v6, v7
-; GFX10-NEXT: v_sub_nc_u16_e64 v4, v4, v5
-; GFX10-NEXT: v_min_u16_e64 v1, v0, v1
-; GFX10-NEXT: v_and_b32_sdwa v2, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_lshlrev_b16_e64 v6, 8, v1
+; GFX10-NEXT: s_mov_b32 s5, 16
+; GFX10-NEXT: s_mov_b32 s4, 24
+; GFX10-NEXT: v_lshrrev_b32_sdwa v4, s5, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_sub_nc_u16_e64 v2, v2, v3 clamp
+; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: s_movk_i32 s5, 0xff
+; GFX10-NEXT: v_lshrrev_b32_sdwa v0, s4, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshrrev_b32_sdwa v1, s4, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v2, v2, s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_sub_nc_u16_e64 v5, v5, v6 clamp
+; GFX10-NEXT: v_sub_nc_u16_e64 v3, v4, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u16_e64 v3, v6, v3
-; GFX10-NEXT: v_lshrrev_b16_e64 v4, 8, v4
-; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1
+; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 clamp
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; GFX10-NEXT: v_and_b32_sdwa v1, v3, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_and_b32_sdwa v0, v0, s4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX10-NEXT: v_and_or_b32 v2, v4, s4, v2
+; GFX10-NEXT: v_lshrrev_b16_e64 v4, 8, v5
+; GFX10-NEXT: v_and_b32_sdwa v1, v3, s5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v0, v0, s5 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_or_b32 v2, v4, s5, v2
; GFX10-NEXT: v_or3_b32 v0, v2, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i32 %lhs.arg to <4 x i8>
@@ -617,176 +541,107 @@ define amdgpu_ps i32 @s_usubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX8-LABEL: s_usubsat_v4i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000
-; GFX8-NEXT: s_lshr_b32 s2, s0, 8
-; GFX8-NEXT: s_lshr_b32 s3, s0, 16
-; GFX8-NEXT: s_lshr_b32 s4, s0, 24
-; GFX8-NEXT: s_lshl_b32 s0, s0, s8
; GFX8-NEXT: s_lshr_b32 s5, s1, 8
; GFX8-NEXT: s_lshr_b32 s6, s1, 16
; GFX8-NEXT: s_lshr_b32 s7, s1, 24
; GFX8-NEXT: s_lshl_b32 s1, s1, s8
-; GFX8-NEXT: s_bfe_u32 s9, s0, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s9, s1
-; GFX8-NEXT: s_cselect_b32 s1, s9, s1
-; GFX8-NEXT: s_sub_i32 s0, s0, s1
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_lshl_b32 s1, s2, s8
-; GFX8-NEXT: s_lshl_b32 s2, s5, s8
-; GFX8-NEXT: s_lshr_b32 s0, s0, s8
-; GFX8-NEXT: s_bfe_u32 s5, s1, 0x100000
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s5, s2
-; GFX8-NEXT: s_cselect_b32 s2, s5, s2
-; GFX8-NEXT: s_sub_i32 s1, s1, s2
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_lshl_b32 s2, s3, s8
-; GFX8-NEXT: s_lshl_b32 s3, s6, s8
-; GFX8-NEXT: s_lshr_b32 s1, s1, s8
-; GFX8-NEXT: s_bfe_u32 s5, s2, 0x100000
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s5, s3
-; GFX8-NEXT: s_cselect_b32 s3, s5, s3
-; GFX8-NEXT: s_sub_i32 s2, s2, s3
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_lshl_b32 s3, s4, s8
-; GFX8-NEXT: s_lshl_b32 s4, s7, s8
-; GFX8-NEXT: s_lshr_b32 s2, s2, s8
-; GFX8-NEXT: s_bfe_u32 s5, s3, 0x100000
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s5, s4
-; GFX8-NEXT: s_cselect_b32 s4, s5, s4
-; GFX8-NEXT: s_sub_i32 s3, s3, s4
-; GFX8-NEXT: s_movk_i32 s4, 0xff
-; GFX8-NEXT: s_and_b32 s1, s1, s4
-; GFX8-NEXT: s_and_b32 s0, s0, s4
-; GFX8-NEXT: s_lshl_b32 s1, s1, 8
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_or_b32 s0, s0, s1
-; GFX8-NEXT: s_and_b32 s1, s2, s4
-; GFX8-NEXT: s_lshl_b32 s1, s1, 16
-; GFX8-NEXT: s_lshr_b32 s3, s3, s8
-; GFX8-NEXT: s_or_b32 s0, s0, s1
-; GFX8-NEXT: s_and_b32 s1, s3, s4
-; GFX8-NEXT: s_lshl_b32 s1, s1, 24
-; GFX8-NEXT: s_or_b32 s0, s0, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: s_lshl_b32 s1, s5, s8
+; GFX8-NEXT: s_lshr_b32 s2, s0, 8
+; GFX8-NEXT: s_lshr_b32 s3, s0, 16
+; GFX8-NEXT: s_lshr_b32 s4, s0, 24
+; GFX8-NEXT: s_lshl_b32 s0, s0, s8
+; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_lshl_b32 s0, s2, s8
+; GFX8-NEXT: v_sub_u16_e64 v1, s0, v1 clamp
+; GFX8-NEXT: v_mov_b32_e32 v4, 0xff
+; GFX8-NEXT: s_lshl_b32 s1, s6, s8
+; GFX8-NEXT: v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: s_lshl_b32 s0, s3, s8
+; GFX8-NEXT: s_lshl_b32 s1, s7, s8
+; GFX8-NEXT: v_sub_u16_e64 v2, s0, v2 clamp
+; GFX8-NEXT: s_lshl_b32 s0, s4, s8
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_and_b32_sdwa v1, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_sub_u16_e64 v3, s0, v3 clamp
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_v4i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s8, 8, 0x100000
-; GFX9-NEXT: s_lshr_b32 s2, s0, 8
-; GFX9-NEXT: s_lshr_b32 s3, s0, 16
-; GFX9-NEXT: s_lshr_b32 s4, s0, 24
-; GFX9-NEXT: s_lshl_b32 s0, s0, s8
; GFX9-NEXT: s_lshr_b32 s5, s1, 8
; GFX9-NEXT: s_lshr_b32 s6, s1, 16
; GFX9-NEXT: s_lshr_b32 s7, s1, 24
; GFX9-NEXT: s_lshl_b32 s1, s1, s8
-; GFX9-NEXT: s_bfe_u32 s9, s0, 0x100000
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s9, s1
-; GFX9-NEXT: s_cselect_b32 s1, s9, s1
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
-; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX9-NEXT: s_lshl_b32 s1, s2, s8
-; GFX9-NEXT: s_lshl_b32 s2, s5, s8
-; GFX9-NEXT: s_lshr_b32 s0, s0, s8
-; GFX9-NEXT: s_bfe_u32 s5, s1, 0x100000
-; GFX9-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s5, s2
-; GFX9-NEXT: s_cselect_b32 s2, s5, s2
-; GFX9-NEXT: s_sub_i32 s1, s1, s2
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: s_lshl_b32 s2, s3, s8
-; GFX9-NEXT: s_lshl_b32 s3, s6, s8
-; GFX9-NEXT: s_lshr_b32 s1, s1, s8
-; GFX9-NEXT: s_bfe_u32 s5, s2, 0x100000
-; GFX9-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s5, s3
-; GFX9-NEXT: s_cselect_b32 s3, s5, s3
-; GFX9-NEXT: s_sub_i32 s2, s2, s3
-; GFX9-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX9-NEXT: s_lshl_b32 s3, s4, s8
-; GFX9-NEXT: s_lshl_b32 s4, s7, s8
-; GFX9-NEXT: s_lshr_b32 s2, s2, s8
-; GFX9-NEXT: s_bfe_u32 s5, s3, 0x100000
-; GFX9-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s5, s4
-; GFX9-NEXT: s_cselect_b32 s4, s5, s4
-; GFX9-NEXT: s_sub_i32 s3, s3, s4
-; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: s_and_b32 s1, s1, s4
-; GFX9-NEXT: s_and_b32 s0, s0, s4
-; GFX9-NEXT: s_lshl_b32 s1, s1, 8
-; GFX9-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: s_and_b32 s1, s2, s4
-; GFX9-NEXT: s_lshl_b32 s1, s1, 16
-; GFX9-NEXT: s_lshr_b32 s3, s3, s8
-; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: s_and_b32 s1, s3, s4
-; GFX9-NEXT: s_lshl_b32 s1, s1, 24
-; GFX9-NEXT: s_or_b32 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: s_lshl_b32 s1, s5, s8
+; GFX9-NEXT: s_lshr_b32 s2, s0, 8
+; GFX9-NEXT: s_lshr_b32 s3, s0, 16
+; GFX9-NEXT: s_lshr_b32 s4, s0, 24
+; GFX9-NEXT: s_lshl_b32 s0, s0, s8
+; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-NEXT: s_lshl_b32 s0, s2, s8
+; GFX9-NEXT: s_lshl_b32 s1, s6, s8
+; GFX9-NEXT: v_sub_u16_e64 v1, s0, v1 clamp
+; GFX9-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-NEXT: s_lshl_b32 s0, s3, s8
+; GFX9-NEXT: s_lshl_b32 s1, s7, s8
+; GFX9-NEXT: v_sub_u16_e64 v2, s0, v2 clamp
+; GFX9-NEXT: s_lshl_b32 s0, s4, s8
+; GFX9-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-NEXT: v_sub_u16_e64 v3, s0, v3 clamp
+; GFX9-NEXT: s_movk_i32 s0, 0xff
+; GFX9-NEXT: v_and_b32_sdwa v1, v1, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v1
+; GFX9-NEXT: v_and_b32_sdwa v1, v2, s0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_sdwa v2, v3, s0 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_v4i8:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s6, 8, 0x100000
+; GFX10-NEXT: s_bfe_u32 s5, 8, 0x100000
; GFX10-NEXT: s_lshr_b32 s2, s0, 8
-; GFX10-NEXT: s_lshl_b32 s8, s1, s6
+; GFX10-NEXT: s_lshr_b32 s6, s1, 8
+; GFX10-NEXT: s_lshl_b32 s2, s2, s5
+; GFX10-NEXT: s_lshl_b32 s6, s6, s5
; GFX10-NEXT: s_lshr_b32 s3, s0, 16
+; GFX10-NEXT: v_sub_nc_u16_e64 v1, s2, s6 clamp
; GFX10-NEXT: s_lshr_b32 s4, s0, 24
-; GFX10-NEXT: s_lshl_b32 s0, s0, s6
-; GFX10-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX10-NEXT: s_bfe_u32 s9, s0, 0x100000
-; GFX10-NEXT: s_lshr_b32 s5, s1, 8
-; GFX10-NEXT: s_lshr_b32 s7, s1, 16
+; GFX10-NEXT: s_movk_i32 s2, 0xff
+; GFX10-NEXT: s_lshl_b32 s0, s0, s5
+; GFX10-NEXT: s_lshl_b32 s7, s1, s5
+; GFX10-NEXT: v_and_b32_sdwa v1, v1, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, s7 clamp
+; GFX10-NEXT: s_lshr_b32 s0, s1, 16
; GFX10-NEXT: s_lshr_b32 s1, s1, 24
-; GFX10-NEXT: s_cmp_lt_u32 s9, s8
+; GFX10-NEXT: s_lshl_b32 s3, s3, s5
+; GFX10-NEXT: s_lshl_b32 s0, s0, s5
+; GFX10-NEXT: s_lshl_b32 s4, s4, s5
+; GFX10-NEXT: s_lshl_b32 s1, s1, s5
+; GFX10-NEXT: v_lshrrev_b16_e64 v0, 8, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX10-NEXT: v_sub_nc_u16_e64 v2, s3, s0 clamp
+; GFX10-NEXT: v_sub_nc_u16_e64 v3, s4, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s8, s9, s8
-; GFX10-NEXT: s_lshl_b32 s5, s5, s6
-; GFX10-NEXT: s_sub_i32 s0, s0, s8
-; GFX10-NEXT: s_lshl_b32 s2, s2, s6
-; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX10-NEXT: s_bfe_u32 s8, s2, 0x100000
-; GFX10-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX10-NEXT: s_lshr_b32 s0, s0, s6
-; GFX10-NEXT: s_cmp_lt_u32 s8, s5
-; GFX10-NEXT: s_cselect_b32 s5, s8, s5
-; GFX10-NEXT: s_lshl_b32 s3, s3, s6
-; GFX10-NEXT: s_sub_i32 s2, s2, s5
-; GFX10-NEXT: s_lshl_b32 s5, s7, s6
-; GFX10-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX10-NEXT: s_bfe_u32 s7, s3, 0x100000
-; GFX10-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX10-NEXT: s_lshr_b32 s2, s2, s6
-; GFX10-NEXT: s_cmp_lt_u32 s7, s5
-; GFX10-NEXT: s_cselect_b32 s5, s7, s5
-; GFX10-NEXT: s_lshl_b32 s1, s1, s6
-; GFX10-NEXT: s_sub_i32 s3, s3, s5
-; GFX10-NEXT: s_lshl_b32 s4, s4, s6
-; GFX10-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX10-NEXT: s_bfe_u32 s5, s4, 0x100000
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: s_lshr_b32 s3, s3, s6
-; GFX10-NEXT: s_cmp_lt_u32 s5, s1
-; GFX10-NEXT: s_cselect_b32 s1, s5, s1
-; GFX10-NEXT: s_sub_i32 s1, s4, s1
-; GFX10-NEXT: s_movk_i32 s4, 0xff
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: s_and_b32 s2, s2, s4
-; GFX10-NEXT: s_lshr_b32 s1, s1, s6
-; GFX10-NEXT: s_and_b32 s0, s0, s4
-; GFX10-NEXT: s_lshl_b32 s2, s2, 8
-; GFX10-NEXT: s_and_b32 s3, s3, s4
-; GFX10-NEXT: s_and_b32 s1, s1, s4
-; GFX10-NEXT: s_or_b32 s0, s0, s2
-; GFX10-NEXT: s_lshl_b32 s2, s3, 16
-; GFX10-NEXT: s_lshl_b32 s1, s1, 24
-; GFX10-NEXT: s_or_b32 s0, s0, s2
-; GFX10-NEXT: s_or_b32 s0, s0, s1
+; GFX10-NEXT: v_and_or_b32 v0, v0, s2, v1
+; GFX10-NEXT: v_and_b32_sdwa v1, v2, s2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_and_b32_sdwa v2, v3, s2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
@@ -811,8 +666,7 @@ define i24 @v_usubsat_i24(i24 %lhs, i24 %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX8-NEXT: v_min_u32_e32 v1, v0, v1
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
+; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v1 clamp
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -821,8 +675,7 @@ define i24 @v_usubsat_i24(i24 %lhs, i24 %rhs) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX9-NEXT: v_min_u32_e32 v1, v0, v1
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_sub_u32_e64 v0, v0, v1 clamp
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -833,8 +686,7 @@ define i24 @v_usubsat_i24(i24 %lhs, i24 %rhs) {
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_min_u32_e32 v1, v0, v1
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v1 clamp
; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.usub.sat.i24(i24 %lhs, i24 %rhs)
@@ -854,22 +706,22 @@ define amdgpu_ps i24 @s_usubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
;
; GFX8-LABEL: s_usubsat_i24:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_lshl_b32 s0, s0, 8
; GFX8-NEXT: s_lshl_b32 s1, s1, 8
-; GFX8-NEXT: s_cmp_lt_u32 s0, s1
-; GFX8-NEXT: s_cselect_b32 s1, s0, s1
-; GFX8-NEXT: s_sub_i32 s0, s0, s1
-; GFX8-NEXT: s_lshr_b32 s0, s0, 8
+; GFX8-NEXT: s_lshl_b32 s0, s0, 8
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v0
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_i24:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshl_b32 s0, s0, 8
; GFX9-NEXT: s_lshl_b32 s1, s1, 8
-; GFX9-NEXT: s_cmp_lt_u32 s0, s1
-; GFX9-NEXT: s_cselect_b32 s1, s0, s1
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
-; GFX9-NEXT: s_lshr_b32 s0, s0, 8
+; GFX9-NEXT: s_lshl_b32 s0, s0, 8
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v0
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_i24:
@@ -877,10 +729,9 @@ define amdgpu_ps i24 @s_usubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX10-NEXT: s_lshl_b32 s0, s0, 8
; GFX10-NEXT: s_lshl_b32 s1, s1, 8
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cmp_lt_u32 s0, s1
-; GFX10-NEXT: s_cselect_b32 s1, s0, s1
-; GFX10-NEXT: s_sub_i32 s0, s0, s1
-; GFX10-NEXT: s_lshr_b32 s0, s0, 8
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s1 clamp
+; GFX10-NEXT: v_lshrrev_b32_e32 v0, 8, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i24 @llvm.usub.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result
@@ -897,24 +748,21 @@ define i32 @v_usubsat_i32(i32 %lhs, i32 %rhs) {
; GFX8-LABEL: v_usubsat_i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_u32_e32 v1, v0, v1
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
+; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v1 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_usubsat_i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_u32_e32 v1, v0, v1
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_sub_u32_e64 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_usubsat_i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_min_u32_e32 v1, v0, v1
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
@@ -930,24 +778,23 @@ define amdgpu_ps i32 @s_usubsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
;
; GFX8-LABEL: s_usubsat_i32:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_cmp_lt_u32 s0, s1
-; GFX8-NEXT: s_cselect_b32 s1, s0, s1
-; GFX8-NEXT: s_sub_i32 s0, s0, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_lt_u32 s0, s1
-; GFX9-NEXT: s_cselect_b32 s1, s0, s1
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_lt_u32 s0, s1
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s1, s0, s1
-; GFX10-NEXT: s_sub_i32 s0, s0, s1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
@@ -962,21 +809,18 @@ define amdgpu_ps float @usubsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
;
; GFX8-LABEL: usubsat_i32_sv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_min_u32_e32 v0, s0, v0
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0
+; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: usubsat_i32_sv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_min_u32_e32 v0, s0, v0
-; GFX9-NEXT: v_sub_u32_e32 v0, s0, v0
+; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: usubsat_i32_sv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_min_u32_e32 v0, s0, v0
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, v0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
@@ -992,21 +836,18 @@ define amdgpu_ps float @usubsat_i32_vs(i32 %lhs, i32 inreg %rhs) {
;
; GFX8-LABEL: usubsat_i32_vs:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_min_u32_e32 v1, s0, v0
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
+; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], v0, s0 clamp
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: usubsat_i32_vs:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_min_u32_e32 v1, s0, v0
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1
+; GFX9-NEXT: v_sub_u32_e64 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: usubsat_i32_vs:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_min_u32_e32 v1, s0, v0
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, s0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
@@ -1026,30 +867,24 @@ define <2 x i32> @v_usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX8-LABEL: v_usubsat_v2i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_u32_e32 v2, v0, v2
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v2
-; GFX8-NEXT: v_min_u32_e32 v2, v1, v3
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v2
+; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v2 clamp
+; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v3 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_usubsat_v2i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_u32_e32 v2, v0, v2
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v2
-; GFX9-NEXT: v_min_u32_e32 v2, v1, v3
-; GFX9-NEXT: v_sub_u32_e32 v1, v1, v2
+; GFX9-NEXT: v_sub_u32_e64 v0, v0, v2 clamp
+; GFX9-NEXT: v_sub_u32_e64 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_usubsat_v2i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_min_u32_e32 v2, v0, v2
-; GFX10-NEXT: v_min_u32_e32 v3, v1, v3
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v2 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
@@ -1068,33 +903,31 @@ define amdgpu_ps <2 x i32> @s_usubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inre
;
; GFX8-LABEL: s_usubsat_v2i32:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_cmp_lt_u32 s0, s2
-; GFX8-NEXT: s_cselect_b32 s2, s0, s2
-; GFX8-NEXT: s_sub_i32 s0, s0, s2
-; GFX8-NEXT: s_cmp_lt_u32 s1, s3
-; GFX8-NEXT: s_cselect_b32 s2, s1, s3
-; GFX8-NEXT: s_sub_i32 s1, s1, s2
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], s0, v0 clamp
+; GFX8-NEXT: v_sub_u32_e64 v1, s[0:1], s1, v1 clamp
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_v2i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_lt_u32 s0, s2
-; GFX9-NEXT: s_cselect_b32 s2, s0, s2
-; GFX9-NEXT: s_sub_i32 s0, s0, s2
-; GFX9-NEXT: s_cmp_lt_u32 s1, s3
-; GFX9-NEXT: s_cselect_b32 s2, s1, s3
-; GFX9-NEXT: s_sub_i32 s1, s1, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_v2i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_lt_u32 s0, s2
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s2 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s2, s0, s2
-; GFX10-NEXT: s_sub_i32 s0, s0, s2
-; GFX10-NEXT: s_cmp_lt_u32 s1, s3
-; GFX10-NEXT: s_cselect_b32 s2, s1, s3
-; GFX10-NEXT: s_sub_i32 s1, s1, s2
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
@@ -1115,36 +948,27 @@ define <3 x i32> @v_usubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX8-LABEL: v_usubsat_v3i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_u32_e32 v3, v0, v3
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v3
-; GFX8-NEXT: v_min_u32_e32 v3, v1, v4
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v3
-; GFX8-NEXT: v_min_u32_e32 v3, v2, v5
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v3
+; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v3 clamp
+; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v4 clamp
+; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v5 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_usubsat_v3i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_u32_e32 v3, v0, v3
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3
-; GFX9-NEXT: v_min_u32_e32 v3, v1, v4
-; GFX9-NEXT: v_sub_u32_e32 v1, v1, v3
-; GFX9-NEXT: v_min_u32_e32 v3, v2, v5
-; GFX9-NEXT: v_sub_u32_e32 v2, v2, v3
+; GFX9-NEXT: v_sub_u32_e64 v0, v0, v3 clamp
+; GFX9-NEXT: v_sub_u32_e64 v1, v1, v4 clamp
+; GFX9-NEXT: v_sub_u32_e64 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_usubsat_v3i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_min_u32_e32 v3, v0, v3
-; GFX10-NEXT: v_min_u32_e32 v4, v1, v4
-; GFX10-NEXT: v_min_u32_e32 v5, v2, v5
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v3 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v4 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v3
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v4
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
@@ -1166,42 +990,39 @@ define amdgpu_ps <3 x i32> @s_usubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inre
;
; GFX8-LABEL: s_usubsat_v3i32:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_cmp_lt_u32 s0, s3
-; GFX8-NEXT: s_cselect_b32 s3, s0, s3
-; GFX8-NEXT: s_sub_i32 s0, s0, s3
-; GFX8-NEXT: s_cmp_lt_u32 s1, s4
-; GFX8-NEXT: s_cselect_b32 s3, s1, s4
-; GFX8-NEXT: s_sub_i32 s1, s1, s3
-; GFX8-NEXT: s_cmp_lt_u32 s2, s5
-; GFX8-NEXT: s_cselect_b32 s3, s2, s5
-; GFX8-NEXT: s_sub_i32 s2, s2, s3
+; GFX8-NEXT: v_mov_b32_e32 v0, s3
+; GFX8-NEXT: v_mov_b32_e32 v1, s4
+; GFX8-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NEXT: v_sub_u32_e64 v0, s[6:7], s0, v0 clamp
+; GFX8-NEXT: v_sub_u32_e64 v1, s[0:1], s1, v1 clamp
+; GFX8-NEXT: v_sub_u32_e64 v2, s[0:1], s2, v2 clamp
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_v3i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_lt_u32 s0, s3
-; GFX9-NEXT: s_cselect_b32 s3, s0, s3
-; GFX9-NEXT: s_sub_i32 s0, s0, s3
-; GFX9-NEXT: s_cmp_lt_u32 s1, s4
-; GFX9-NEXT: s_cselect_b32 s3, s1, s4
-; GFX9-NEXT: s_sub_i32 s1, s1, s3
-; GFX9-NEXT: s_cmp_lt_u32 s2, s5
-; GFX9-NEXT: s_cselect_b32 s3, s2, s5
-; GFX9-NEXT: s_sub_i32 s2, s2, s3
+; GFX9-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp
+; GFX9-NEXT: v_sub_u32_e64 v2, s2, v2 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_v3i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_lt_u32 s0, s3
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s3 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s4 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v2, s2, s5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s3, s0, s3
-; GFX10-NEXT: s_sub_i32 s0, s0, s3
-; GFX10-NEXT: s_cmp_lt_u32 s1, s4
-; GFX10-NEXT: s_cselect_b32 s3, s1, s4
-; GFX10-NEXT: s_sub_i32 s1, s1, s3
-; GFX10-NEXT: s_cmp_lt_u32 s2, s5
-; GFX10-NEXT: s_cselect_b32 s3, s2, s5
-; GFX10-NEXT: s_sub_i32 s2, s2, s3
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: ; return to shader part epilog
%result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
@@ -1224,42 +1045,30 @@ define <4 x i32> @v_usubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX8-LABEL: v_usubsat_v4i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_u32_e32 v4, v0, v4
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v4
-; GFX8-NEXT: v_min_u32_e32 v4, v1, v5
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v4
-; GFX8-NEXT: v_min_u32_e32 v4, v2, v6
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v4
-; GFX8-NEXT: v_min_u32_e32 v4, v3, v7
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, v3, v4
+; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v4 clamp
+; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v5 clamp
+; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v6 clamp
+; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v3, v7 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_usubsat_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_u32_e32 v4, v0, v4
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v4
-; GFX9-NEXT: v_min_u32_e32 v4, v1, v5
-; GFX9-NEXT: v_sub_u32_e32 v1, v1, v4
-; GFX9-NEXT: v_min_u32_e32 v4, v2, v6
-; GFX9-NEXT: v_sub_u32_e32 v2, v2, v4
-; GFX9-NEXT: v_min_u32_e32 v4, v3, v7
-; GFX9-NEXT: v_sub_u32_e32 v3, v3, v4
+; GFX9-NEXT: v_sub_u32_e64 v0, v0, v4 clamp
+; GFX9-NEXT: v_sub_u32_e64 v1, v1, v5 clamp
+; GFX9-NEXT: v_sub_u32_e64 v2, v2, v6 clamp
+; GFX9-NEXT: v_sub_u32_e64 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_usubsat_v4i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_min_u32_e32 v19, v2, v6
-; GFX10-NEXT: v_min_u32_e32 v11, v0, v4
-; GFX10-NEXT: v_min_u32_e32 v15, v1, v5
-; GFX10-NEXT: v_min_u32_e32 v6, v3, v7
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v4 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v5 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v6 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v3, v3, v7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v19
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v11
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v15
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, v3, v6
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
@@ -1284,51 +1093,47 @@ define amdgpu_ps <4 x i32> @s_usubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inre
;
; GFX8-LABEL: s_usubsat_v4i32:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_cmp_lt_u32 s0, s4
-; GFX8-NEXT: s_cselect_b32 s4, s0, s4
-; GFX8-NEXT: s_sub_i32 s0, s0, s4
-; GFX8-NEXT: s_cmp_lt_u32 s1, s5
-; GFX8-NEXT: s_cselect_b32 s4, s1, s5
-; GFX8-NEXT: s_sub_i32 s1, s1, s4
-; GFX8-NEXT: s_cmp_lt_u32 s2, s6
-; GFX8-NEXT: s_cselect_b32 s4, s2, s6
-; GFX8-NEXT: s_sub_i32 s2, s2, s4
-; GFX8-NEXT: s_cmp_lt_u32 s3, s7
-; GFX8-NEXT: s_cselect_b32 s4, s3, s7
-; GFX8-NEXT: s_sub_i32 s3, s3, s4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_sub_u32_e64 v0, s[8:9], s0, v0 clamp
+; GFX8-NEXT: v_sub_u32_e64 v1, s[0:1], s1, v1 clamp
+; GFX8-NEXT: v_sub_u32_e64 v2, s[0:1], s2, v2 clamp
+; GFX8-NEXT: v_sub_u32_e64 v3, s[0:1], s3, v3 clamp
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
+; GFX8-NEXT: v_readfirstlane_b32 s3, v3
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_v4i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_lt_u32 s0, s4
-; GFX9-NEXT: s_cselect_b32 s4, s0, s4
-; GFX9-NEXT: s_sub_i32 s0, s0, s4
-; GFX9-NEXT: s_cmp_lt_u32 s1, s5
-; GFX9-NEXT: s_cselect_b32 s4, s1, s5
-; GFX9-NEXT: s_sub_i32 s1, s1, s4
-; GFX9-NEXT: s_cmp_lt_u32 s2, s6
-; GFX9-NEXT: s_cselect_b32 s4, s2, s6
-; GFX9-NEXT: s_sub_i32 s2, s2, s4
-; GFX9-NEXT: s_cmp_lt_u32 s3, s7
-; GFX9-NEXT: s_cselect_b32 s4, s3, s7
-; GFX9-NEXT: s_sub_i32 s3, s3, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp
+; GFX9-NEXT: v_sub_u32_e64 v2, s2, v2 clamp
+; GFX9-NEXT: v_sub_u32_e64 v3, s3, v3 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_v4i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_lt_u32 s0, s4
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s4 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s5 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v2, s2, s6 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v3, s3, s7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s4, s0, s4
-; GFX10-NEXT: s_sub_i32 s0, s0, s4
-; GFX10-NEXT: s_cmp_lt_u32 s1, s5
-; GFX10-NEXT: s_cselect_b32 s4, s1, s5
-; GFX10-NEXT: s_sub_i32 s1, s1, s4
-; GFX10-NEXT: s_cmp_lt_u32 s2, s6
-; GFX10-NEXT: s_cselect_b32 s4, s2, s6
-; GFX10-NEXT: s_sub_i32 s2, s2, s4
-; GFX10-NEXT: s_cmp_lt_u32 s3, s7
-; GFX10-NEXT: s_cselect_b32 s4, s3, s7
-; GFX10-NEXT: s_sub_i32 s3, s3, s4
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: ; return to shader part epilog
%result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
@@ -1353,47 +1158,32 @@ define <5 x i32> @v_usubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX8-LABEL: v_usubsat_v5i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_u32_e32 v5, v0, v5
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v5
-; GFX8-NEXT: v_min_u32_e32 v5, v1, v6
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v5
-; GFX8-NEXT: v_min_u32_e32 v5, v2, v7
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v5
-; GFX8-NEXT: v_min_u32_e32 v5, v3, v8
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, v3, v5
-; GFX8-NEXT: v_min_u32_e32 v5, v4, v9
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v5
+; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v5 clamp
+; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v6 clamp
+; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v7 clamp
+; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v3, v8 clamp
+; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v4, v9 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_usubsat_v5i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_u32_e32 v5, v0, v5
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v5
-; GFX9-NEXT: v_min_u32_e32 v5, v1, v6
-; GFX9-NEXT: v_sub_u32_e32 v1, v1, v5
-; GFX9-NEXT: v_min_u32_e32 v5, v2, v7
-; GFX9-NEXT: v_sub_u32_e32 v2, v2, v5
-; GFX9-NEXT: v_min_u32_e32 v5, v3, v8
-; GFX9-NEXT: v_sub_u32_e32 v3, v3, v5
-; GFX9-NEXT: v_min_u32_e32 v5, v4, v9
-; GFX9-NEXT: v_sub_u32_e32 v4, v4, v5
+; GFX9-NEXT: v_sub_u32_e64 v0, v0, v5 clamp
+; GFX9-NEXT: v_sub_u32_e64 v1, v1, v6 clamp
+; GFX9-NEXT: v_sub_u32_e64 v2, v2, v7 clamp
+; GFX9-NEXT: v_sub_u32_e64 v3, v3, v8 clamp
+; GFX9-NEXT: v_sub_u32_e64 v4, v4, v9 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_usubsat_v5i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_min_u32_e32 v5, v0, v5
-; GFX10-NEXT: v_min_u32_e32 v6, v1, v6
-; GFX10-NEXT: v_min_u32_e32 v7, v2, v7
-; GFX10-NEXT: v_min_u32_e32 v8, v3, v8
-; GFX10-NEXT: v_min_u32_e32 v9, v4, v9
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v5
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v6
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v7
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, v3, v8
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v9
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v5 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v6 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v7 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v3, v3, v8 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v4, v4, v9 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
@@ -1422,60 +1212,55 @@ define amdgpu_ps <5 x i32> @s_usubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inre
;
; GFX8-LABEL: s_usubsat_v5i32:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_cmp_lt_u32 s0, s5
-; GFX8-NEXT: s_cselect_b32 s5, s0, s5
-; GFX8-NEXT: s_sub_i32 s0, s0, s5
-; GFX8-NEXT: s_cmp_lt_u32 s1, s6
-; GFX8-NEXT: s_cselect_b32 s5, s1, s6
-; GFX8-NEXT: s_sub_i32 s1, s1, s5
-; GFX8-NEXT: s_cmp_lt_u32 s2, s7
-; GFX8-NEXT: s_cselect_b32 s5, s2, s7
-; GFX8-NEXT: s_sub_i32 s2, s2, s5
-; GFX8-NEXT: s_cmp_lt_u32 s3, s8
-; GFX8-NEXT: s_cselect_b32 s5, s3, s8
-; GFX8-NEXT: s_sub_i32 s3, s3, s5
-; GFX8-NEXT: s_cmp_lt_u32 s4, s9
-; GFX8-NEXT: s_cselect_b32 s5, s4, s9
-; GFX8-NEXT: s_sub_i32 s4, s4, s5
+; GFX8-NEXT: v_mov_b32_e32 v0, s5
+; GFX8-NEXT: v_mov_b32_e32 v1, s6
+; GFX8-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NEXT: v_mov_b32_e32 v3, s8
+; GFX8-NEXT: v_mov_b32_e32 v4, s9
+; GFX8-NEXT: v_sub_u32_e64 v0, s[10:11], s0, v0 clamp
+; GFX8-NEXT: v_sub_u32_e64 v1, s[0:1], s1, v1 clamp
+; GFX8-NEXT: v_sub_u32_e64 v2, s[0:1], s2, v2 clamp
+; GFX8-NEXT: v_sub_u32_e64 v3, s[0:1], s3, v3 clamp
+; GFX8-NEXT: v_sub_u32_e64 v4, s[0:1], s4, v4 clamp
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
+; GFX8-NEXT: v_readfirstlane_b32 s3, v3
+; GFX8-NEXT: v_readfirstlane_b32 s4, v4
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_v5i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_lt_u32 s0, s5
-; GFX9-NEXT: s_cselect_b32 s5, s0, s5
-; GFX9-NEXT: s_sub_i32 s0, s0, s5
-; GFX9-NEXT: s_cmp_lt_u32 s1, s6
-; GFX9-NEXT: s_cselect_b32 s5, s1, s6
-; GFX9-NEXT: s_sub_i32 s1, s1, s5
-; GFX9-NEXT: s_cmp_lt_u32 s2, s7
-; GFX9-NEXT: s_cselect_b32 s5, s2, s7
-; GFX9-NEXT: s_sub_i32 s2, s2, s5
-; GFX9-NEXT: s_cmp_lt_u32 s3, s8
-; GFX9-NEXT: s_cselect_b32 s5, s3, s8
-; GFX9-NEXT: s_sub_i32 s3, s3, s5
-; GFX9-NEXT: s_cmp_lt_u32 s4, s9
-; GFX9-NEXT: s_cselect_b32 s5, s4, s9
-; GFX9-NEXT: s_sub_i32 s4, s4, s5
+; GFX9-NEXT: v_mov_b32_e32 v0, s5
+; GFX9-NEXT: v_mov_b32_e32 v1, s6
+; GFX9-NEXT: v_mov_b32_e32 v2, s7
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
+; GFX9-NEXT: v_mov_b32_e32 v4, s9
+; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp
+; GFX9-NEXT: v_sub_u32_e64 v2, s2, v2 clamp
+; GFX9-NEXT: v_sub_u32_e64 v3, s3, v3 clamp
+; GFX9-NEXT: v_sub_u32_e64 v4, s4, v4 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
+; GFX9-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_v5i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_lt_u32 s0, s5
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s5 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s6 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v2, s2, s7 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v3, s3, s8 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v4, s4, s9 clamp
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10-NEXT: v_readfirstlane_b32 s4, v4
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s5, s0, s5
-; GFX10-NEXT: s_sub_i32 s0, s0, s5
-; GFX10-NEXT: s_cmp_lt_u32 s1, s6
-; GFX10-NEXT: s_cselect_b32 s5, s1, s6
-; GFX10-NEXT: s_sub_i32 s1, s1, s5
-; GFX10-NEXT: s_cmp_lt_u32 s2, s7
-; GFX10-NEXT: s_cselect_b32 s5, s2, s7
-; GFX10-NEXT: s_sub_i32 s2, s2, s5
-; GFX10-NEXT: s_cmp_lt_u32 s3, s8
-; GFX10-NEXT: s_cselect_b32 s5, s3, s8
-; GFX10-NEXT: s_sub_i32 s3, s3, s5
-; GFX10-NEXT: s_cmp_lt_u32 s4, s9
-; GFX10-NEXT: s_cselect_b32 s5, s4, s9
-; GFX10-NEXT: s_sub_i32 s4, s4, s5
; GFX10-NEXT: ; return to shader part epilog
%result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result
@@ -1522,113 +1307,65 @@ define <16 x i32> @v_usubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
; GFX8-LABEL: v_usubsat_v16i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_u32_e32 v16, v0, v16
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v1, v17
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v2, v18
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v3, v19
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, v3, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v4, v20
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v5, v21
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v5, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v6, v22
-; GFX8-NEXT: v_sub_u32_e32 v6, vcc, v6, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v7, v23
-; GFX8-NEXT: v_sub_u32_e32 v7, vcc, v7, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v8, v24
-; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v8, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v9, v25
-; GFX8-NEXT: v_sub_u32_e32 v9, vcc, v9, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v10, v26
-; GFX8-NEXT: v_sub_u32_e32 v10, vcc, v10, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v11, v27
-; GFX8-NEXT: v_sub_u32_e32 v11, vcc, v11, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v12, v28
-; GFX8-NEXT: v_sub_u32_e32 v12, vcc, v12, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v13, v29
-; GFX8-NEXT: v_sub_u32_e32 v13, vcc, v13, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v14, v30
-; GFX8-NEXT: v_sub_u32_e32 v14, vcc, v14, v16
-; GFX8-NEXT: v_min_u32_e32 v16, v15, v31
-; GFX8-NEXT: v_sub_u32_e32 v15, vcc, v15, v16
+; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v16 clamp
+; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v17 clamp
+; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v18 clamp
+; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v3, v19 clamp
+; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v4, v20 clamp
+; GFX8-NEXT: v_sub_u32_e64 v5, s[4:5], v5, v21 clamp
+; GFX8-NEXT: v_sub_u32_e64 v6, s[4:5], v6, v22 clamp
+; GFX8-NEXT: v_sub_u32_e64 v7, s[4:5], v7, v23 clamp
+; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v8, v24 clamp
+; GFX8-NEXT: v_sub_u32_e64 v9, s[4:5], v9, v25 clamp
+; GFX8-NEXT: v_sub_u32_e64 v10, s[4:5], v10, v26 clamp
+; GFX8-NEXT: v_sub_u32_e64 v11, s[4:5], v11, v27 clamp
+; GFX8-NEXT: v_sub_u32_e64 v12, s[4:5], v12, v28 clamp
+; GFX8-NEXT: v_sub_u32_e64 v13, s[4:5], v13, v29 clamp
+; GFX8-NEXT: v_sub_u32_e64 v14, s[4:5], v14, v30 clamp
+; GFX8-NEXT: v_sub_u32_e64 v15, s[4:5], v15, v31 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_usubsat_v16i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_u32_e32 v16, v0, v16
-; GFX9-NEXT: v_sub_u32_e32 v0, v0, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v1, v17
-; GFX9-NEXT: v_sub_u32_e32 v1, v1, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v2, v18
-; GFX9-NEXT: v_sub_u32_e32 v2, v2, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v3, v19
-; GFX9-NEXT: v_sub_u32_e32 v3, v3, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v4, v20
-; GFX9-NEXT: v_sub_u32_e32 v4, v4, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v5, v21
-; GFX9-NEXT: v_sub_u32_e32 v5, v5, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v6, v22
-; GFX9-NEXT: v_sub_u32_e32 v6, v6, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v7, v23
-; GFX9-NEXT: v_sub_u32_e32 v7, v7, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v8, v24
-; GFX9-NEXT: v_sub_u32_e32 v8, v8, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v9, v25
-; GFX9-NEXT: v_sub_u32_e32 v9, v9, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v10, v26
-; GFX9-NEXT: v_sub_u32_e32 v10, v10, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v11, v27
-; GFX9-NEXT: v_sub_u32_e32 v11, v11, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v12, v28
-; GFX9-NEXT: v_sub_u32_e32 v12, v12, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v13, v29
-; GFX9-NEXT: v_sub_u32_e32 v13, v13, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v14, v30
-; GFX9-NEXT: v_sub_u32_e32 v14, v14, v16
-; GFX9-NEXT: v_min_u32_e32 v16, v15, v31
-; GFX9-NEXT: v_sub_u32_e32 v15, v15, v16
+; GFX9-NEXT: v_sub_u32_e64 v0, v0, v16 clamp
+; GFX9-NEXT: v_sub_u32_e64 v1, v1, v17 clamp
+; GFX9-NEXT: v_sub_u32_e64 v2, v2, v18 clamp
+; GFX9-NEXT: v_sub_u32_e64 v3, v3, v19 clamp
+; GFX9-NEXT: v_sub_u32_e64 v4, v4, v20 clamp
+; GFX9-NEXT: v_sub_u32_e64 v5, v5, v21 clamp
+; GFX9-NEXT: v_sub_u32_e64 v6, v6, v22 clamp
+; GFX9-NEXT: v_sub_u32_e64 v7, v7, v23 clamp
+; GFX9-NEXT: v_sub_u32_e64 v8, v8, v24 clamp
+; GFX9-NEXT: v_sub_u32_e64 v9, v9, v25 clamp
+; GFX9-NEXT: v_sub_u32_e64 v10, v10, v26 clamp
+; GFX9-NEXT: v_sub_u32_e64 v11, v11, v27 clamp
+; GFX9-NEXT: v_sub_u32_e64 v12, v12, v28 clamp
+; GFX9-NEXT: v_sub_u32_e64 v13, v13, v29 clamp
+; GFX9-NEXT: v_sub_u32_e64 v14, v14, v30 clamp
+; GFX9-NEXT: v_sub_u32_e64 v15, v15, v31 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_usubsat_v16i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_min_u32_e32 v35, v0, v16
-; GFX10-NEXT: v_min_u32_e32 v16, v1, v17
-; GFX10-NEXT: v_min_u32_e32 v17, v2, v18
-; GFX10-NEXT: v_min_u32_e32 v18, v3, v19
-; GFX10-NEXT: v_min_u32_e32 v19, v4, v20
-; GFX10-NEXT: v_min_u32_e32 v20, v5, v21
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, v1, v16
-; GFX10-NEXT: v_min_u32_e32 v16, v6, v22
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, v2, v17
-; GFX10-NEXT: v_min_u32_e32 v17, v7, v23
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, v3, v18
-; GFX10-NEXT: v_min_u32_e32 v18, v8, v24
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v19
-; GFX10-NEXT: v_min_u32_e32 v19, v9, v25
-; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v20
-; GFX10-NEXT: v_min_u32_e32 v20, v10, v26
-; GFX10-NEXT: v_sub_nc_u32_e32 v6, v6, v16
-; GFX10-NEXT: v_min_u32_e32 v16, v11, v27
-; GFX10-NEXT: v_sub_nc_u32_e32 v7, v7, v17
-; GFX10-NEXT: v_min_u32_e32 v17, v12, v28
-; GFX10-NEXT: v_sub_nc_u32_e32 v8, v8, v18
-; GFX10-NEXT: v_min_u32_e32 v18, v13, v29
-; GFX10-NEXT: v_sub_nc_u32_e32 v9, v9, v19
-; GFX10-NEXT: v_min_u32_e32 v19, v14, v30
-; GFX10-NEXT: v_sub_nc_u32_e32 v10, v10, v20
-; GFX10-NEXT: v_min_u32_e32 v20, v15, v31
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, v0, v35
-; GFX10-NEXT: v_sub_nc_u32_e32 v11, v11, v16
-; GFX10-NEXT: v_sub_nc_u32_e32 v12, v12, v17
-; GFX10-NEXT: v_sub_nc_u32_e32 v13, v13, v18
-; GFX10-NEXT: v_sub_nc_u32_e32 v14, v14, v19
-; GFX10-NEXT: v_sub_nc_u32_e32 v15, v15, v20
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v16 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v17 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v18 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v3, v3, v19 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v4, v4, v20 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v5, v5, v21 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v6, v6, v22 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v7, v7, v23 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v8, v8, v24 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v9, v9, v25 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v10, v10, v26 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v11, v11, v27 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v12, v12, v28 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v13, v13, v29 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v14, v14, v30 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v15, v15, v31 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
@@ -1690,159 +1427,143 @@ define amdgpu_ps <16 x i32> @s_usubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32>
;
; GFX8-LABEL: s_usubsat_v16i32:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_cmp_lt_u32 s0, s16
-; GFX8-NEXT: s_cselect_b32 s16, s0, s16
-; GFX8-NEXT: s_sub_i32 s0, s0, s16
-; GFX8-NEXT: s_cmp_lt_u32 s1, s17
-; GFX8-NEXT: s_cselect_b32 s16, s1, s17
-; GFX8-NEXT: s_sub_i32 s1, s1, s16
-; GFX8-NEXT: s_cmp_lt_u32 s2, s18
-; GFX8-NEXT: s_cselect_b32 s16, s2, s18
-; GFX8-NEXT: s_sub_i32 s2, s2, s16
-; GFX8-NEXT: s_cmp_lt_u32 s3, s19
-; GFX8-NEXT: s_cselect_b32 s16, s3, s19
-; GFX8-NEXT: s_sub_i32 s3, s3, s16
-; GFX8-NEXT: s_cmp_lt_u32 s4, s20
-; GFX8-NEXT: s_cselect_b32 s16, s4, s20
-; GFX8-NEXT: s_sub_i32 s4, s4, s16
-; GFX8-NEXT: s_cmp_lt_u32 s5, s21
-; GFX8-NEXT: s_cselect_b32 s16, s5, s21
-; GFX8-NEXT: s_sub_i32 s5, s5, s16
-; GFX8-NEXT: s_cmp_lt_u32 s6, s22
-; GFX8-NEXT: s_cselect_b32 s16, s6, s22
-; GFX8-NEXT: s_sub_i32 s6, s6, s16
-; GFX8-NEXT: s_cmp_lt_u32 s7, s23
-; GFX8-NEXT: s_cselect_b32 s16, s7, s23
-; GFX8-NEXT: s_sub_i32 s7, s7, s16
-; GFX8-NEXT: s_cmp_lt_u32 s8, s24
-; GFX8-NEXT: s_cselect_b32 s16, s8, s24
-; GFX8-NEXT: s_sub_i32 s8, s8, s16
-; GFX8-NEXT: s_cmp_lt_u32 s9, s25
-; GFX8-NEXT: s_cselect_b32 s16, s9, s25
-; GFX8-NEXT: s_sub_i32 s9, s9, s16
-; GFX8-NEXT: s_cmp_lt_u32 s10, s26
-; GFX8-NEXT: s_cselect_b32 s16, s10, s26
-; GFX8-NEXT: s_sub_i32 s10, s10, s16
-; GFX8-NEXT: s_cmp_lt_u32 s11, s27
-; GFX8-NEXT: s_cselect_b32 s16, s11, s27
-; GFX8-NEXT: s_sub_i32 s11, s11, s16
-; GFX8-NEXT: s_cmp_lt_u32 s12, s28
-; GFX8-NEXT: s_cselect_b32 s16, s12, s28
-; GFX8-NEXT: s_sub_i32 s12, s12, s16
-; GFX8-NEXT: s_cmp_lt_u32 s13, s29
-; GFX8-NEXT: s_cselect_b32 s16, s13, s29
-; GFX8-NEXT: s_sub_i32 s13, s13, s16
-; GFX8-NEXT: s_cmp_lt_u32 s14, s30
-; GFX8-NEXT: s_cselect_b32 s16, s14, s30
-; GFX8-NEXT: s_sub_i32 s14, s14, s16
-; GFX8-NEXT: s_cmp_lt_u32 s15, s31
-; GFX8-NEXT: s_cselect_b32 s16, s15, s31
-; GFX8-NEXT: s_sub_i32 s15, s15, s16
+; GFX8-NEXT: v_mov_b32_e32 v0, s16
+; GFX8-NEXT: v_mov_b32_e32 v1, s17
+; GFX8-NEXT: v_mov_b32_e32 v2, s18
+; GFX8-NEXT: v_mov_b32_e32 v3, s19
+; GFX8-NEXT: v_mov_b32_e32 v4, s20
+; GFX8-NEXT: v_mov_b32_e32 v5, s21
+; GFX8-NEXT: v_mov_b32_e32 v6, s22
+; GFX8-NEXT: v_mov_b32_e32 v7, s23
+; GFX8-NEXT: v_mov_b32_e32 v8, s24
+; GFX8-NEXT: v_mov_b32_e32 v9, s25
+; GFX8-NEXT: v_mov_b32_e32 v10, s26
+; GFX8-NEXT: v_mov_b32_e32 v11, s27
+; GFX8-NEXT: v_mov_b32_e32 v12, s28
+; GFX8-NEXT: v_mov_b32_e32 v13, s29
+; GFX8-NEXT: v_mov_b32_e32 v14, s30
+; GFX8-NEXT: v_mov_b32_e32 v15, s31
+; GFX8-NEXT: v_sub_u32_e64 v0, s[32:33], s0, v0 clamp
+; GFX8-NEXT: v_sub_u32_e64 v1, s[16:17], s1, v1 clamp
+; GFX8-NEXT: v_sub_u32_e64 v2, s[16:17], s2, v2 clamp
+; GFX8-NEXT: v_sub_u32_e64 v3, s[2:3], s3, v3 clamp
+; GFX8-NEXT: v_sub_u32_e64 v4, s[2:3], s4, v4 clamp
+; GFX8-NEXT: v_sub_u32_e64 v5, s[2:3], s5, v5 clamp
+; GFX8-NEXT: v_sub_u32_e64 v6, s[2:3], s6, v6 clamp
+; GFX8-NEXT: v_sub_u32_e64 v7, s[2:3], s7, v7 clamp
+; GFX8-NEXT: v_sub_u32_e64 v8, s[2:3], s8, v8 clamp
+; GFX8-NEXT: v_sub_u32_e64 v9, s[2:3], s9, v9 clamp
+; GFX8-NEXT: v_sub_u32_e64 v10, s[2:3], s10, v10 clamp
+; GFX8-NEXT: v_sub_u32_e64 v11, s[2:3], s11, v11 clamp
+; GFX8-NEXT: v_sub_u32_e64 v12, s[2:3], s12, v12 clamp
+; GFX8-NEXT: v_sub_u32_e64 v13, s[2:3], s13, v13 clamp
+; GFX8-NEXT: v_sub_u32_e64 v14, s[2:3], s14, v14 clamp
+; GFX8-NEXT: v_sub_u32_e64 v15, s[2:3], s15, v15 clamp
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
+; GFX8-NEXT: v_readfirstlane_b32 s3, v3
+; GFX8-NEXT: v_readfirstlane_b32 s4, v4
+; GFX8-NEXT: v_readfirstlane_b32 s5, v5
+; GFX8-NEXT: v_readfirstlane_b32 s6, v6
+; GFX8-NEXT: v_readfirstlane_b32 s7, v7
+; GFX8-NEXT: v_readfirstlane_b32 s8, v8
+; GFX8-NEXT: v_readfirstlane_b32 s9, v9
+; GFX8-NEXT: v_readfirstlane_b32 s10, v10
+; GFX8-NEXT: v_readfirstlane_b32 s11, v11
+; GFX8-NEXT: v_readfirstlane_b32 s12, v12
+; GFX8-NEXT: v_readfirstlane_b32 s13, v13
+; GFX8-NEXT: v_readfirstlane_b32 s14, v14
+; GFX8-NEXT: v_readfirstlane_b32 s15, v15
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_v16i32:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_cmp_lt_u32 s0, s16
-; GFX9-NEXT: s_cselect_b32 s16, s0, s16
-; GFX9-NEXT: s_sub_i32 s0, s0, s16
-; GFX9-NEXT: s_cmp_lt_u32 s1, s17
-; GFX9-NEXT: s_cselect_b32 s16, s1, s17
-; GFX9-NEXT: s_sub_i32 s1, s1, s16
-; GFX9-NEXT: s_cmp_lt_u32 s2, s18
-; GFX9-NEXT: s_cselect_b32 s16, s2, s18
-; GFX9-NEXT: s_sub_i32 s2, s2, s16
-; GFX9-NEXT: s_cmp_lt_u32 s3, s19
-; GFX9-NEXT: s_cselect_b32 s16, s3, s19
-; GFX9-NEXT: s_sub_i32 s3, s3, s16
-; GFX9-NEXT: s_cmp_lt_u32 s4, s20
-; GFX9-NEXT: s_cselect_b32 s16, s4, s20
-; GFX9-NEXT: s_sub_i32 s4, s4, s16
-; GFX9-NEXT: s_cmp_lt_u32 s5, s21
-; GFX9-NEXT: s_cselect_b32 s16, s5, s21
-; GFX9-NEXT: s_sub_i32 s5, s5, s16
-; GFX9-NEXT: s_cmp_lt_u32 s6, s22
-; GFX9-NEXT: s_cselect_b32 s16, s6, s22
-; GFX9-NEXT: s_sub_i32 s6, s6, s16
-; GFX9-NEXT: s_cmp_lt_u32 s7, s23
-; GFX9-NEXT: s_cselect_b32 s16, s7, s23
-; GFX9-NEXT: s_sub_i32 s7, s7, s16
-; GFX9-NEXT: s_cmp_lt_u32 s8, s24
-; GFX9-NEXT: s_cselect_b32 s16, s8, s24
-; GFX9-NEXT: s_sub_i32 s8, s8, s16
-; GFX9-NEXT: s_cmp_lt_u32 s9, s25
-; GFX9-NEXT: s_cselect_b32 s16, s9, s25
-; GFX9-NEXT: s_sub_i32 s9, s9, s16
-; GFX9-NEXT: s_cmp_lt_u32 s10, s26
-; GFX9-NEXT: s_cselect_b32 s16, s10, s26
-; GFX9-NEXT: s_sub_i32 s10, s10, s16
-; GFX9-NEXT: s_cmp_lt_u32 s11, s27
-; GFX9-NEXT: s_cselect_b32 s16, s11, s27
-; GFX9-NEXT: s_sub_i32 s11, s11, s16
-; GFX9-NEXT: s_cmp_lt_u32 s12, s28
-; GFX9-NEXT: s_cselect_b32 s16, s12, s28
-; GFX9-NEXT: s_sub_i32 s12, s12, s16
-; GFX9-NEXT: s_cmp_lt_u32 s13, s29
-; GFX9-NEXT: s_cselect_b32 s16, s13, s29
-; GFX9-NEXT: s_sub_i32 s13, s13, s16
-; GFX9-NEXT: s_cmp_lt_u32 s14, s30
-; GFX9-NEXT: s_cselect_b32 s16, s14, s30
-; GFX9-NEXT: s_sub_i32 s14, s14, s16
-; GFX9-NEXT: s_cmp_lt_u32 s15, s31
-; GFX9-NEXT: s_cselect_b32 s16, s15, s31
-; GFX9-NEXT: s_sub_i32 s15, s15, s16
+; GFX9-NEXT: v_mov_b32_e32 v0, s16
+; GFX9-NEXT: v_mov_b32_e32 v1, s17
+; GFX9-NEXT: v_mov_b32_e32 v2, s18
+; GFX9-NEXT: v_mov_b32_e32 v3, s19
+; GFX9-NEXT: v_mov_b32_e32 v4, s20
+; GFX9-NEXT: v_mov_b32_e32 v5, s21
+; GFX9-NEXT: v_mov_b32_e32 v6, s22
+; GFX9-NEXT: v_mov_b32_e32 v7, s23
+; GFX9-NEXT: v_mov_b32_e32 v8, s24
+; GFX9-NEXT: v_mov_b32_e32 v9, s25
+; GFX9-NEXT: v_mov_b32_e32 v10, s26
+; GFX9-NEXT: v_mov_b32_e32 v11, s27
+; GFX9-NEXT: v_mov_b32_e32 v12, s28
+; GFX9-NEXT: v_mov_b32_e32 v13, s29
+; GFX9-NEXT: v_mov_b32_e32 v14, s30
+; GFX9-NEXT: v_mov_b32_e32 v15, s31
+; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp
+; GFX9-NEXT: v_sub_u32_e64 v2, s2, v2 clamp
+; GFX9-NEXT: v_sub_u32_e64 v3, s3, v3 clamp
+; GFX9-NEXT: v_sub_u32_e64 v4, s4, v4 clamp
+; GFX9-NEXT: v_sub_u32_e64 v5, s5, v5 clamp
+; GFX9-NEXT: v_sub_u32_e64 v6, s6, v6 clamp
+; GFX9-NEXT: v_sub_u32_e64 v7, s7, v7 clamp
+; GFX9-NEXT: v_sub_u32_e64 v8, s8, v8 clamp
+; GFX9-NEXT: v_sub_u32_e64 v9, s9, v9 clamp
+; GFX9-NEXT: v_sub_u32_e64 v10, s10, v10 clamp
+; GFX9-NEXT: v_sub_u32_e64 v11, s11, v11 clamp
+; GFX9-NEXT: v_sub_u32_e64 v12, s12, v12 clamp
+; GFX9-NEXT: v_sub_u32_e64 v13, s13, v13 clamp
+; GFX9-NEXT: v_sub_u32_e64 v14, s14, v14 clamp
+; GFX9-NEXT: v_sub_u32_e64 v15, s15, v15 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
+; GFX9-NEXT: v_readfirstlane_b32 s4, v4
+; GFX9-NEXT: v_readfirstlane_b32 s5, v5
+; GFX9-NEXT: v_readfirstlane_b32 s6, v6
+; GFX9-NEXT: v_readfirstlane_b32 s7, v7
+; GFX9-NEXT: v_readfirstlane_b32 s8, v8
+; GFX9-NEXT: v_readfirstlane_b32 s9, v9
+; GFX9-NEXT: v_readfirstlane_b32 s10, v10
+; GFX9-NEXT: v_readfirstlane_b32 s11, v11
+; GFX9-NEXT: v_readfirstlane_b32 s12, v12
+; GFX9-NEXT: v_readfirstlane_b32 s13, v13
+; GFX9-NEXT: v_readfirstlane_b32 s14, v14
+; GFX9-NEXT: v_readfirstlane_b32 s15, v15
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_v16i32:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_cmp_lt_u32 s0, s16
+; GFX10-NEXT: v_sub_nc_u32_e64 v0, s0, s16 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v1, s1, s17 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v2, s2, s18 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v3, s3, s19 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v4, s4, s20 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v5, s5, s21 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v6, s6, s22 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v7, s7, s23 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v8, s8, s24 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v9, s9, s25 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v10, s10, s26 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v11, s11, s27 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v12, s12, s28 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v13, s13, s29 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v14, s14, s30 clamp
+; GFX10-NEXT: v_sub_nc_u32_e64 v15, s15, s31 clamp
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10-NEXT: v_readfirstlane_b32 s8, v8
+; GFX10-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10-NEXT: v_readfirstlane_b32 s10, v10
+; GFX10-NEXT: v_readfirstlane_b32 s11, v11
+; GFX10-NEXT: v_readfirstlane_b32 s12, v12
+; GFX10-NEXT: v_readfirstlane_b32 s13, v13
+; GFX10-NEXT: v_readfirstlane_b32 s14, v14
+; GFX10-NEXT: v_readfirstlane_b32 s15, v15
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s46, s0, s16
-; GFX10-NEXT: s_sub_i32 s0, s0, s46
-; GFX10-NEXT: s_cmp_lt_u32 s1, s17
-; GFX10-NEXT: s_cselect_b32 s46, s1, s17
-; GFX10-NEXT: s_sub_i32 s1, s1, s46
-; GFX10-NEXT: s_cmp_lt_u32 s2, s18
-; GFX10-NEXT: s_cselect_b32 s16, s2, s18
-; GFX10-NEXT: s_sub_i32 s2, s2, s16
-; GFX10-NEXT: s_cmp_lt_u32 s3, s19
-; GFX10-NEXT: s_cselect_b32 s16, s3, s19
-; GFX10-NEXT: s_sub_i32 s3, s3, s16
-; GFX10-NEXT: s_cmp_lt_u32 s4, s20
-; GFX10-NEXT: s_cselect_b32 s16, s4, s20
-; GFX10-NEXT: s_sub_i32 s4, s4, s16
-; GFX10-NEXT: s_cmp_lt_u32 s5, s21
-; GFX10-NEXT: s_cselect_b32 s16, s5, s21
-; GFX10-NEXT: s_sub_i32 s5, s5, s16
-; GFX10-NEXT: s_cmp_lt_u32 s6, s22
-; GFX10-NEXT: s_cselect_b32 s16, s6, s22
-; GFX10-NEXT: s_sub_i32 s6, s6, s16
-; GFX10-NEXT: s_cmp_lt_u32 s7, s23
-; GFX10-NEXT: s_cselect_b32 s16, s7, s23
-; GFX10-NEXT: s_sub_i32 s7, s7, s16
-; GFX10-NEXT: s_cmp_lt_u32 s8, s24
-; GFX10-NEXT: s_cselect_b32 s16, s8, s24
-; GFX10-NEXT: s_sub_i32 s8, s8, s16
-; GFX10-NEXT: s_cmp_lt_u32 s9, s25
-; GFX10-NEXT: s_cselect_b32 s16, s9, s25
-; GFX10-NEXT: s_sub_i32 s9, s9, s16
-; GFX10-NEXT: s_cmp_lt_u32 s10, s26
-; GFX10-NEXT: s_cselect_b32 s16, s10, s26
-; GFX10-NEXT: s_sub_i32 s10, s10, s16
-; GFX10-NEXT: s_cmp_lt_u32 s11, s27
-; GFX10-NEXT: s_cselect_b32 s16, s11, s27
-; GFX10-NEXT: s_sub_i32 s11, s11, s16
-; GFX10-NEXT: s_cmp_lt_u32 s12, s28
-; GFX10-NEXT: s_cselect_b32 s16, s12, s28
-; GFX10-NEXT: s_sub_i32 s12, s12, s16
-; GFX10-NEXT: s_cmp_lt_u32 s13, s29
-; GFX10-NEXT: s_cselect_b32 s16, s13, s29
-; GFX10-NEXT: s_sub_i32 s13, s13, s16
-; GFX10-NEXT: s_cmp_lt_u32 s14, s30
-; GFX10-NEXT: s_cselect_b32 s16, s14, s30
-; GFX10-NEXT: s_sub_i32 s14, s14, s16
-; GFX10-NEXT: s_cmp_lt_u32 s15, s31
-; GFX10-NEXT: s_cselect_b32 s16, s15, s31
-; GFX10-NEXT: s_sub_i32 s15, s15, s16
; GFX10-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
@@ -1862,24 +1583,21 @@ define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) {
; GFX8-LABEL: v_usubsat_i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_min_u16_e32 v1, v0, v1
-; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_usubsat_i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_min_u16_e32 v1, v0, v1
-; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_usubsat_i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_min_u16_e64 v1, v0, v1
+; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
@@ -1898,30 +1616,23 @@ define amdgpu_ps i16 @s_usubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
;
; GFX8-LABEL: s_usubsat_i16:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_bfe_u32 s2, s0, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s2, s1
-; GFX8-NEXT: s_cselect_b32 s1, s2, s1
-; GFX8-NEXT: s_sub_i32 s0, s0, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_bfe_u32 s2, s0, 0x100000
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: s_cmp_lt_u32 s2, s1
-; GFX9-NEXT: s_cselect_b32 s1, s2, s1
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_bfe_u32 s2, s0, 0x100000
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
+; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cmp_lt_u32 s2, s1
-; GFX10-NEXT: s_cselect_b32 s1, s2, s1
-; GFX10-NEXT: s_sub_i32 s0, s0, s1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
@@ -1939,21 +1650,18 @@ define amdgpu_ps half @usubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
;
; GFX8-LABEL: usubsat_i16_sv:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_min_u16_e32 v0, s0, v0
-; GFX8-NEXT: v_sub_u16_e32 v0, s0, v0
+; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: usubsat_i16_sv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_min_u16_e32 v0, s0, v0
-; GFX9-NEXT: v_sub_u16_e32 v0, s0, v0
+; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: usubsat_i16_sv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_min_u16_e64 v0, s0, v0
+; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, v0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u16_e64 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
@@ -1972,21 +1680,18 @@ define amdgpu_ps half @usubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
;
; GFX8-LABEL: usubsat_i16_vs:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_min_u16_e32 v1, s0, v0
-; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
+; GFX8-NEXT: v_sub_u16_e64 v0, v0, s0 clamp
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: usubsat_i16_vs:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_min_u16_e32 v1, s0, v0
-; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1
+; GFX9-NEXT: v_sub_u16_e64 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: usubsat_i16_vs:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_min_u16_e64 v1, v0, s0
+; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, s0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_sub_nc_u16_e64 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
@@ -2012,28 +1717,25 @@ define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX8-LABEL: v_usubsat_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX8-NEXT: v_min_u16_e32 v3, v0, v1
-; GFX8-NEXT: v_min_u16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_sub_u16_e32 v0, v0, v3
-; GFX8-NEXT: v_sub_u16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_sub_u16_e64 v2, v0, v1 clamp
+; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v1, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_usubsat_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_min_u16 v1, v0, v1
-; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1
+; GFX9-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_usubsat_v2i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_min_u16 v1, v0, v1
+; GFX10-NEXT: v_pk_sub_u16 v0, v0, v1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result
@@ -2065,57 +1767,28 @@ define amdgpu_ps i32 @s_usubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
-; GFX8-NEXT: s_bfe_u32 s4, s0, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s4, s1
-; GFX8-NEXT: s_cselect_b32 s1, s4, s1
-; GFX8-NEXT: s_sub_i32 s0, s0, s1
-; GFX8-NEXT: s_bfe_u32 s1, s2, 0x100000
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s1, s3
-; GFX8-NEXT: s_cselect_b32 s1, s1, s3
-; GFX8-NEXT: s_sub_i32 s1, s2, s1
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_lshl_b32 s1, s1, 16
-; GFX8-NEXT: s_or_b32 s0, s0, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NEXT: v_sub_u16_e64 v1, s2, v1 clamp
+; GFX8-NEXT: v_mov_b32_e32 v2, 16
+; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_v2i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_mov_b32 s3, 0xffff
-; GFX9-NEXT: s_lshr_b32 s5, s1, 16
-; GFX9-NEXT: s_lshr_b32 s2, s0, 16
-; GFX9-NEXT: s_and_b32 s4, s0, s3
-; GFX9-NEXT: s_and_b32 s1, s1, s3
-; GFX9-NEXT: s_cmp_lt_u32 s4, s1
-; GFX9-NEXT: s_cselect_b32 s1, s4, s1
-; GFX9-NEXT: s_cmp_lt_u32 s2, s5
-; GFX9-NEXT: s_cselect_b32 s3, s2, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3
-; GFX9-NEXT: s_lshr_b32 s3, s1, 16
-; GFX9-NEXT: s_sub_i32 s0, s0, s1
-; GFX9-NEXT: s_sub_i32 s1, s2, s3
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1
+; GFX9-NEXT: v_mov_b32_e32 v0, s1
+; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_v2i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_mov_b32 s2, 0xffff
-; GFX10-NEXT: s_lshr_b32 s3, s0, 16
-; GFX10-NEXT: s_and_b32 s4, s0, s2
-; GFX10-NEXT: s_and_b32 s2, s1, s2
-; GFX10-NEXT: s_lshr_b32 s1, s1, 16
-; GFX10-NEXT: s_cmp_lt_u32 s4, s2
+; GFX10-NEXT: v_pk_sub_u16 v0, s0, s1 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s2, s4, s2
-; GFX10-NEXT: s_cmp_lt_u32 s3, s1
-; GFX10-NEXT: s_cselect_b32 s1, s3, s1
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s2, s1
-; GFX10-NEXT: s_lshr_b32 s2, s1, 16
-; GFX10-NEXT: s_sub_i32 s0, s0, s1
-; GFX10-NEXT: s_sub_i32 s1, s3, s2
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to i32
@@ -2146,24 +1819,22 @@ define amdgpu_ps float @usubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v2, s1
-; GFX8-NEXT: v_min_u16_e32 v1, s0, v0
-; GFX8-NEXT: v_min_u16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_sub_u16_e32 v1, s0, v1
-; GFX8-NEXT: v_sub_u16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_sub_u16_e64 v1, s0, v0 clamp
+; GFX8-NEXT: v_sub_u16_sdwa v0, v2, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v2, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: usubsat_v2i16_sv:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_pk_min_u16 v0, s0, v0
-; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0
+; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: usubsat_v2i16_sv:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_min_u16 v0, s0, v0
+; GFX10-NEXT: v_pk_sub_u16 v0, s0, v0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_sub_i16 v0, s0, v0
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
@@ -2192,26 +1863,24 @@ define amdgpu_ps float @usubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
;
; GFX8-LABEL: usubsat_v2i16_vs:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
-; GFX8-NEXT: v_min_u16_e32 v2, s0, v0
-; GFX8-NEXT: v_min_u16_e32 v3, s1, v1
-; GFX8-NEXT: v_sub_u16_e32 v0, v0, v2
-; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: v_sub_u16_e64 v1, v0, s0 clamp
+; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v2, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: usubsat_v2i16_vs:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_pk_min_u16 v1, v0, s0
-; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1
+; GFX9-NEXT: v_pk_sub_u16 v0, v0, s0 clamp
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: usubsat_v2i16_vs:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_pk_min_u16 v1, v0, s0
+; GFX10-NEXT: v_pk_sub_u16 v0, v0, s0 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
@@ -2267,38 +1936,31 @@ define <2 x float> @v_usubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX8-LABEL: v_usubsat_v4i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX8-NEXT: v_min_u16_e32 v6, v0, v2
-; GFX8-NEXT: v_min_u16_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX8-NEXT: v_min_u16_e32 v7, v1, v3
-; GFX8-NEXT: v_min_u16_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_sub_u16_e32 v0, v0, v6
-; GFX8-NEXT: v_sub_u16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_sub_u16_e32 v1, v1, v7
-; GFX8-NEXT: v_sub_u16_sdwa v2, v5, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_sub_u16_e64 v4, v0, v2 clamp
+; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_sub_u16_e64 v2, v1, v3 clamp
+; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v3 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v3, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_usubsat_v4i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_min_u16 v2, v0, v2
-; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2
-; GFX9-NEXT: v_pk_min_u16 v2, v1, v3
-; GFX9-NEXT: v_pk_sub_i16 v1, v1, v2
+; GFX9-NEXT: v_pk_sub_u16 v0, v0, v2 clamp
+; GFX9-NEXT: v_pk_sub_u16 v1, v1, v3 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_usubsat_v4i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_min_u16 v2, v0, v2
-; GFX10-NEXT: v_pk_min_u16 v3, v1, v3
+; GFX10-NEXT: v_pk_sub_u16 v0, v0, v2 clamp
+; GFX10-NEXT: v_pk_sub_u16 v1, v1, v3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, v2
-; GFX10-NEXT: v_pk_sub_i16 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x float>
@@ -2346,100 +2008,43 @@ define amdgpu_ps <2 x i32> @s_usubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inre
; GFX8-LABEL: s_usubsat_v4i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s6, s2, 16
+; GFX8-NEXT: s_lshr_b32 s7, s3, 16
; GFX8-NEXT: s_lshr_b32 s4, s0, 16
+; GFX8-NEXT: v_mov_b32_e32 v1, s6
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: s_lshr_b32 s5, s1, 16
-; GFX8-NEXT: s_lshr_b32 s7, s3, 16
-; GFX8-NEXT: s_bfe_u32 s8, s0, 0x100000
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s8, s2
-; GFX8-NEXT: s_cselect_b32 s2, s8, s2
-; GFX8-NEXT: s_sub_i32 s0, s0, s2
-; GFX8-NEXT: s_bfe_u32 s2, s4, 0x100000
-; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s2, s6
-; GFX8-NEXT: s_cselect_b32 s2, s2, s6
-; GFX8-NEXT: s_sub_i32 s2, s4, s2
-; GFX8-NEXT: s_bfe_u32 s4, s1, 0x100000
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s4, s3
-; GFX8-NEXT: s_cselect_b32 s3, s4, s3
-; GFX8-NEXT: s_sub_i32 s1, s1, s3
-; GFX8-NEXT: s_bfe_u32 s3, s5, 0x100000
-; GFX8-NEXT: s_bfe_u32 s4, s7, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s3, s4
-; GFX8-NEXT: s_cselect_b32 s3, s3, s4
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_sub_i32 s3, s5, s3
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_lshl_b32 s2, s2, 16
-; GFX8-NEXT: s_or_b32 s0, s0, s2
-; GFX8-NEXT: s_bfe_u32 s2, s3, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_lshl_b32 s2, s2, 16
-; GFX8-NEXT: s_or_b32 s1, s1, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_sub_u16_e64 v1, s4, v1 clamp
+; GFX8-NEXT: v_mov_b32_e32 v4, 16
+; GFX8-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_sub_u16_e64 v3, s5, v3 clamp
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_sub_u16_e64 v2, s1, v2 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_v4i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_mov_b32 s5, 0xffff
-; GFX9-NEXT: s_lshr_b32 s7, s2, 16
-; GFX9-NEXT: s_lshr_b32 s4, s0, 16
-; GFX9-NEXT: s_and_b32 s6, s0, s5
-; GFX9-NEXT: s_and_b32 s2, s2, s5
-; GFX9-NEXT: s_cmp_lt_u32 s6, s2
-; GFX9-NEXT: s_cselect_b32 s2, s6, s2
-; GFX9-NEXT: s_cmp_lt_u32 s4, s7
-; GFX9-NEXT: s_cselect_b32 s6, s4, s7
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s6
-; GFX9-NEXT: s_lshr_b32 s6, s2, 16
-; GFX9-NEXT: s_sub_i32 s0, s0, s2
-; GFX9-NEXT: s_sub_i32 s2, s4, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX9-NEXT: s_lshr_b32 s6, s3, 16
-; GFX9-NEXT: s_lshr_b32 s2, s1, 16
-; GFX9-NEXT: s_and_b32 s4, s1, s5
-; GFX9-NEXT: s_and_b32 s3, s3, s5
-; GFX9-NEXT: s_cmp_lt_u32 s4, s3
-; GFX9-NEXT: s_cselect_b32 s3, s4, s3
-; GFX9-NEXT: s_cmp_lt_u32 s2, s6
-; GFX9-NEXT: s_cselect_b32 s4, s2, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4
-; GFX9-NEXT: s_lshr_b32 s4, s3, 16
-; GFX9-NEXT: s_sub_i32 s1, s1, s3
-; GFX9-NEXT: s_sub_i32 s2, s2, s4
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2
+; GFX9-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp
+; GFX9-NEXT: v_pk_sub_u16 v1, s1, v1 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_v4i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_mov_b32 s4, 0xffff
-; GFX10-NEXT: s_lshr_b32 s5, s0, 16
-; GFX10-NEXT: s_and_b32 s7, s2, s4
-; GFX10-NEXT: s_and_b32 s6, s0, s4
-; GFX10-NEXT: s_lshr_b32 s2, s2, 16
-; GFX10-NEXT: s_cmp_lt_u32 s6, s7
+; GFX10-NEXT: v_pk_sub_u16 v0, s0, s2 clamp
+; GFX10-NEXT: v_pk_sub_u16 v1, s1, s3 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s6, s6, s7
-; GFX10-NEXT: s_cmp_lt_u32 s5, s2
-; GFX10-NEXT: s_cselect_b32 s2, s5, s2
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s6, s2
-; GFX10-NEXT: s_lshr_b32 s6, s2, 16
-; GFX10-NEXT: s_sub_i32 s0, s0, s2
-; GFX10-NEXT: s_sub_i32 s2, s5, s6
-; GFX10-NEXT: s_and_b32 s6, s1, s4
-; GFX10-NEXT: s_and_b32 s4, s3, s4
-; GFX10-NEXT: s_lshr_b32 s5, s1, 16
-; GFX10-NEXT: s_lshr_b32 s3, s3, 16
-; GFX10-NEXT: s_cmp_lt_u32 s6, s4
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
-; GFX10-NEXT: s_cselect_b32 s4, s6, s4
-; GFX10-NEXT: s_cmp_lt_u32 s5, s3
-; GFX10-NEXT: s_cselect_b32 s3, s5, s3
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s4, s3
-; GFX10-NEXT: s_lshr_b32 s4, s3, 16
-; GFX10-NEXT: s_sub_i32 s1, s1, s3
-; GFX10-NEXT: s_sub_i32 s3, s5, s4
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x i32>
@@ -2509,48 +2114,38 @@ define <3 x float> @v_usubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX8-LABEL: v_usubsat_v6i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX8-NEXT: v_min_u16_e32 v9, v0, v3
-; GFX8-NEXT: v_min_u16_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX8-NEXT: v_min_u16_e32 v10, v1, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX8-NEXT: v_min_u16_sdwa v4, v7, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_sub_u16_e32 v0, v0, v9
-; GFX8-NEXT: v_sub_u16_sdwa v3, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_min_u16_e32 v11, v2, v5
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
-; GFX8-NEXT: v_min_u16_sdwa v5, v8, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_sub_u16_e32 v1, v1, v10
-; GFX8-NEXT: v_sub_u16_sdwa v3, v7, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX8-NEXT: v_sub_u16_e32 v2, v2, v11
-; GFX8-NEXT: v_sub_u16_sdwa v3, v8, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX8-NEXT: v_sub_u16_e64 v6, v0, v3 clamp
+; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v3 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_sub_u16_e64 v3, v1, v4 clamp
+; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v4 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_sub_u16_e64 v4, v2, v5 clamp
+; GFX8-NEXT: v_sub_u16_sdwa v2, v2, v5 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v5, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v3, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_usubsat_v6i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_min_u16 v3, v0, v3
-; GFX9-NEXT: v_pk_sub_i16 v0, v0, v3
-; GFX9-NEXT: v_pk_min_u16 v3, v1, v4
-; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3
-; GFX9-NEXT: v_pk_min_u16 v3, v2, v5
-; GFX9-NEXT: v_pk_sub_i16 v2, v2, v3
+; GFX9-NEXT: v_pk_sub_u16 v0, v0, v3 clamp
+; GFX9-NEXT: v_pk_sub_u16 v1, v1, v4 clamp
+; GFX9-NEXT: v_pk_sub_u16 v2, v2, v5 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_usubsat_v6i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_min_u16 v3, v0, v3
-; GFX10-NEXT: v_pk_min_u16 v4, v1, v4
-; GFX10-NEXT: v_pk_min_u16 v5, v2, v5
+; GFX10-NEXT: v_pk_sub_u16 v0, v0, v3 clamp
+; GFX10-NEXT: v_pk_sub_u16 v1, v1, v4 clamp
+; GFX10-NEXT: v_pk_sub_u16 v2, v2, v5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, v3
-; GFX10-NEXT: v_pk_sub_i16 v1, v1, v4
-; GFX10-NEXT: v_pk_sub_i16 v2, v2, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x i16> @llvm.usub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x float>
@@ -2614,142 +2209,57 @@ define amdgpu_ps <3 x i32> @s_usubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inre
; GFX8-LABEL: s_usubsat_v6i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s9, s3, 16
+; GFX8-NEXT: s_lshr_b32 s10, s4, 16
; GFX8-NEXT: s_lshr_b32 s6, s0, 16
+; GFX8-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NEXT: v_mov_b32_e32 v0, s3
+; GFX8-NEXT: s_lshr_b32 s11, s5, 16
; GFX8-NEXT: s_lshr_b32 s7, s1, 16
+; GFX8-NEXT: v_mov_b32_e32 v3, s10
+; GFX8-NEXT: v_sub_u16_e64 v1, s6, v1 clamp
+; GFX8-NEXT: v_mov_b32_e32 v6, 16
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_lshr_b32 s8, s2, 16
-; GFX8-NEXT: s_lshr_b32 s10, s4, 16
-; GFX8-NEXT: s_lshr_b32 s11, s5, 16
-; GFX8-NEXT: s_bfe_u32 s12, s0, 0x100000
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s12, s3
-; GFX8-NEXT: s_cselect_b32 s3, s12, s3
-; GFX8-NEXT: s_sub_i32 s0, s0, s3
-; GFX8-NEXT: s_bfe_u32 s3, s6, 0x100000
-; GFX8-NEXT: s_bfe_u32 s9, s9, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s3, s9
-; GFX8-NEXT: s_cselect_b32 s3, s3, s9
-; GFX8-NEXT: s_sub_i32 s3, s6, s3
-; GFX8-NEXT: s_bfe_u32 s6, s1, 0x100000
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s6, s4
-; GFX8-NEXT: s_cselect_b32 s4, s6, s4
-; GFX8-NEXT: s_sub_i32 s1, s1, s4
-; GFX8-NEXT: s_bfe_u32 s4, s7, 0x100000
-; GFX8-NEXT: s_bfe_u32 s6, s10, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s4, s6
-; GFX8-NEXT: s_cselect_b32 s4, s4, s6
-; GFX8-NEXT: s_sub_i32 s4, s7, s4
-; GFX8-NEXT: s_bfe_u32 s6, s2, 0x100000
-; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s6, s5
-; GFX8-NEXT: s_cselect_b32 s5, s6, s5
-; GFX8-NEXT: s_sub_i32 s2, s2, s5
-; GFX8-NEXT: s_bfe_u32 s5, s8, 0x100000
-; GFX8-NEXT: s_bfe_u32 s6, s11, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s5, s6
-; GFX8-NEXT: s_cselect_b32 s5, s5, s6
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_lshl_b32 s3, s3, 16
-; GFX8-NEXT: s_or_b32 s0, s0, s3
-; GFX8-NEXT: s_bfe_u32 s3, s4, 0x100000
-; GFX8-NEXT: s_sub_i32 s5, s8, s5
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_lshl_b32 s3, s3, 16
-; GFX8-NEXT: s_or_b32 s1, s1, s3
-; GFX8-NEXT: s_bfe_u32 s3, s5, 0x100000
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_lshl_b32 s3, s3, 16
-; GFX8-NEXT: s_or_b32 s2, s2, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s11
+; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_sub_u16_e64 v3, s7, v3 clamp
+; GFX8-NEXT: v_mov_b32_e32 v4, s5
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_sub_u16_e64 v2, s1, v2 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_sub_u16_e64 v5, s8, v5 clamp
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_sub_u16_e64 v4, s2, v4 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_v6i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_mov_b32 s7, 0xffff
-; GFX9-NEXT: s_lshr_b32 s9, s3, 16
-; GFX9-NEXT: s_lshr_b32 s6, s0, 16
-; GFX9-NEXT: s_and_b32 s8, s0, s7
-; GFX9-NEXT: s_and_b32 s3, s3, s7
-; GFX9-NEXT: s_cmp_lt_u32 s8, s3
-; GFX9-NEXT: s_cselect_b32 s3, s8, s3
-; GFX9-NEXT: s_cmp_lt_u32 s6, s9
-; GFX9-NEXT: s_cselect_b32 s8, s6, s9
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s8
-; GFX9-NEXT: s_lshr_b32 s8, s3, 16
-; GFX9-NEXT: s_sub_i32 s0, s0, s3
-; GFX9-NEXT: s_sub_i32 s3, s6, s8
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s3
-; GFX9-NEXT: s_lshr_b32 s8, s4, 16
-; GFX9-NEXT: s_lshr_b32 s3, s1, 16
-; GFX9-NEXT: s_and_b32 s6, s1, s7
-; GFX9-NEXT: s_and_b32 s4, s4, s7
-; GFX9-NEXT: s_cmp_lt_u32 s6, s4
-; GFX9-NEXT: s_cselect_b32 s4, s6, s4
-; GFX9-NEXT: s_cmp_lt_u32 s3, s8
-; GFX9-NEXT: s_cselect_b32 s6, s3, s8
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s6
-; GFX9-NEXT: s_lshr_b32 s6, s4, 16
-; GFX9-NEXT: s_sub_i32 s1, s1, s4
-; GFX9-NEXT: s_sub_i32 s3, s3, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3
-; GFX9-NEXT: s_lshr_b32 s6, s5, 16
-; GFX9-NEXT: s_lshr_b32 s3, s2, 16
-; GFX9-NEXT: s_and_b32 s4, s2, s7
-; GFX9-NEXT: s_and_b32 s5, s5, s7
-; GFX9-NEXT: s_cmp_lt_u32 s4, s5
-; GFX9-NEXT: s_cselect_b32 s4, s4, s5
-; GFX9-NEXT: s_cmp_lt_u32 s3, s6
-; GFX9-NEXT: s_cselect_b32 s5, s3, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: s_lshr_b32 s5, s4, 16
-; GFX9-NEXT: s_sub_i32 s2, s2, s4
-; GFX9-NEXT: s_sub_i32 s3, s3, s5
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s3
+; GFX9-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp
+; GFX9-NEXT: v_pk_sub_u16 v1, s1, v1 clamp
+; GFX9-NEXT: v_pk_sub_u16 v2, s2, v2 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_v6i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_mov_b32 s6, 0xffff
-; GFX10-NEXT: s_lshr_b32 s7, s0, 16
-; GFX10-NEXT: s_and_b32 s9, s3, s6
-; GFX10-NEXT: s_and_b32 s8, s0, s6
-; GFX10-NEXT: s_lshr_b32 s3, s3, 16
-; GFX10-NEXT: s_cmp_lt_u32 s8, s9
+; GFX10-NEXT: v_pk_sub_u16 v0, s0, s3 clamp
+; GFX10-NEXT: v_pk_sub_u16 v1, s1, s4 clamp
+; GFX10-NEXT: v_pk_sub_u16 v2, s2, s5 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s8, s8, s9
-; GFX10-NEXT: s_cmp_lt_u32 s7, s3
-; GFX10-NEXT: s_cselect_b32 s3, s7, s3
-; GFX10-NEXT: s_and_b32 s9, s4, s6
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s8, s3
-; GFX10-NEXT: s_lshr_b32 s4, s4, 16
-; GFX10-NEXT: s_lshr_b32 s8, s3, 16
-; GFX10-NEXT: s_sub_i32 s0, s0, s3
-; GFX10-NEXT: s_sub_i32 s3, s7, s8
-; GFX10-NEXT: s_and_b32 s8, s1, s6
-; GFX10-NEXT: s_lshr_b32 s7, s1, 16
-; GFX10-NEXT: s_cmp_lt_u32 s8, s9
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s3
-; GFX10-NEXT: s_cselect_b32 s8, s8, s9
-; GFX10-NEXT: s_cmp_lt_u32 s7, s4
-; GFX10-NEXT: s_cselect_b32 s4, s7, s4
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s8, s4
-; GFX10-NEXT: s_lshr_b32 s8, s4, 16
-; GFX10-NEXT: s_sub_i32 s1, s1, s4
-; GFX10-NEXT: s_sub_i32 s4, s7, s8
-; GFX10-NEXT: s_and_b32 s8, s2, s6
-; GFX10-NEXT: s_and_b32 s6, s5, s6
-; GFX10-NEXT: s_lshr_b32 s7, s2, 16
-; GFX10-NEXT: s_lshr_b32 s5, s5, 16
-; GFX10-NEXT: s_cmp_lt_u32 s8, s6
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s4
-; GFX10-NEXT: s_cselect_b32 s6, s8, s6
-; GFX10-NEXT: s_cmp_lt_u32 s7, s5
-; GFX10-NEXT: s_cselect_b32 s5, s7, s5
-; GFX10-NEXT: s_pack_ll_b32_b16 s5, s6, s5
-; GFX10-NEXT: s_lshr_b32 s3, s5, 16
-; GFX10-NEXT: s_sub_i32 s2, s2, s5
-; GFX10-NEXT: s_sub_i32 s3, s7, s3
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s3
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: ; return to shader part epilog
%result = call <6 x i16> @llvm.usub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x i32>
@@ -2822,58 +2332,44 @@ define <4 x float> @v_usubsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX8-LABEL: v_usubsat_v8i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX8-NEXT: v_min_u16_e32 v12, v0, v4
-; GFX8-NEXT: v_min_u16_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX8-NEXT: v_min_u16_e32 v13, v1, v5
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX8-NEXT: v_min_u16_sdwa v5, v9, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_sub_u16_e32 v0, v0, v12
-; GFX8-NEXT: v_sub_u16_sdwa v4, v8, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_min_u16_e32 v14, v2, v6
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v3
-; GFX8-NEXT: v_min_u16_sdwa v6, v10, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_sub_u16_e32 v1, v1, v13
-; GFX8-NEXT: v_sub_u16_sdwa v4, v9, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_min_u16_e32 v15, v3, v7
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX8-NEXT: v_min_u16_sdwa v7, v11, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_sub_u16_e32 v2, v2, v14
-; GFX8-NEXT: v_sub_u16_sdwa v4, v10, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
-; GFX8-NEXT: v_sub_u16_e32 v3, v3, v15
-; GFX8-NEXT: v_sub_u16_sdwa v4, v11, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX8-NEXT: v_sub_u16_e64 v8, v0, v4 clamp
+; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v4 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_sub_u16_e64 v4, v1, v5 clamp
+; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v5 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_sub_u16_e64 v5, v2, v6 clamp
+; GFX8-NEXT: v_sub_u16_sdwa v2, v2, v6 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_sub_u16_e64 v6, v3, v7 clamp
+; GFX8-NEXT: v_sub_u16_sdwa v3, v3, v7 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v7, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v7, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_mov_b32_e32 v7, 16
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v0, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_usubsat_v8i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_pk_min_u16 v4, v0, v4
-; GFX9-NEXT: v_pk_sub_i16 v0, v0, v4
-; GFX9-NEXT: v_pk_min_u16 v4, v1, v5
-; GFX9-NEXT: v_pk_sub_i16 v1, v1, v4
-; GFX9-NEXT: v_pk_min_u16 v4, v2, v6
-; GFX9-NEXT: v_pk_sub_i16 v2, v2, v4
-; GFX9-NEXT: v_pk_min_u16 v4, v3, v7
-; GFX9-NEXT: v_pk_sub_i16 v3, v3, v4
+; GFX9-NEXT: v_pk_sub_u16 v0, v0, v4 clamp
+; GFX9-NEXT: v_pk_sub_u16 v1, v1, v5 clamp
+; GFX9-NEXT: v_pk_sub_u16 v2, v2, v6 clamp
+; GFX9-NEXT: v_pk_sub_u16 v3, v3, v7 clamp
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_usubsat_v8i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_pk_min_u16 v19, v2, v6
-; GFX10-NEXT: v_pk_min_u16 v11, v0, v4
-; GFX10-NEXT: v_pk_min_u16 v15, v1, v5
-; GFX10-NEXT: v_pk_min_u16 v6, v3, v7
+; GFX10-NEXT: v_pk_sub_u16 v0, v0, v4 clamp
+; GFX10-NEXT: v_pk_sub_u16 v1, v1, v5 clamp
+; GFX10-NEXT: v_pk_sub_u16 v2, v2, v6 clamp
+; GFX10-NEXT: v_pk_sub_u16 v3, v3, v7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: v_pk_sub_i16 v2, v2, v19
-; GFX10-NEXT: v_pk_sub_i16 v0, v0, v11
-; GFX10-NEXT: v_pk_sub_i16 v1, v1, v15
-; GFX10-NEXT: v_pk_sub_i16 v3, v3, v6
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x float>
@@ -2953,184 +2449,71 @@ define amdgpu_ps <4 x i32> @s_usubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inre
; GFX8-LABEL: s_usubsat_v8i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s12, s4, 16
+; GFX8-NEXT: s_lshr_b32 s13, s5, 16
; GFX8-NEXT: s_lshr_b32 s8, s0, 16
+; GFX8-NEXT: v_mov_b32_e32 v1, s12
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: s_lshr_b32 s14, s6, 16
+; GFX8-NEXT: s_lshr_b32 s15, s7, 16
; GFX8-NEXT: s_lshr_b32 s9, s1, 16
+; GFX8-NEXT: v_mov_b32_e32 v3, s13
+; GFX8-NEXT: v_sub_u16_e64 v1, s8, v1 clamp
+; GFX8-NEXT: v_mov_b32_e32 v8, 16
+; GFX8-NEXT: v_mov_b32_e32 v2, s5
; GFX8-NEXT: s_lshr_b32 s10, s2, 16
+; GFX8-NEXT: v_mov_b32_e32 v5, s14
; GFX8-NEXT: s_lshr_b32 s11, s3, 16
-; GFX8-NEXT: s_lshr_b32 s13, s5, 16
-; GFX8-NEXT: s_lshr_b32 s14, s6, 16
-; GFX8-NEXT: s_lshr_b32 s15, s7, 16
-; GFX8-NEXT: s_bfe_u32 s16, s0, 0x100000
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s16, s4
-; GFX8-NEXT: s_cselect_b32 s4, s16, s4
-; GFX8-NEXT: s_sub_i32 s0, s0, s4
-; GFX8-NEXT: s_bfe_u32 s4, s8, 0x100000
-; GFX8-NEXT: s_bfe_u32 s12, s12, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s4, s12
-; GFX8-NEXT: s_cselect_b32 s4, s4, s12
-; GFX8-NEXT: s_sub_i32 s4, s8, s4
-; GFX8-NEXT: s_bfe_u32 s8, s1, 0x100000
-; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s8, s5
-; GFX8-NEXT: s_cselect_b32 s5, s8, s5
-; GFX8-NEXT: s_sub_i32 s1, s1, s5
-; GFX8-NEXT: s_bfe_u32 s5, s9, 0x100000
-; GFX8-NEXT: s_bfe_u32 s8, s13, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s5, s8
-; GFX8-NEXT: s_cselect_b32 s5, s5, s8
-; GFX8-NEXT: s_sub_i32 s5, s9, s5
-; GFX8-NEXT: s_bfe_u32 s8, s2, 0x100000
-; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s8, s6
-; GFX8-NEXT: s_cselect_b32 s6, s8, s6
-; GFX8-NEXT: s_sub_i32 s2, s2, s6
-; GFX8-NEXT: s_bfe_u32 s6, s10, 0x100000
-; GFX8-NEXT: s_bfe_u32 s8, s14, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s6, s8
-; GFX8-NEXT: s_cselect_b32 s6, s6, s8
-; GFX8-NEXT: s_sub_i32 s6, s10, s6
-; GFX8-NEXT: s_bfe_u32 s8, s3, 0x100000
-; GFX8-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s8, s7
-; GFX8-NEXT: s_cselect_b32 s7, s8, s7
-; GFX8-NEXT: s_sub_i32 s3, s3, s7
-; GFX8-NEXT: s_bfe_u32 s7, s11, 0x100000
-; GFX8-NEXT: s_bfe_u32 s8, s15, 0x100000
-; GFX8-NEXT: s_cmp_lt_u32 s7, s8
-; GFX8-NEXT: s_cselect_b32 s7, s7, s8
-; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
-; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT: s_lshl_b32 s4, s4, 16
-; GFX8-NEXT: s_or_b32 s0, s0, s4
-; GFX8-NEXT: s_bfe_u32 s4, s5, 0x100000
-; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX8-NEXT: s_lshl_b32 s4, s4, 16
-; GFX8-NEXT: s_or_b32 s1, s1, s4
-; GFX8-NEXT: s_bfe_u32 s4, s6, 0x100000
-; GFX8-NEXT: s_sub_i32 s7, s11, s7
-; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX8-NEXT: s_lshl_b32 s4, s4, 16
-; GFX8-NEXT: s_or_b32 s2, s2, s4
-; GFX8-NEXT: s_bfe_u32 s4, s7, 0x100000
-; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX8-NEXT: s_lshl_b32 s4, s4, 16
-; GFX8-NEXT: s_or_b32 s3, s3, s4
+; GFX8-NEXT: v_mov_b32_e32 v7, s15
+; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_sub_u16_e64 v3, s9, v3 clamp
+; GFX8-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NEXT: v_mov_b32_e32 v6, s7
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_sub_u16_e64 v2, s1, v2 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_sub_u16_e64 v7, s11, v7 clamp
+; GFX8-NEXT: v_sub_u16_e64 v5, s10, v5 clamp
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_sub_u16_e64 v4, s2, v4 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v8, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_sub_u16_e64 v6, s3, v6 clamp
+; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
+; GFX8-NEXT: v_readfirstlane_b32 s2, v2
+; GFX8-NEXT: v_readfirstlane_b32 s3, v3
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_usubsat_v8i16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_mov_b32 s9, 0xffff
-; GFX9-NEXT: s_lshr_b32 s11, s4, 16
-; GFX9-NEXT: s_lshr_b32 s8, s0, 16
-; GFX9-NEXT: s_and_b32 s10, s0, s9
-; GFX9-NEXT: s_and_b32 s4, s4, s9
-; GFX9-NEXT: s_cmp_lt_u32 s10, s4
-; GFX9-NEXT: s_cselect_b32 s4, s10, s4
-; GFX9-NEXT: s_cmp_lt_u32 s8, s11
-; GFX9-NEXT: s_cselect_b32 s10, s8, s11
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s10
-; GFX9-NEXT: s_lshr_b32 s10, s4, 16
-; GFX9-NEXT: s_sub_i32 s0, s0, s4
-; GFX9-NEXT: s_sub_i32 s4, s8, s10
-; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4
-; GFX9-NEXT: s_lshr_b32 s10, s5, 16
-; GFX9-NEXT: s_lshr_b32 s4, s1, 16
-; GFX9-NEXT: s_and_b32 s8, s1, s9
-; GFX9-NEXT: s_and_b32 s5, s5, s9
-; GFX9-NEXT: s_cmp_lt_u32 s8, s5
-; GFX9-NEXT: s_cselect_b32 s5, s8, s5
-; GFX9-NEXT: s_cmp_lt_u32 s4, s10
-; GFX9-NEXT: s_cselect_b32 s8, s4, s10
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s8
-; GFX9-NEXT: s_lshr_b32 s8, s5, 16
-; GFX9-NEXT: s_sub_i32 s1, s1, s5
-; GFX9-NEXT: s_sub_i32 s4, s4, s8
-; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4
-; GFX9-NEXT: s_lshr_b32 s8, s6, 16
-; GFX9-NEXT: s_lshr_b32 s4, s2, 16
-; GFX9-NEXT: s_and_b32 s5, s2, s9
-; GFX9-NEXT: s_and_b32 s6, s6, s9
-; GFX9-NEXT: s_cmp_lt_u32 s5, s6
-; GFX9-NEXT: s_cselect_b32 s5, s5, s6
-; GFX9-NEXT: s_cmp_lt_u32 s4, s8
-; GFX9-NEXT: s_cselect_b32 s6, s4, s8
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s6
-; GFX9-NEXT: s_lshr_b32 s6, s5, 16
-; GFX9-NEXT: s_sub_i32 s2, s2, s5
-; GFX9-NEXT: s_sub_i32 s4, s4, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4
-; GFX9-NEXT: s_lshr_b32 s6, s7, 16
-; GFX9-NEXT: s_lshr_b32 s4, s3, 16
-; GFX9-NEXT: s_and_b32 s5, s3, s9
-; GFX9-NEXT: s_and_b32 s7, s7, s9
-; GFX9-NEXT: s_cmp_lt_u32 s5, s7
-; GFX9-NEXT: s_cselect_b32 s5, s5, s7
-; GFX9-NEXT: s_cmp_lt_u32 s4, s6
-; GFX9-NEXT: s_cselect_b32 s6, s4, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s6
-; GFX9-NEXT: s_lshr_b32 s6, s5, 16
-; GFX9-NEXT: s_sub_i32 s3, s3, s5
-; GFX9-NEXT: s_sub_i32 s4, s4, s6
-; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4
+; GFX9-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp
+; GFX9-NEXT: v_pk_sub_u16 v1, s1, v1 clamp
+; GFX9-NEXT: v_pk_sub_u16 v2, s2, v2 clamp
+; GFX9-NEXT: v_pk_sub_u16 v3, s3, v3 clamp
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
+; GFX9-NEXT: v_readfirstlane_b32 s2, v2
+; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_usubsat_v8i16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_mov_b32 s8, 0xffff
-; GFX10-NEXT: s_lshr_b32 s9, s0, 16
-; GFX10-NEXT: s_and_b32 s11, s4, s8
-; GFX10-NEXT: s_and_b32 s10, s0, s8
-; GFX10-NEXT: s_lshr_b32 s4, s4, 16
-; GFX10-NEXT: s_cmp_lt_u32 s10, s11
+; GFX10-NEXT: v_pk_sub_u16 v0, s0, s4 clamp
+; GFX10-NEXT: v_pk_sub_u16 v1, s1, s5 clamp
+; GFX10-NEXT: v_pk_sub_u16 v2, s2, s6 clamp
+; GFX10-NEXT: v_pk_sub_u16 v3, s3, s7 clamp
; GFX10-NEXT: ; implicit-def: $vcc_hi
-; GFX10-NEXT: s_cselect_b32 s10, s10, s11
-; GFX10-NEXT: s_cmp_lt_u32 s9, s4
-; GFX10-NEXT: s_cselect_b32 s4, s9, s4
-; GFX10-NEXT: s_and_b32 s11, s5, s8
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s10, s4
-; GFX10-NEXT: s_lshr_b32 s5, s5, 16
-; GFX10-NEXT: s_lshr_b32 s10, s4, 16
-; GFX10-NEXT: s_sub_i32 s0, s0, s4
-; GFX10-NEXT: s_sub_i32 s4, s9, s10
-; GFX10-NEXT: s_and_b32 s10, s1, s8
-; GFX10-NEXT: s_lshr_b32 s9, s1, 16
-; GFX10-NEXT: s_cmp_lt_u32 s10, s11
-; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4
-; GFX10-NEXT: s_cselect_b32 s10, s10, s11
-; GFX10-NEXT: s_cmp_lt_u32 s9, s5
-; GFX10-NEXT: s_cselect_b32 s5, s9, s5
-; GFX10-NEXT: s_and_b32 s11, s6, s8
-; GFX10-NEXT: s_pack_ll_b32_b16 s5, s10, s5
-; GFX10-NEXT: s_lshr_b32 s6, s6, 16
-; GFX10-NEXT: s_lshr_b32 s10, s5, 16
-; GFX10-NEXT: s_sub_i32 s1, s1, s5
-; GFX10-NEXT: s_sub_i32 s5, s9, s10
-; GFX10-NEXT: s_and_b32 s10, s2, s8
-; GFX10-NEXT: s_lshr_b32 s9, s2, 16
-; GFX10-NEXT: s_cmp_lt_u32 s10, s11
-; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5
-; GFX10-NEXT: s_cselect_b32 s10, s10, s11
-; GFX10-NEXT: s_cmp_lt_u32 s9, s6
-; GFX10-NEXT: s_cselect_b32 s6, s9, s6
-; GFX10-NEXT: s_pack_ll_b32_b16 s6, s10, s6
-; GFX10-NEXT: s_lshr_b32 s10, s6, 16
-; GFX10-NEXT: s_sub_i32 s2, s2, s6
-; GFX10-NEXT: s_sub_i32 s6, s9, s10
-; GFX10-NEXT: s_and_b32 s10, s3, s8
-; GFX10-NEXT: s_and_b32 s8, s7, s8
-; GFX10-NEXT: s_lshr_b32 s9, s3, 16
-; GFX10-NEXT: s_lshr_b32 s7, s7, 16
-; GFX10-NEXT: s_cmp_lt_u32 s10, s8
-; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s6
-; GFX10-NEXT: s_cselect_b32 s8, s10, s8
-; GFX10-NEXT: s_cmp_lt_u32 s9, s7
-; GFX10-NEXT: s_cselect_b32 s7, s9, s7
-; GFX10-NEXT: s_pack_ll_b32_b16 s4, s8, s7
-; GFX10-NEXT: s_lshr_b32 s5, s4, 16
-; GFX10-NEXT: s_sub_i32 s3, s3, s4
-; GFX10-NEXT: s_sub_i32 s4, s9, s5
-; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s4
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: ; return to shader part epilog
%result = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x i32>
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