[PATCH] D84332: [DAGCombiner] Fold sext_inreg of a masked load into a signed extended masked load

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:11136
+    if (ExtVT == Ld->getMemoryVT() && N0.hasOneUse() &&
+        Ld->getExtensionType() != ISD::LoadExtType::SEXTLOAD &&
+        TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, ExtVT)) {
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Hmm. One last thing... If the extension type is a SEXTLOAD, should we be removing the sign_ext_inreg anyway?
I guess with NON_EXTLOAD the ExtVT and MemoryVT would not match?


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Comment at: llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs -tail-predication=enabled -o - %s | FileCheck %s
+
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You likely don't need -tail-predication=enabled any more.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84332/new/

https://reviews.llvm.org/D84332