[llvm] f5e1ec8 - [AArch64] fjcvtzs,rmif,cfinv,setf* all clobber nzcv
Jon Roelofs via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 27 08:18:15 PDT 2020
Author: Jon Roelofs
Date: 2020-07-27T09:17:53-06:00
New Revision: f5e1ec8c5804ab7bd36f9acd43124b2029fbabc4
URL: https://github.com/llvm/llvm-project/commit/f5e1ec8c5804ab7bd36f9acd43124b2029fbabc4
DIFF: https://github.com/llvm/llvm-project/commit/f5e1ec8c5804ab7bd36f9acd43124b2029fbabc4.diff
LOG: [AArch64] fjcvtzs,rmif,cfinv,setf* all clobber nzcv
Differential Revision: https://reviews.llvm.org/D83818
Added:
llvm/test/CodeGen/AArch64/cfinv-def-nzcv.mir
llvm/test/CodeGen/AArch64/cfinv-use-nzcv.mir
llvm/test/CodeGen/AArch64/fjcvtzs.mir
llvm/test/CodeGen/AArch64/rmif-def-nzcv.mir
llvm/test/CodeGen/AArch64/rmif-use-nzcv.mir
llvm/test/CodeGen/AArch64/setf16-def-nzcv.mir
llvm/test/CodeGen/AArch64/setf16-use-nzcv.mir
llvm/test/CodeGen/AArch64/setf8-def-nzcv.mir
llvm/test/CodeGen/AArch64/setf8-use-nzcv.mir
Modified:
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 4f4ba692c2db..e2403c5f6347 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1942,6 +1942,7 @@ class BaseFlagManipulation<bit sf, bit sz, dag iops, string asm, string ops>
: I<(outs), iops, asm, ops, "", []>,
Sched<[WriteI, ReadI, ReadI]> {
let Uses = [NZCV];
+ let Defs = [NZCV];
bits<5> Rn;
let Inst{31} = sf;
let Inst{30-15} = 0b0111010000000000;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index d4e984754d0e..9ea497838b63 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1030,7 +1030,7 @@ let Predicates = [HasPA] in {
}
// v8.3a floating point conversion for javascript
-let Predicates = [HasJS, HasFPARMv8] in
+let Predicates = [HasJS, HasFPARMv8], Defs = [NZCV] in
def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
"fjcvtzs",
[(set GPR32:$Rd,
@@ -1039,7 +1039,7 @@ def FJCVTZS : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
} // HasJS, HasFPARMv8
// v8.4 Flag manipulation instructions
-let Predicates = [HasFMI] in {
+let Predicates = [HasFMI], Defs = [NZCV], Uses = [NZCV] in {
def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> {
let Inst{20-5} = 0b0000001000000000;
}
diff --git a/llvm/test/CodeGen/AArch64/cfinv-def-nzcv.mir b/llvm/test/CodeGen/AArch64/cfinv-def-nzcv.mir
new file mode 100644
index 000000000000..cfcda7de52c5
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/cfinv-def-nzcv.mir
@@ -0,0 +1,17 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+11]]:29: missing implicit register operand 'implicit $nzcv'
+...
+---
+name: test_flags
+liveins:
+ - { reg: '$w0' }
+ - { reg: '$x0' }
+body: |
+ bb.0:
+ liveins: $w0, $x0
+
+ CFINV implicit-def $nzcv
+ RET undef $lr, implicit killed $w0
+
+
diff --git a/llvm/test/CodeGen/AArch64/cfinv-use-nzcv.mir b/llvm/test/CodeGen/AArch64/cfinv-use-nzcv.mir
new file mode 100644
index 000000000000..4e3b3ead7715
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/cfinv-use-nzcv.mir
@@ -0,0 +1,17 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+11]]:25: missing implicit register operand 'implicit-def $nzcv'
+...
+---
+name: test_flags
+liveins:
+ - { reg: '$w0' }
+ - { reg: '$x0' }
+body: |
+ bb.0:
+ liveins: $w0, $x0
+
+ CFINV implicit $nzcv
+ RET undef $lr, implicit killed $w0
+
+
diff --git a/llvm/test/CodeGen/AArch64/fjcvtzs.mir b/llvm/test/CodeGen/AArch64/fjcvtzs.mir
new file mode 100644
index 000000000000..efdee63669e2
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fjcvtzs.mir
@@ -0,0 +1,17 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -mattr=+jsconv -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+11]]:49: missing implicit register operand 'implicit-def $nzcv'
+
+...
+---
+name: test_jcvt
+liveins:
+ - { reg: '$d0' }
+body: |
+ bb.0:
+ liveins: $d0
+
+ renamable $w0 = FJCVTZS killed renamable $d0
+ RET undef $lr, implicit killed $w0
+
+...
diff --git a/llvm/test/CodeGen/AArch64/rmif-def-nzcv.mir b/llvm/test/CodeGen/AArch64/rmif-def-nzcv.mir
new file mode 100644
index 000000000000..1d0903d1af8a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/rmif-def-nzcv.mir
@@ -0,0 +1,16 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+10]]:49: missing implicit register operand 'implicit $nzcv'
+...
+---
+name: test_flags
+liveins:
+ - { reg: '$x0' }
+body: |
+ bb.0:
+ liveins: $x0
+
+ RMIF renamable $x0, 0, 0, implicit-def $nzcv
+ RET undef $lr, implicit killed $w0
+
+
diff --git a/llvm/test/CodeGen/AArch64/rmif-use-nzcv.mir b/llvm/test/CodeGen/AArch64/rmif-use-nzcv.mir
new file mode 100644
index 000000000000..74274a2acb2e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/rmif-use-nzcv.mir
@@ -0,0 +1,16 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+10]]:45: missing implicit register operand 'implicit-def $nzcv'
+...
+---
+name: test_flags
+liveins:
+ - { reg: '$x0' }
+body: |
+ bb.0:
+ liveins: $x0
+
+ RMIF renamable $x0, 0, 0, implicit $nzcv
+ RET undef $lr, implicit killed $w0
+
+
diff --git a/llvm/test/CodeGen/AArch64/setf16-def-nzcv.mir b/llvm/test/CodeGen/AArch64/setf16-def-nzcv.mir
new file mode 100644
index 000000000000..e828ddad68e1
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/setf16-def-nzcv.mir
@@ -0,0 +1,16 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+10]]:45: missing implicit register operand 'implicit $nzcv'
+...
+---
+name: test_flags
+liveins:
+ - { reg: '$w0' }
+body: |
+ bb.0:
+ liveins: $w0
+
+ SETF16 renamable $w0, implicit-def $nzcv
+ RET undef $lr, implicit killed $w0
+
+
diff --git a/llvm/test/CodeGen/AArch64/setf16-use-nzcv.mir b/llvm/test/CodeGen/AArch64/setf16-use-nzcv.mir
new file mode 100644
index 000000000000..7f2c5606f2e8
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/setf16-use-nzcv.mir
@@ -0,0 +1,16 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+10]]:41: missing implicit register operand 'implicit-def $nzcv'
+...
+---
+name: test_flags
+liveins:
+ - { reg: '$w0' }
+body: |
+ bb.0:
+ liveins: $w0
+
+ SETF16 renamable $w0, implicit $nzcv
+ RET undef $lr, implicit killed $w0
+
+
diff --git a/llvm/test/CodeGen/AArch64/setf8-def-nzcv.mir b/llvm/test/CodeGen/AArch64/setf8-def-nzcv.mir
new file mode 100644
index 000000000000..d9a9ef00efd5
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/setf8-def-nzcv.mir
@@ -0,0 +1,16 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+10]]:44: missing implicit register operand 'implicit $nzcv'
+...
+---
+name: test_flags
+liveins:
+ - { reg: '$w0' }
+body: |
+ bb.0:
+ liveins: $w0
+
+ SETF8 renamable $w0, implicit-def $nzcv
+ RET undef $lr, implicit killed $w0
+
+
diff --git a/llvm/test/CodeGen/AArch64/setf8-use-nzcv.mir b/llvm/test/CodeGen/AArch64/setf8-use-nzcv.mir
new file mode 100644
index 000000000000..05d803f7b7b6
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/setf8-use-nzcv.mir
@@ -0,0 +1,16 @@
+# RUN: not llc -o - %s -mtriple=arm64-eabi -run-pass=legalizer 2>&1 | FileCheck %s
+
+# CHECK: [[@LINE+10]]:40: missing implicit register operand 'implicit-def $nzcv'
+...
+---
+name: test_flags
+liveins:
+ - { reg: '$w0' }
+body: |
+ bb.0:
+ liveins: $w0
+
+ SETF8 renamable $w0, implicit $nzcv
+ RET undef $lr, implicit killed $w0
+
+
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