[PATCH] D84654: GlobalISel: Implement lower for G_EXTRACT_VECTOR_ELT

[Matt Arsenault via Phabricator via llvm-commits]

arsenm updated this revision to Diff 280906.
arsenm added a comment.

Fix test source error that should have been caught by the verifier


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84654/new/

https://reviews.llvm.org/D84654

Files:
  llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir


Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
@@ -911,14 +911,11 @@
     ; CHECK: [[PTR_ADD65:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C65]](s32)
     ; CHECK: G_STORE [[UV63]](s32), [[PTR_ADD65]](p5) :: (store 4 into %stack.0 + 252, align 256, addrspace 5)
     ; CHECK: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load 4 from %stack.0 + 28, addrspace 5)
-    ; CHECK: [[PTR_ADD66:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD9]], [[C3]](s32)
-    ; CHECK: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD66]](p5) :: (load 4 from %stack.0 + 32, addrspace 5)
-    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD4]](s32), [[LOAD5]](s32)
-    ; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
+    ; CHECK: S_ENDPGM 0, implicit [[LOAD4]](s32)
     %0:_(p1) = COPY $sgpr0_sgpr1
     %1:_(s32) = G_CONSTANT i32 7
     %2:_(<64 x s32>) = G_LOAD %0 :: (load 256, align 4, addrspace 4)
-    %3:_(s64) = G_EXTRACT_VECTOR_ELT %2, %1
+    %3:_(s32) = G_EXTRACT_VECTOR_ELT %2, %1
     S_ENDPGM 0, implicit %3
 ...
 
@@ -1142,13 +1139,10 @@
     ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[C3]]
     ; CHECK: [[PTR_ADD66:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[MUL]](s32)
     ; CHECK: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD66]](p5) :: (load 4)
-    ; CHECK: [[PTR_ADD67:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD66]], [[C3]](s32)
-    ; CHECK: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD67]](p5) :: (load 4 + 4)
-    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD4]](s32), [[LOAD5]](s32)
-    ; CHECK: S_ENDPGM 0, implicit [[MV]](s64)
+    ; CHECK: S_ENDPGM 0, implicit [[LOAD4]](s32)
     %0:_(p1) = COPY $sgpr0_sgpr1
     %1:_(s32) = COPY $sgpr2
     %2:_(<64 x s32>) = G_LOAD %0 :: (load 256, align 4, addrspace 4)
-    %3:_(s64) = G_EXTRACT_VECTOR_ELT %2, %1
+    %3:_(s32) = G_EXTRACT_VECTOR_ELT %2, %1
     S_ENDPGM 0, implicit %3
 ...


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