[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

[Albion Fung via Phabricator via llvm-commits]

Conanap added a comment.

Addressed formatting comments



================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14156
+
+  // This transformation is only valid if the we are loading either a byte,
+  // halfword, word, or doubleword.
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NeHuang wrote:
> nit: if we are loading either a byte....
I'm not too sure what you mean, would you be able to elaborate?  
The comment is:


> This transformation is only valid if the we are loading either a byte,
> halfword, word, or doubleword.

Thanks!




CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82502/new/

https://reviews.llvm.org/D82502