[PATCH] D81993: [AArch64][GlobalISel] Add post-legalize combine for sext(trunc(sextload)) -> trunc/copy

[Amara Emerson via Phabricator via llvm-commits]

aemerson added a comment.

I reverted this because it turns out that `computeNumSignBits()` doesn't actually do what we need here. Its definition of sign bits are any top-most bits which are known to be identical. Because of that it matches G_ZEXTLOAD with the known zero bits at the top returns as "sign bits". This behavior seems to be consistent with the SDAG KB implementation too.

I committed the original version of this patch in 3b10e42ba1a3ff97346bc51f13195ed9595800f4 <https://reviews.llvm.org/rG3b10e42ba1a3ff97346bc51f13195ed9595800f4>, with the vector bail out added. Let me know if I should change it post commit.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81993/new/

https://reviews.llvm.org/D81993