[llvm] deb4bb2 - [IR] Add min/max/abs intrinsics
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 23 11:56:37 PDT 2020
Author: Nikita Popov
Date: 2020-07-23T20:56:19+02:00
New Revision: deb4bb2b3abd216aceaa109a5304f025a234540f
URL: https://github.com/llvm/llvm-project/commit/deb4bb2b3abd216aceaa109a5304f025a234540f
DIFF: https://github.com/llvm/llvm-project/commit/deb4bb2b3abd216aceaa109a5304f025a234540f.diff
LOG: [IR] Add min/max/abs intrinsics
This adds the llvm.abs(), llvm.umin(), llvm.umax(), llvm.smin(),
and llvm.smax() intrinsics specified in D81829. For SelectionDAG,
the ISD opcodes and all the legalization and lowering already exist,
so this just wires them up to the intrinsic in the SDAG builder and
adds rudimentary tests. For GlobalISel only the min/max intrinsics
are wired up, as llvm.abs() will require the addition of a G_ABS op,
and corresponding legalization support.
Differential Revision: https://reviews.llvm.org/D84125
Added:
llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll
llvm/test/CodeGen/X86/abs.ll
llvm/test/CodeGen/X86/smax.ll
llvm/test/CodeGen/X86/smin.ll
llvm/test/CodeGen/X86/umax.ll
llvm/test/CodeGen/X86/umin.ll
Modified:
llvm/include/llvm/IR/Intrinsics.td
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index 4918ea876df6..0a071464804e 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -1039,6 +1039,25 @@ def int_udiv_fix_sat : Intrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
[IntrNoMem, ImmArg<ArgIndex<2>>]>;
+//===------------------ Integer Min/Max/Abs Intrinsics --------------------===//
+//
+def int_abs : Intrinsic<
+ [llvm_anyint_ty], [LLVMMatchType<0>, llvm_i1_ty],
+ [IntrNoMem, IntrSpeculatable, IntrWillReturn, ImmArg<ArgIndex<1>>]>;
+
+def int_smax : Intrinsic<
+ [llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
+ [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+def int_smin : Intrinsic<
+ [llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
+ [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+def int_umax : Intrinsic<
+ [llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
+ [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+def int_umin : Intrinsic<
+ [llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
+ [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+
//===------------------------- Memory Use Markers -------------------------===//
//
def int_lifetime_start : Intrinsic<[],
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index a5706958b39f..aa898d5a6189 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1486,6 +1486,14 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
return translateBinaryOp(TargetOpcode::G_USUBSAT, CI, MIRBuilder);
case Intrinsic::ssub_sat:
return translateBinaryOp(TargetOpcode::G_SSUBSAT, CI, MIRBuilder);
+ case Intrinsic::umin:
+ return translateBinaryOp(TargetOpcode::G_UMIN, CI, MIRBuilder);
+ case Intrinsic::umax:
+ return translateBinaryOp(TargetOpcode::G_UMAX, CI, MIRBuilder);
+ case Intrinsic::smin:
+ return translateBinaryOp(TargetOpcode::G_SMIN, CI, MIRBuilder);
+ case Intrinsic::smax:
+ return translateBinaryOp(TargetOpcode::G_SMAX, CI, MIRBuilder);
case Intrinsic::fmuladd: {
const TargetMachine &TM = MF->getTarget();
const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 8dadb2833e8d..9d2f64b94df1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -6363,6 +6363,36 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
Op1, Op2, Op3, DAG, TLI));
return;
}
+ case Intrinsic::smax: {
+ SDValue Op1 = getValue(I.getArgOperand(0));
+ SDValue Op2 = getValue(I.getArgOperand(1));
+ setValue(&I, DAG.getNode(ISD::SMAX, sdl, Op1.getValueType(), Op1, Op2));
+ return;
+ }
+ case Intrinsic::smin: {
+ SDValue Op1 = getValue(I.getArgOperand(0));
+ SDValue Op2 = getValue(I.getArgOperand(1));
+ setValue(&I, DAG.getNode(ISD::SMIN, sdl, Op1.getValueType(), Op1, Op2));
+ return;
+ }
+ case Intrinsic::umax: {
+ SDValue Op1 = getValue(I.getArgOperand(0));
+ SDValue Op2 = getValue(I.getArgOperand(1));
+ setValue(&I, DAG.getNode(ISD::UMAX, sdl, Op1.getValueType(), Op1, Op2));
+ return;
+ }
+ case Intrinsic::umin: {
+ SDValue Op1 = getValue(I.getArgOperand(0));
+ SDValue Op2 = getValue(I.getArgOperand(1));
+ setValue(&I, DAG.getNode(ISD::UMIN, sdl, Op1.getValueType(), Op1, Op2));
+ return;
+ }
+ case Intrinsic::abs: {
+ // TODO: Preserve "int min is poison" arg in SDAG?
+ SDValue Op1 = getValue(I.getArgOperand(0));
+ setValue(&I, DAG.getNode(ISD::ABS, sdl, Op1.getValueType(), Op1));
+ return;
+ }
case Intrinsic::stacksave: {
SDValue Op = getRoot();
EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll
new file mode 100644
index 000000000000..0f84f12a1257
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/minmaxabs.ll
@@ -0,0 +1,104 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
+
+declare i32 @llvm.umin.i32(i32, i32)
+declare i32 @llvm.umax.i32(i32, i32)
+declare i32 @llvm.smin.i32(i32, i32)
+declare i32 @llvm.smax.i32(i32, i32)
+
+declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)
+declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)
+
+define i32 @test_umin_i32(i32 %a, i32 %b) {
+; CHECK-LABEL: test_umin_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %r = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+ ret i32 %r
+}
+
+define i32 @test_umax_i32(i32 %a, i32 %b) {
+; CHECK-LABEL: test_umax_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %r = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+ ret i32 %r
+}
+
+define i32 @test_smin_i32(i32 %a, i32 %b) {
+; CHECK-LABEL: test_smin_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_i32_e32 v0, v0, v1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %r = call i32 @llvm.smin.i32(i32 %a, i32 %b)
+ ret i32 %r
+}
+
+define i32 @test_smax_i32(i32 %a, i32 %b) {
+; CHECK-LABEL: test_smax_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v0, v0, v1
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %r = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+ ret i32 %r
+}
+
+define <4 x i32> @test_umin_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_umin_v4i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_u32_e32 v0, v0, v4
+; CHECK-NEXT: v_min_u32_e32 v1, v1, v5
+; CHECK-NEXT: v_min_u32_e32 v2, v2, v6
+; CHECK-NEXT: v_min_u32_e32 v3, v3, v7
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %r = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> %b)
+ ret <4 x i32> %r
+}
+
+define <4 x i32> @test_umax_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_umax_v4i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_u32_e32 v0, v0, v4
+; CHECK-NEXT: v_max_u32_e32 v1, v1, v5
+; CHECK-NEXT: v_max_u32_e32 v2, v2, v6
+; CHECK-NEXT: v_max_u32_e32 v3, v3, v7
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %r = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> %b)
+ ret <4 x i32> %r
+}
+
+define <4 x i32> @test_smin_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_smin_v4i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_min_i32_e32 v0, v0, v4
+; CHECK-NEXT: v_min_i32_e32 v1, v1, v5
+; CHECK-NEXT: v_min_i32_e32 v2, v2, v6
+; CHECK-NEXT: v_min_i32_e32 v3, v3, v7
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %r = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> %b)
+ ret <4 x i32> %r
+}
+
+define <4 x i32> @test_smax_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_smax_v4i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_max_i32_e32 v0, v0, v4
+; CHECK-NEXT: v_max_i32_e32 v1, v1, v5
+; CHECK-NEXT: v_max_i32_e32 v2, v2, v6
+; CHECK-NEXT: v_max_i32_e32 v3, v3, v7
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %r = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> %b)
+ ret <4 x i32> %r
+}
diff --git a/llvm/test/CodeGen/X86/abs.ll b/llvm/test/CodeGen/X86/abs.ll
new file mode 100644
index 000000000000..345830676aba
--- /dev/null
+++ b/llvm/test/CodeGen/X86/abs.ll
@@ -0,0 +1,618 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=X64,SSE
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=avx | FileCheck %s --check-prefixes=X64,AVX,AVX1
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=avx2 | FileCheck %s --check-prefixes=X64,AVX,AVX2
+; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefix=X86
+
+; The i1 parameter is not codegen-relevant right now.
+
+declare i8 @llvm.abs.i8(i8, i1)
+declare i16 @llvm.abs.i16(i16, i1)
+declare i24 @llvm.abs.i24(i24, i1)
+declare i32 @llvm.abs.i32(i32, i1)
+declare i64 @llvm.abs.i64(i64, i1)
+declare i128 @llvm.abs.i128(i128, i1)
+
+declare <1 x i32> @llvm.abs.v1i32(<1 x i32>, i1)
+declare <2 x i32> @llvm.abs.v2i32(<2 x i32>, i1)
+declare <3 x i32> @llvm.abs.v3i32(<3 x i32>, i1)
+declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
+declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1)
+
+declare <8 x i16> @llvm.abs.v8i16(<8 x i16>, i1)
+declare <16 x i8> @llvm.abs.v16i8(<16 x i8>, i1)
+
+define i8 @test_i8(i8 %a) nounwind {
+; X64-LABEL: test_i8:
+; X64: # %bb.0:
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: movl %edi, %ecx
+; X64-NEXT: sarb $7, %cl
+; X64-NEXT: leal (%rdi,%rcx), %eax
+; X64-NEXT: xorb %cl, %al
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i8:
+; X86: # %bb.0:
+; X86-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: sarb $7, %cl
+; X86-NEXT: addb %cl, %al
+; X86-NEXT: xorb %cl, %al
+; X86-NEXT: retl
+ %r = call i8 @llvm.abs.i8(i8 %a, i1 false)
+ ret i8 %r
+}
+
+define i16 @test_i16(i16 %a) nounwind {
+; X64-LABEL: test_i16:
+; X64: # %bb.0:
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: negw %ax
+; X64-NEXT: cmovlw %di, %ax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i16:
+; X86: # %bb.0:
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: negw %ax
+; X86-NEXT: cmovlw %cx, %ax
+; X86-NEXT: retl
+ %r = call i16 @llvm.abs.i16(i16 %a, i1 false)
+ ret i16 %r
+}
+
+define i24 @test_i24(i24 %a) nounwind {
+; X64-LABEL: test_i24:
+; X64: # %bb.0:
+; X64-NEXT: shll $8, %edi
+; X64-NEXT: sarl $8, %edi
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: negl %eax
+; X64-NEXT: cmovll %edi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i24:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: shll $8, %ecx
+; X86-NEXT: sarl $8, %ecx
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: cmovll %ecx, %eax
+; X86-NEXT: retl
+ %r = call i24 @llvm.abs.i24(i24 %a, i1 false)
+ ret i24 %r
+}
+
+define i32 @test_i32(i32 %a) nounwind {
+; X64-LABEL: test_i32:
+; X64: # %bb.0:
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: negl %eax
+; X64-NEXT: cmovll %edi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: cmovll %ecx, %eax
+; X86-NEXT: retl
+ %r = call i32 @llvm.abs.i32(i32 %a, i1 false)
+ ret i32 %r
+}
+
+define i64 @test_i64(i64 %a) nounwind {
+; X64-LABEL: test_i64:
+; X64: # %bb.0:
+; X64-NEXT: movq %rdi, %rax
+; X64-NEXT: negq %rax
+; X64-NEXT: cmovlq %rdi, %rax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i64:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: sarl $31, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: addl %ecx, %eax
+; X86-NEXT: adcl %ecx, %edx
+; X86-NEXT: xorl %ecx, %edx
+; X86-NEXT: xorl %ecx, %eax
+; X86-NEXT: retl
+ %r = call i64 @llvm.abs.i64(i64 %a, i1 false)
+ ret i64 %r
+}
+
+define i128 @test_i128(i128 %a) nounwind {
+; X64-LABEL: test_i128:
+; X64: # %bb.0:
+; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: movq %rdi, %rax
+; X64-NEXT: negq %rax
+; X64-NEXT: sbbq %rsi, %rdx
+; X64-NEXT: testq %rsi, %rsi
+; X64-NEXT: cmovnsq %rdi, %rax
+; X64-NEXT: cmovnsq %rsi, %rdx
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i128:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: xorl %esi, %esi
+; X86-NEXT: negl %edi
+; X86-NEXT: movl $0, %ebx
+; X86-NEXT: sbbl %edx, %ebx
+; X86-NEXT: movl $0, %ebp
+; X86-NEXT: sbbl %ecx, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: sbbl %eax, %esi
+; X86-NEXT: testl %eax, %eax
+; X86-NEXT: cmovnsl %eax, %esi
+; X86-NEXT: cmovnsl %ecx, %ebp
+; X86-NEXT: cmovnsl %edx, %ebx
+; X86-NEXT: cmovnsl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl %edi, (%eax)
+; X86-NEXT: movl %ebx, 4(%eax)
+; X86-NEXT: movl %ebp, 8(%eax)
+; X86-NEXT: movl %esi, 12(%eax)
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call i128 @llvm.abs.i128(i128 %a, i1 false)
+ ret i128 %r
+}
+
+define <1 x i32> @test_v1i32(<1 x i32> %a) nounwind {
+; X64-LABEL: test_v1i32:
+; X64: # %bb.0:
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: negl %eax
+; X64-NEXT: cmovll %edi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_v1i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: cmovll %ecx, %eax
+; X86-NEXT: retl
+ %r = call <1 x i32> @llvm.abs.v1i32(<1 x i32> %a, i1 false)
+ ret <1 x i32> %r
+}
+
+define <2 x i32> @test_v2i32(<2 x i32> %a) nounwind {
+; SSE-LABEL: test_v2i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: psrad $31, %xmm1
+; SSE-NEXT: paddd %xmm1, %xmm0
+; SSE-NEXT: pxor %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v2i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpabsd %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v2i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %edx, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: cmovll %edx, %eax
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: negl %edx
+; X86-NEXT: cmovll %ecx, %edx
+; X86-NEXT: retl
+ %r = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %a, i1 false)
+ ret <2 x i32> %r
+}
+
+define <3 x i32> @test_v3i32(<3 x i32> %a) nounwind {
+; SSE-LABEL: test_v3i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: psrad $31, %xmm1
+; SSE-NEXT: paddd %xmm1, %xmm0
+; SSE-NEXT: pxor %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v3i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpabsd %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v3i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %edx, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: cmovll %edx, %eax
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: negl %edx
+; X86-NEXT: cmovll %ecx, %edx
+; X86-NEXT: movl %esi, %ecx
+; X86-NEXT: negl %ecx
+; X86-NEXT: cmovll %esi, %ecx
+; X86-NEXT: popl %esi
+; X86-NEXT: retl
+ %r = call <3 x i32> @llvm.abs.v3i32(<3 x i32> %a, i1 false)
+ ret <3 x i32> %r
+}
+
+define <4 x i32> @test_v4i32(<4 x i32> %a) nounwind {
+; SSE-LABEL: test_v4i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: psrad $31, %xmm1
+; SSE-NEXT: paddd %xmm1, %xmm0
+; SSE-NEXT: pxor %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v4i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpabsd %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl %edi, %ebx
+; X86-NEXT: negl %ebx
+; X86-NEXT: cmovll %edi, %ebx
+; X86-NEXT: movl %esi, %edi
+; X86-NEXT: negl %edi
+; X86-NEXT: cmovll %esi, %edi
+; X86-NEXT: movl %edx, %esi
+; X86-NEXT: negl %esi
+; X86-NEXT: cmovll %edx, %esi
+; X86-NEXT: movl %ecx, %edx
+; X86-NEXT: negl %edx
+; X86-NEXT: cmovll %ecx, %edx
+; X86-NEXT: movl %edx, 12(%eax)
+; X86-NEXT: movl %esi, 8(%eax)
+; X86-NEXT: movl %edi, 4(%eax)
+; X86-NEXT: movl %ebx, (%eax)
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: retl $4
+ %r = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %a, i1 false)
+ ret <4 x i32> %r
+}
+
+define <8 x i32> @test_v8i32(<8 x i32> %a) nounwind {
+; SSE-LABEL: test_v8i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm0, %xmm2
+; SSE-NEXT: psrad $31, %xmm2
+; SSE-NEXT: paddd %xmm2, %xmm0
+; SSE-NEXT: pxor %xmm2, %xmm0
+; SSE-NEXT: movdqa %xmm1, %xmm2
+; SSE-NEXT: psrad $31, %xmm2
+; SSE-NEXT: paddd %xmm2, %xmm1
+; SSE-NEXT: pxor %xmm2, %xmm1
+; SSE-NEXT: retq
+;
+; AVX1-LABEL: test_v8i32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vpabsd %xmm0, %xmm1
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX1-NEXT: vpabsd %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v8i32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpabsd %ymm0, %ymm0
+; AVX2-NEXT: retq
+;
+; X86-LABEL: test_v8i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $8, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: negl %ecx
+; X86-NEXT: cmovll %edx, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl %ebp, %ecx
+; X86-NEXT: negl %ecx
+; X86-NEXT: cmovll %ebp, %ecx
+; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-NEXT: movl %ebx, %ebp
+; X86-NEXT: negl %ebp
+; X86-NEXT: cmovll %ebx, %ebp
+; X86-NEXT: movl %edi, %ebx
+; X86-NEXT: negl %ebx
+; X86-NEXT: cmovll %edi, %ebx
+; X86-NEXT: movl %esi, %edi
+; X86-NEXT: negl %edi
+; X86-NEXT: cmovll %esi, %edi
+; X86-NEXT: movl %eax, %esi
+; X86-NEXT: negl %esi
+; X86-NEXT: cmovll %eax, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: cmovll %ecx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: negl %ecx
+; X86-NEXT: cmovll %edx, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %ecx, 28(%edx)
+; X86-NEXT: movl %eax, 24(%edx)
+; X86-NEXT: movl %esi, 20(%edx)
+; X86-NEXT: movl %edi, 16(%edx)
+; X86-NEXT: movl %ebx, 12(%edx)
+; X86-NEXT: movl %ebp, 8(%edx)
+; X86-NEXT: movl (%esp), %eax # 4-byte Reload
+; X86-NEXT: movl %eax, 4(%edx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl %eax, (%edx)
+; X86-NEXT: movl %edx, %eax
+; X86-NEXT: addl $8, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %a, i1 false)
+ ret <8 x i32> %r
+}
+
+define <8 x i16> @test_v8i16(<8 x i16> %a) nounwind {
+; SSE-LABEL: test_v8i16:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: psraw $15, %xmm1
+; SSE-NEXT: paddw %xmm1, %xmm0
+; SSE-NEXT: pxor %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v8i16:
+; AVX: # %bb.0:
+; AVX-NEXT: vpabsw %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v8i16:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: pushl %eax
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: negw %cx
+; X86-NEXT: cmovlw %dx, %cx
+; X86-NEXT: movw %cx, {{[-0-9]+}}(%e{{[sb]}}p) # 2-byte Spill
+; X86-NEXT: movl %ebp, %ecx
+; X86-NEXT: negw %cx
+; X86-NEXT: cmovlw %bp, %cx
+; X86-NEXT: movw %cx, (%esp) # 2-byte Spill
+; X86-NEXT: movl %ebx, %ebp
+; X86-NEXT: negw %bp
+; X86-NEXT: cmovlw %bx, %bp
+; X86-NEXT: movl %edi, %ebx
+; X86-NEXT: negw %bx
+; X86-NEXT: cmovlw %di, %bx
+; X86-NEXT: movl %esi, %edi
+; X86-NEXT: negw %di
+; X86-NEXT: cmovlw %si, %di
+; X86-NEXT: movl %eax, %esi
+; X86-NEXT: negw %si
+; X86-NEXT: cmovlw %ax, %si
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: negw %ax
+; X86-NEXT: cmovlw %cx, %ax
+; X86-NEXT: movzwl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: negw %cx
+; X86-NEXT: cmovlw %dx, %cx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movw %cx, 14(%edx)
+; X86-NEXT: movw %ax, 12(%edx)
+; X86-NEXT: movw %si, 10(%edx)
+; X86-NEXT: movw %di, 8(%edx)
+; X86-NEXT: movw %bx, 6(%edx)
+; X86-NEXT: movw %bp, 4(%edx)
+; X86-NEXT: movzwl (%esp), %eax # 2-byte Folded Reload
+; X86-NEXT: movw %ax, 2(%edx)
+; X86-NEXT: movzwl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 2-byte Folded Reload
+; X86-NEXT: movw %ax, (%edx)
+; X86-NEXT: movl %edx, %eax
+; X86-NEXT: addl $4, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %a, i1 false)
+ ret <8 x i16> %r
+}
+
+define <16 x i8> @test_v16i8(<16 x i8> %a) nounwind {
+; SSE-LABEL: test_v16i8:
+; SSE: # %bb.0:
+; SSE-NEXT: pxor %xmm1, %xmm1
+; SSE-NEXT: pcmpgtb %xmm0, %xmm1
+; SSE-NEXT: paddb %xmm1, %xmm0
+; SSE-NEXT: pxor %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v16i8:
+; AVX: # %bb.0:
+; AVX-NEXT: vpabsb %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v16i8:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $12, %esp
+; X86-NEXT: movb {{[0-9]+}}(%esp), %bh
+; X86-NEXT: movb {{[0-9]+}}(%esp), %bl
+; X86-NEXT: movb {{[0-9]+}}(%esp), %dh
+; X86-NEXT: movb {{[0-9]+}}(%esp), %ch
+; X86-NEXT: movb {{[0-9]+}}(%esp), %ah
+; X86-NEXT: movb {{[0-9]+}}(%esp), %dl
+; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
+; X86-NEXT: movb %cl, %al
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %cl
+; X86-NEXT: xorb %al, %cl
+; X86-NEXT: movb %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
+; X86-NEXT: movb %dl, %al
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %dl
+; X86-NEXT: xorb %al, %dl
+; X86-NEXT: movb %dl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
+; X86-NEXT: movb %ah, %al
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %ah
+; X86-NEXT: xorb %al, %ah
+; X86-NEXT: movb %ah, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
+; X86-NEXT: movb %ch, %al
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %ch
+; X86-NEXT: xorb %al, %ch
+; X86-NEXT: movb %ch, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
+; X86-NEXT: movb %dh, %al
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %dh
+; X86-NEXT: xorb %al, %dh
+; X86-NEXT: movb %dh, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
+; X86-NEXT: movl %ebx, %eax
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %bl
+; X86-NEXT: xorb %al, %bl
+; X86-NEXT: movb %bl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
+; X86-NEXT: movb %bh, %al
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %bh
+; X86-NEXT: xorb %al, %bh
+; X86-NEXT: movb %bh, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
+; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %cl
+; X86-NEXT: xorb %al, %cl
+; X86-NEXT: movb %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
+; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %cl
+; X86-NEXT: xorb %al, %cl
+; X86-NEXT: movb %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
+; X86-NEXT: movb {{[0-9]+}}(%esp), %bh
+; X86-NEXT: movb %bh, %al
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %bh
+; X86-NEXT: xorb %al, %bh
+; X86-NEXT: movb {{[0-9]+}}(%esp), %bl
+; X86-NEXT: movl %ebx, %eax
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %bl
+; X86-NEXT: xorb %al, %bl
+; X86-NEXT: movb {{[0-9]+}}(%esp), %dh
+; X86-NEXT: movb %dh, %al
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %dh
+; X86-NEXT: xorb %al, %dh
+; X86-NEXT: movb {{[0-9]+}}(%esp), %ch
+; X86-NEXT: movb %ch, %al
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %ch
+; X86-NEXT: xorb %al, %ch
+; X86-NEXT: movb {{[0-9]+}}(%esp), %dl
+; X86-NEXT: movl %edx, %eax
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %dl
+; X86-NEXT: xorb %al, %dl
+; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: sarb $7, %al
+; X86-NEXT: addb %al, %cl
+; X86-NEXT: xorb %al, %cl
+; X86-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-NEXT: movb %al, %ah
+; X86-NEXT: sarb $7, %ah
+; X86-NEXT: addb %ah, %al
+; X86-NEXT: xorb %ah, %al
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movb %al, 15(%esi)
+; X86-NEXT: movb %cl, 14(%esi)
+; X86-NEXT: movb %dl, 13(%esi)
+; X86-NEXT: movb %ch, 12(%esi)
+; X86-NEXT: movb %dh, 11(%esi)
+; X86-NEXT: movb %bl, 10(%esi)
+; X86-NEXT: movb %bh, 9(%esi)
+; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
+; X86-NEXT: movb %al, 8(%esi)
+; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
+; X86-NEXT: movb %al, 7(%esi)
+; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
+; X86-NEXT: movb %al, 6(%esi)
+; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
+; X86-NEXT: movb %al, 5(%esi)
+; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
+; X86-NEXT: movb %al, 4(%esi)
+; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
+; X86-NEXT: movb %al, 3(%esi)
+; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
+; X86-NEXT: movb %al, 2(%esi)
+; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
+; X86-NEXT: movb %al, 1(%esi)
+; X86-NEXT: movb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Reload
+; X86-NEXT: movb %al, (%esi)
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: addl $12, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %ebx
+; X86-NEXT: retl $4
+ %r = call <16 x i8> @llvm.abs.v16i8(<16 x i8> %a, i1 false)
+ ret <16 x i8> %r
+}
diff --git a/llvm/test/CodeGen/X86/smax.ll b/llvm/test/CodeGen/X86/smax.ll
new file mode 100644
index 000000000000..31d0822f8090
--- /dev/null
+++ b/llvm/test/CodeGen/X86/smax.ll
@@ -0,0 +1,662 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=X64,SSE
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=avx | FileCheck %s --check-prefixes=X64,AVX,AVX1
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=avx2 | FileCheck %s --check-prefixes=X64,AVX,AVX2
+; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefix=X86
+
+declare i8 @llvm.smax.i8(i8, i8)
+declare i16 @llvm.smax.i16(i16, i16)
+declare i24 @llvm.smax.i24(i24, i24)
+declare i32 @llvm.smax.i32(i32, i32)
+declare i64 @llvm.smax.i64(i64, i64)
+declare i128 @llvm.smax.i128(i128, i128)
+
+declare <1 x i32> @llvm.smax.v1i32(<1 x i32>, <1 x i32>)
+declare <2 x i32> @llvm.smax.v2i32(<2 x i32>, <2 x i32>)
+declare <3 x i32> @llvm.smax.v3i32(<3 x i32>, <3 x i32>)
+declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)
+declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>)
+
+declare <8 x i16> @llvm.smax.v8i16(<8 x i16>, <8 x i16>)
+declare <16 x i8> @llvm.smax.v16i8(<16 x i8>, <16 x i8>)
+
+define i8 @test_i8(i8 %a, i8 %b) nounwind {
+; X64-LABEL: test_i8:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpb %al, %dil
+; X64-NEXT: cmovgl %edi, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i8:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpb %al, %cl
+; X86-NEXT: cmovgl %ecx, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: retl
+ %r = call i8 @llvm.smax.i8(i8 %a, i8 %b)
+ ret i8 %r
+}
+
+define i16 @test_i16(i16 %a, i16 %b) nounwind {
+; X64-LABEL: test_i16:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpw %ax, %di
+; X64-NEXT: cmovgl %edi, %eax
+; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i16:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpw %ax, %cx
+; X86-NEXT: cmovgl %ecx, %eax
+; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: retl
+ %r = call i16 @llvm.smax.i16(i16 %a, i16 %b)
+ ret i16 %r
+}
+
+define i24 @test_i24(i24 %a, i24 %b) nounwind {
+; X64-LABEL: test_i24:
+; X64: # %bb.0:
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: shll $8, %esi
+; X64-NEXT: sarl $8, %esi
+; X64-NEXT: shll $8, %eax
+; X64-NEXT: sarl $8, %eax
+; X64-NEXT: cmpl %esi, %eax
+; X64-NEXT: cmovlel %esi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i24:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: shll $8, %ecx
+; X86-NEXT: sarl $8, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: shll $8, %eax
+; X86-NEXT: sarl $8, %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmovlel %ecx, %eax
+; X86-NEXT: retl
+ %r = call i24 @llvm.smax.i24(i24 %a, i24 %b)
+ ret i24 %r
+}
+
+define i32 @test_i32(i32 %a, i32 %b) nounwind {
+; X64-LABEL: test_i32:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpl %esi, %edi
+; X64-NEXT: cmovgl %edi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpl %eax, %ecx
+; X86-NEXT: cmovgl %ecx, %eax
+; X86-NEXT: retl
+ %r = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+ ret i32 %r
+}
+
+define i64 @test_i64(i64 %a, i64 %b) nounwind {
+; X64-LABEL: test_i64:
+; X64: # %bb.0:
+; X64-NEXT: movq %rsi, %rax
+; X64-NEXT: cmpq %rsi, %rdi
+; X64-NEXT: cmovgq %rdi, %rax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i64:
+; X86: # %bb.0:
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cmpl %eax, %ecx
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: cmoval %ecx, %edi
+; X86-NEXT: cmpl %edx, %esi
+; X86-NEXT: cmovgl %ecx, %eax
+; X86-NEXT: cmovel %edi, %eax
+; X86-NEXT: cmovgl %esi, %edx
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: retl
+ %r = call i64 @llvm.smax.i64(i64 %a, i64 %b)
+ ret i64 %r
+}
+
+define i128 @test_i128(i128 %a, i128 %b) nounwind {
+; X64-LABEL: test_i128:
+; X64: # %bb.0:
+; X64-NEXT: movq %rdx, %rax
+; X64-NEXT: cmpq %rdx, %rdi
+; X64-NEXT: cmovaq %rdi, %rdx
+; X64-NEXT: cmpq %rcx, %rsi
+; X64-NEXT: cmovgq %rdi, %rax
+; X64-NEXT: cmoveq %rdx, %rax
+; X64-NEXT: cmovgq %rsi, %rcx
+; X64-NEXT: movq %rcx, %rdx
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i128:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: pushl %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpl %ebx, %edx
+; X86-NEXT: movl %ebx, %eax
+; X86-NEXT: cmoval %edx, %eax
+; X86-NEXT: cmpl %esi, %ecx
+; X86-NEXT: movl %ebx, %ebp
+; X86-NEXT: cmoval %edx, %ebp
+; X86-NEXT: cmovel %eax, %ebp
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: cmoval %ecx, %eax
+; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: sbbl %edi, %ecx
+; X86-NEXT: cmovll {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cmovll {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl %edi, %ecx
+; X86-NEXT: xorl %edx, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: xorl %eax, %edi
+; X86-NEXT: orl %ecx, %edi
+; X86-NEXT: cmovel %ebp, %ebx
+; X86-NEXT: cmovel (%esp), %esi # 4-byte Folded Reload
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: cmpl %eax, %edi
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: cmoval %edi, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: cmpl %edx, %ebp
+; X86-NEXT: cmovgl %edi, %eax
+; X86-NEXT: cmovel %ecx, %eax
+; X86-NEXT: cmovgl %ebp, %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %edx, 12(%ecx)
+; X86-NEXT: movl %eax, 8(%ecx)
+; X86-NEXT: movl %esi, 4(%ecx)
+; X86-NEXT: movl %ebx, (%ecx)
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: addl $4, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call i128 @llvm.smax.i128(i128 %a, i128 %b)
+ ret i128 %r
+}
+
+define <1 x i32> @test_v1i32(<1 x i32> %a, <1 x i32> %b) nounwind {
+; X64-LABEL: test_v1i32:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpl %esi, %edi
+; X64-NEXT: cmovgl %edi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_v1i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpl %eax, %ecx
+; X86-NEXT: cmovgl %ecx, %eax
+; X86-NEXT: retl
+ %r = call <1 x i32> @llvm.smax.v1i32(<1 x i32> %a, <1 x i32> %b)
+ ret <1 x i32> %r
+}
+
+define <2 x i32> @test_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
+; SSE-LABEL: test_v2i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm0, %xmm2
+; SSE-NEXT: pcmpgtd %xmm1, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm0, %xmm2
+; SSE-NEXT: movdqa %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v2i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v2i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cmpl %eax, %esi
+; X86-NEXT: cmovgl %esi, %eax
+; X86-NEXT: cmpl %edx, %ecx
+; X86-NEXT: cmovgl %ecx, %edx
+; X86-NEXT: popl %esi
+; X86-NEXT: retl
+ %r = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %r
+}
+
+define <3 x i32> @test_v3i32(<3 x i32> %a, <3 x i32> %b) nounwind {
+; SSE-LABEL: test_v3i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm0, %xmm2
+; SSE-NEXT: pcmpgtd %xmm1, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm0, %xmm2
+; SSE-NEXT: movdqa %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v3i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v3i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: cmpl %eax, %ebx
+; X86-NEXT: cmovgl %ebx, %eax
+; X86-NEXT: cmpl %edx, %edi
+; X86-NEXT: cmovgl %edi, %edx
+; X86-NEXT: cmpl %ecx, %esi
+; X86-NEXT: cmovgl %esi, %ecx
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: retl
+ %r = call <3 x i32> @llvm.smax.v3i32(<3 x i32> %a, <3 x i32> %b)
+ ret <3 x i32> %r
+}
+
+define <4 x i32> @test_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
+; SSE-LABEL: test_v4i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm0, %xmm2
+; SSE-NEXT: pcmpgtd %xmm1, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm0, %xmm2
+; SSE-NEXT: movdqa %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v4i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edi, %eax
+; X86-NEXT: cmovgl %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %esi, %eax
+; X86-NEXT: cmovgl %eax, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edx, %eax
+; X86-NEXT: cmovgl %eax, %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl %ecx, 12(%eax)
+; X86-NEXT: movl %edx, 8(%eax)
+; X86-NEXT: movl %esi, 4(%eax)
+; X86-NEXT: movl %edi, (%eax)
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: retl $4
+ %r = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> %b)
+ ret <4 x i32> %r
+}
+
+define <8 x i32> @test_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
+; SSE-LABEL: test_v8i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm0, %xmm4
+; SSE-NEXT: pcmpgtd %xmm2, %xmm4
+; SSE-NEXT: pand %xmm4, %xmm0
+; SSE-NEXT: pandn %xmm2, %xmm4
+; SSE-NEXT: por %xmm0, %xmm4
+; SSE-NEXT: movdqa %xmm1, %xmm2
+; SSE-NEXT: pcmpgtd %xmm3, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm1
+; SSE-NEXT: pandn %xmm3, %xmm2
+; SSE-NEXT: por %xmm1, %xmm2
+; SSE-NEXT: movdqa %xmm4, %xmm0
+; SSE-NEXT: movdqa %xmm2, %xmm1
+; SSE-NEXT: retq
+;
+; AVX1-LABEL: test_v8i32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT: vpmaxsd %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v8i32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpmaxsd %ymm1, %ymm0, %ymm0
+; AVX2-NEXT: retq
+;
+; X86-LABEL: test_v8i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $8, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ebp, %eax
+; X86-NEXT: cmovgl %eax, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ebx, %eax
+; X86-NEXT: cmovgl %eax, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edi, %eax
+; X86-NEXT: cmovgl %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %esi, %eax
+; X86-NEXT: cmovgl %eax, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edx, %eax
+; X86-NEXT: cmovgl %eax, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: cmpl %eax, %edx
+; X86-NEXT: cmovgl %edx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %eax, 28(%edx)
+; X86-NEXT: movl %ecx, 24(%edx)
+; X86-NEXT: movl (%esp), %eax # 4-byte Reload
+; X86-NEXT: movl %eax, 20(%edx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl %eax, 16(%edx)
+; X86-NEXT: movl %esi, 12(%edx)
+; X86-NEXT: movl %edi, 8(%edx)
+; X86-NEXT: movl %ebx, 4(%edx)
+; X86-NEXT: movl %ebp, (%edx)
+; X86-NEXT: movl %edx, %eax
+; X86-NEXT: addl $8, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %a, <8 x i32> %b)
+ ret <8 x i32> %r
+}
+
+define <8 x i16> @test_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
+; SSE-LABEL: test_v8i16:
+; SSE: # %bb.0:
+; SSE-NEXT: pmaxsw %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v8i16:
+; AVX: # %bb.0:
+; AVX-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v8i16:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $8, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %bp, %ax
+; X86-NEXT: cmovgl %eax, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %bx, %ax
+; X86-NEXT: cmovgl %eax, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %di, %ax
+; X86-NEXT: cmovgl %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %si, %ax
+; X86-NEXT: cmovgl %eax, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %dx, %ax
+; X86-NEXT: cmovgl %eax, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %cx, %ax
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %dx, %ax
+; X86-NEXT: cmovgl %eax, %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpw %ax, %cx
+; X86-NEXT: cmovgl %ecx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movw %ax, 14(%ecx)
+; X86-NEXT: movw %dx, 12(%ecx)
+; X86-NEXT: movl (%esp), %eax # 4-byte Reload
+; X86-NEXT: movw %ax, 10(%ecx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movw %ax, 8(%ecx)
+; X86-NEXT: movw %si, 6(%ecx)
+; X86-NEXT: movw %di, 4(%ecx)
+; X86-NEXT: movw %bx, 2(%ecx)
+; X86-NEXT: movw %bp, (%ecx)
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: addl $8, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call <8 x i16> @llvm.smax.v8i16(<8 x i16> %a, <8 x i16> %b)
+ ret <8 x i16> %r
+}
+
+define <16 x i8> @test_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
+; SSE-LABEL: test_v16i8:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm0, %xmm2
+; SSE-NEXT: pcmpgtb %xmm1, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm0, %xmm2
+; SSE-NEXT: movdqa %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v16i8:
+; AVX: # %bb.0:
+; AVX-NEXT: vpmaxsb %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v16i8:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $40, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %bl, %al
+; X86-NEXT: cmovgl %eax, %ebx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %dl, %al
+; X86-NEXT: cmovgl %eax, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl %ecx, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl %ecx, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %bl, %al
+; X86-NEXT: cmovgl %eax, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %dl, %al
+; X86-NEXT: cmovgl %eax, %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovgl %eax, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movb %cl, 15(%eax)
+; X86-NEXT: movb %dl, 14(%eax)
+; X86-NEXT: movb %bl, 13(%eax)
+; X86-NEXT: movl %esi, %ecx
+; X86-NEXT: movb %cl, 12(%eax)
+; X86-NEXT: movl %edi, %ecx
+; X86-NEXT: movb %cl, 11(%eax)
+; X86-NEXT: movl %ebp, %ecx
+; X86-NEXT: movb %cl, 10(%eax)
+; X86-NEXT: movl (%esp), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 9(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 8(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 7(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 6(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 5(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 4(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 3(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 2(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 1(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, (%eax)
+; X86-NEXT: addl $40, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call <16 x i8> @llvm.smax.v16i8(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %r
+}
diff --git a/llvm/test/CodeGen/X86/smin.ll b/llvm/test/CodeGen/X86/smin.ll
new file mode 100644
index 000000000000..70391534f544
--- /dev/null
+++ b/llvm/test/CodeGen/X86/smin.ll
@@ -0,0 +1,656 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=X64,SSE
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=avx | FileCheck %s --check-prefixes=X64,AVX,AVX1
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=avx2 | FileCheck %s --check-prefixes=X64,AVX,AVX2
+; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefix=X86
+
+declare i8 @llvm.smin.i8(i8, i8)
+declare i16 @llvm.smin.i16(i16, i16)
+declare i24 @llvm.smin.i24(i24, i24)
+declare i32 @llvm.smin.i32(i32, i32)
+declare i64 @llvm.smin.i64(i64, i64)
+declare i128 @llvm.smin.i128(i128, i128)
+
+declare <1 x i32> @llvm.smin.v1i32(<1 x i32>, <1 x i32>)
+declare <2 x i32> @llvm.smin.v2i32(<2 x i32>, <2 x i32>)
+declare <3 x i32> @llvm.smin.v3i32(<3 x i32>, <3 x i32>)
+declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)
+declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>)
+
+declare <8 x i16> @llvm.smin.v8i16(<8 x i16>, <8 x i16>)
+declare <16 x i8> @llvm.smin.v16i8(<16 x i8>, <16 x i8>)
+
+define i8 @test_i8(i8 %a, i8 %b) nounwind {
+; X64-LABEL: test_i8:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpb %al, %dil
+; X64-NEXT: cmovll %edi, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i8:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpb %al, %cl
+; X86-NEXT: cmovll %ecx, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: retl
+ %r = call i8 @llvm.smin.i8(i8 %a, i8 %b)
+ ret i8 %r
+}
+
+define i16 @test_i16(i16 %a, i16 %b) nounwind {
+; X64-LABEL: test_i16:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpw %ax, %di
+; X64-NEXT: cmovll %edi, %eax
+; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i16:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpw %ax, %cx
+; X86-NEXT: cmovll %ecx, %eax
+; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: retl
+ %r = call i16 @llvm.smin.i16(i16 %a, i16 %b)
+ ret i16 %r
+}
+
+define i24 @test_i24(i24 %a, i24 %b) nounwind {
+; X64-LABEL: test_i24:
+; X64: # %bb.0:
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: shll $8, %esi
+; X64-NEXT: sarl $8, %esi
+; X64-NEXT: shll $8, %eax
+; X64-NEXT: sarl $8, %eax
+; X64-NEXT: cmpl %esi, %eax
+; X64-NEXT: cmovgel %esi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i24:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: shll $8, %ecx
+; X86-NEXT: sarl $8, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: shll $8, %eax
+; X86-NEXT: sarl $8, %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmovgel %ecx, %eax
+; X86-NEXT: retl
+ %r = call i24 @llvm.smin.i24(i24 %a, i24 %b)
+ ret i24 %r
+}
+
+define i32 @test_i32(i32 %a, i32 %b) nounwind {
+; X64-LABEL: test_i32:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpl %esi, %edi
+; X64-NEXT: cmovll %edi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpl %eax, %ecx
+; X86-NEXT: cmovll %ecx, %eax
+; X86-NEXT: retl
+ %r = call i32 @llvm.smin.i32(i32 %a, i32 %b)
+ ret i32 %r
+}
+
+define i64 @test_i64(i64 %a, i64 %b) nounwind {
+; X64-LABEL: test_i64:
+; X64: # %bb.0:
+; X64-NEXT: movq %rsi, %rax
+; X64-NEXT: cmpq %rsi, %rdi
+; X64-NEXT: cmovlq %rdi, %rax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i64:
+; X86: # %bb.0:
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cmpl %eax, %ecx
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: cmovbl %ecx, %edi
+; X86-NEXT: cmpl %edx, %esi
+; X86-NEXT: cmovll %ecx, %eax
+; X86-NEXT: cmovel %edi, %eax
+; X86-NEXT: cmovll %esi, %edx
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: retl
+ %r = call i64 @llvm.smin.i64(i64 %a, i64 %b)
+ ret i64 %r
+}
+
+define i128 @test_i128(i128 %a, i128 %b) nounwind {
+; X64-LABEL: test_i128:
+; X64: # %bb.0:
+; X64-NEXT: movq %rdx, %rax
+; X64-NEXT: cmpq %rdx, %rdi
+; X64-NEXT: cmovbq %rdi, %rdx
+; X64-NEXT: cmpq %rcx, %rsi
+; X64-NEXT: cmovlq %rdi, %rax
+; X64-NEXT: cmoveq %rdx, %rax
+; X64-NEXT: cmovlq %rsi, %rcx
+; X64-NEXT: movq %rcx, %rdx
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i128:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $8, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: movl %ecx, %ebx
+; X86-NEXT: cmovbl %eax, %ebx
+; X86-NEXT: cmpl %esi, %edi
+; X86-NEXT: movl %ecx, %ebp
+; X86-NEXT: cmovbl %eax, %ebp
+; X86-NEXT: cmovel %ebx, %ebp
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: cmovbl %edi, %eax
+; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: cmpl %edx, %edi
+; X86-NEXT: movl %edx, %eax
+; X86-NEXT: cmovbl %edi, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl %ebx, %edi
+; X86-NEXT: sbbl %eax, %edi
+; X86-NEXT: cmovll {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cmovll {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ebx, %edi
+; X86-NEXT: xorl %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: xorl %edx, %ebx
+; X86-NEXT: orl %edi, %ebx
+; X86-NEXT: cmovel %ebp, %ecx
+; X86-NEXT: cmovel (%esp), %esi # 4-byte Folded Reload
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: cmpl %eax, %edi
+; X86-NEXT: cmovll {{[0-9]+}}(%esp), %edx
+; X86-NEXT: cmovel {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
+; X86-NEXT: cmovll %edi, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl %eax, 12(%edi)
+; X86-NEXT: movl %edx, 8(%edi)
+; X86-NEXT: movl %esi, 4(%edi)
+; X86-NEXT: movl %ecx, (%edi)
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: addl $8, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call i128 @llvm.smin.i128(i128 %a, i128 %b)
+ ret i128 %r
+}
+
+define <1 x i32> @test_v1i32(<1 x i32> %a, <1 x i32> %b) nounwind {
+; X64-LABEL: test_v1i32:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpl %esi, %edi
+; X64-NEXT: cmovll %edi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_v1i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpl %eax, %ecx
+; X86-NEXT: cmovll %ecx, %eax
+; X86-NEXT: retl
+ %r = call <1 x i32> @llvm.smin.v1i32(<1 x i32> %a, <1 x i32> %b)
+ ret <1 x i32> %r
+}
+
+define <2 x i32> @test_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
+; SSE-LABEL: test_v2i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm1, %xmm2
+; SSE-NEXT: pcmpgtd %xmm0, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v2i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpminsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v2i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cmpl %eax, %esi
+; X86-NEXT: cmovll %esi, %eax
+; X86-NEXT: cmpl %edx, %ecx
+; X86-NEXT: cmovll %ecx, %edx
+; X86-NEXT: popl %esi
+; X86-NEXT: retl
+ %r = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %r
+}
+
+define <3 x i32> @test_v3i32(<3 x i32> %a, <3 x i32> %b) nounwind {
+; SSE-LABEL: test_v3i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm1, %xmm2
+; SSE-NEXT: pcmpgtd %xmm0, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v3i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpminsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v3i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: cmpl %eax, %ebx
+; X86-NEXT: cmovll %ebx, %eax
+; X86-NEXT: cmpl %edx, %edi
+; X86-NEXT: cmovll %edi, %edx
+; X86-NEXT: cmpl %ecx, %esi
+; X86-NEXT: cmovll %esi, %ecx
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: retl
+ %r = call <3 x i32> @llvm.smin.v3i32(<3 x i32> %a, <3 x i32> %b)
+ ret <3 x i32> %r
+}
+
+define <4 x i32> @test_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
+; SSE-LABEL: test_v4i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm1, %xmm2
+; SSE-NEXT: pcmpgtd %xmm0, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v4i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpminsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edi, %eax
+; X86-NEXT: cmovll %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %esi, %eax
+; X86-NEXT: cmovll %eax, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edx, %eax
+; X86-NEXT: cmovll %eax, %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl %ecx, 12(%eax)
+; X86-NEXT: movl %edx, 8(%eax)
+; X86-NEXT: movl %esi, 4(%eax)
+; X86-NEXT: movl %edi, (%eax)
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: retl $4
+ %r = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> %b)
+ ret <4 x i32> %r
+}
+
+define <8 x i32> @test_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
+; SSE-LABEL: test_v8i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm2, %xmm4
+; SSE-NEXT: pcmpgtd %xmm0, %xmm4
+; SSE-NEXT: pand %xmm4, %xmm0
+; SSE-NEXT: pandn %xmm2, %xmm4
+; SSE-NEXT: por %xmm4, %xmm0
+; SSE-NEXT: movdqa %xmm3, %xmm2
+; SSE-NEXT: pcmpgtd %xmm1, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm1
+; SSE-NEXT: pandn %xmm3, %xmm2
+; SSE-NEXT: por %xmm2, %xmm1
+; SSE-NEXT: retq
+;
+; AVX1-LABEL: test_v8i32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT: vpminsd %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v8i32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpminsd %ymm1, %ymm0, %ymm0
+; AVX2-NEXT: retq
+;
+; X86-LABEL: test_v8i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $8, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ebp, %eax
+; X86-NEXT: cmovll %eax, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ebx, %eax
+; X86-NEXT: cmovll %eax, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edi, %eax
+; X86-NEXT: cmovll %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %esi, %eax
+; X86-NEXT: cmovll %eax, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edx, %eax
+; X86-NEXT: cmovll %eax, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: cmpl %eax, %edx
+; X86-NEXT: cmovll %edx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %eax, 28(%edx)
+; X86-NEXT: movl %ecx, 24(%edx)
+; X86-NEXT: movl (%esp), %eax # 4-byte Reload
+; X86-NEXT: movl %eax, 20(%edx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl %eax, 16(%edx)
+; X86-NEXT: movl %esi, 12(%edx)
+; X86-NEXT: movl %edi, 8(%edx)
+; X86-NEXT: movl %ebx, 4(%edx)
+; X86-NEXT: movl %ebp, (%edx)
+; X86-NEXT: movl %edx, %eax
+; X86-NEXT: addl $8, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %a, <8 x i32> %b)
+ ret <8 x i32> %r
+}
+
+define <8 x i16> @test_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
+; SSE-LABEL: test_v8i16:
+; SSE: # %bb.0:
+; SSE-NEXT: pminsw %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v8i16:
+; AVX: # %bb.0:
+; AVX-NEXT: vpminsw %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v8i16:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $8, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %bp, %ax
+; X86-NEXT: cmovll %eax, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %bx, %ax
+; X86-NEXT: cmovll %eax, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %di, %ax
+; X86-NEXT: cmovll %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %si, %ax
+; X86-NEXT: cmovll %eax, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %dx, %ax
+; X86-NEXT: cmovll %eax, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %cx, %ax
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %dx, %ax
+; X86-NEXT: cmovll %eax, %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpw %ax, %cx
+; X86-NEXT: cmovll %ecx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movw %ax, 14(%ecx)
+; X86-NEXT: movw %dx, 12(%ecx)
+; X86-NEXT: movl (%esp), %eax # 4-byte Reload
+; X86-NEXT: movw %ax, 10(%ecx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movw %ax, 8(%ecx)
+; X86-NEXT: movw %si, 6(%ecx)
+; X86-NEXT: movw %di, 4(%ecx)
+; X86-NEXT: movw %bx, 2(%ecx)
+; X86-NEXT: movw %bp, (%ecx)
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: addl $8, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call <8 x i16> @llvm.smin.v8i16(<8 x i16> %a, <8 x i16> %b)
+ ret <8 x i16> %r
+}
+
+define <16 x i8> @test_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
+; SSE-LABEL: test_v16i8:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa %xmm1, %xmm2
+; SSE-NEXT: pcmpgtb %xmm0, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v16i8:
+; AVX: # %bb.0:
+; AVX-NEXT: vpminsb %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v16i8:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $40, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %bl, %al
+; X86-NEXT: cmovll %eax, %ebx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %dl, %al
+; X86-NEXT: cmovll %eax, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl %ecx, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl %ecx, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %bl, %al
+; X86-NEXT: cmovll %eax, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %dl, %al
+; X86-NEXT: cmovll %eax, %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovll %eax, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movb %cl, 15(%eax)
+; X86-NEXT: movb %dl, 14(%eax)
+; X86-NEXT: movb %bl, 13(%eax)
+; X86-NEXT: movl %esi, %ecx
+; X86-NEXT: movb %cl, 12(%eax)
+; X86-NEXT: movl %edi, %ecx
+; X86-NEXT: movb %cl, 11(%eax)
+; X86-NEXT: movl %ebp, %ecx
+; X86-NEXT: movb %cl, 10(%eax)
+; X86-NEXT: movl (%esp), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 9(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 8(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 7(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 6(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 5(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 4(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 3(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 2(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 1(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, (%eax)
+; X86-NEXT: addl $40, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call <16 x i8> @llvm.smin.v16i8(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %r
+}
diff --git a/llvm/test/CodeGen/X86/umax.ll b/llvm/test/CodeGen/X86/umax.ll
new file mode 100644
index 000000000000..14a0248e1914
--- /dev/null
+++ b/llvm/test/CodeGen/X86/umax.ll
@@ -0,0 +1,668 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=X64,SSE
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=avx | FileCheck %s --check-prefixes=X64,AVX,AVX1
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=avx2 | FileCheck %s --check-prefixes=X64,AVX,AVX2
+; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefix=X86
+
+declare i8 @llvm.umax.i8(i8, i8)
+declare i16 @llvm.umax.i16(i16, i16)
+declare i24 @llvm.umax.i24(i24, i24)
+declare i32 @llvm.umax.i32(i32, i32)
+declare i64 @llvm.umax.i64(i64, i64)
+declare i128 @llvm.umax.i128(i128, i128)
+
+declare <1 x i32> @llvm.umax.v1i32(<1 x i32>, <1 x i32>)
+declare <2 x i32> @llvm.umax.v2i32(<2 x i32>, <2 x i32>)
+declare <3 x i32> @llvm.umax.v3i32(<3 x i32>, <3 x i32>)
+declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>)
+declare <8 x i32> @llvm.umax.v8i32(<8 x i32>, <8 x i32>)
+
+declare <8 x i16> @llvm.umax.v8i16(<8 x i16>, <8 x i16>)
+declare <16 x i8> @llvm.umax.v16i8(<16 x i8>, <16 x i8>)
+
+define i8 @test_i8(i8 %a, i8 %b) nounwind {
+; X64-LABEL: test_i8:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpb %al, %dil
+; X64-NEXT: cmoval %edi, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i8:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpb %al, %cl
+; X86-NEXT: cmoval %ecx, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: retl
+ %r = call i8 @llvm.umax.i8(i8 %a, i8 %b)
+ ret i8 %r
+}
+
+define i16 @test_i16(i16 %a, i16 %b) nounwind {
+; X64-LABEL: test_i16:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpw %ax, %di
+; X64-NEXT: cmoval %edi, %eax
+; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i16:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpw %ax, %cx
+; X86-NEXT: cmoval %ecx, %eax
+; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: retl
+ %r = call i16 @llvm.umax.i16(i16 %a, i16 %b)
+ ret i16 %r
+}
+
+define i24 @test_i24(i24 %a, i24 %b) nounwind {
+; X64-LABEL: test_i24:
+; X64: # %bb.0:
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: andl $16777215, %esi # imm = 0xFFFFFF
+; X64-NEXT: andl $16777215, %eax # imm = 0xFFFFFF
+; X64-NEXT: cmpl %esi, %eax
+; X64-NEXT: cmovbel %esi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i24:
+; X86: # %bb.0:
+; X86-NEXT: movl $16777215, %eax # imm = 0xFFFFFF
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: andl %eax, %ecx
+; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmovbel %ecx, %eax
+; X86-NEXT: retl
+ %r = call i24 @llvm.umax.i24(i24 %a, i24 %b)
+ ret i24 %r
+}
+
+define i32 @test_i32(i32 %a, i32 %b) nounwind {
+; X64-LABEL: test_i32:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpl %esi, %edi
+; X64-NEXT: cmoval %edi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpl %eax, %ecx
+; X86-NEXT: cmoval %ecx, %eax
+; X86-NEXT: retl
+ %r = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+ ret i32 %r
+}
+
+define i64 @test_i64(i64 %a, i64 %b) nounwind {
+; X64-LABEL: test_i64:
+; X64: # %bb.0:
+; X64-NEXT: movq %rsi, %rax
+; X64-NEXT: cmpq %rsi, %rdi
+; X64-NEXT: cmovaq %rdi, %rax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i64:
+; X86: # %bb.0:
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cmpl %eax, %ecx
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: cmoval %ecx, %edi
+; X86-NEXT: cmpl %edx, %esi
+; X86-NEXT: cmoval %ecx, %eax
+; X86-NEXT: cmovel %edi, %eax
+; X86-NEXT: cmoval %esi, %edx
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: retl
+ %r = call i64 @llvm.umax.i64(i64 %a, i64 %b)
+ ret i64 %r
+}
+
+define i128 @test_i128(i128 %a, i128 %b) nounwind {
+; X64-LABEL: test_i128:
+; X64: # %bb.0:
+; X64-NEXT: movq %rdx, %rax
+; X64-NEXT: cmpq %rdx, %rdi
+; X64-NEXT: cmovaq %rdi, %rdx
+; X64-NEXT: cmpq %rcx, %rsi
+; X64-NEXT: cmovaq %rdi, %rax
+; X64-NEXT: cmoveq %rdx, %rax
+; X64-NEXT: cmovaq %rsi, %rcx
+; X64-NEXT: movq %rcx, %rdx
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i128:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: pushl %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpl %ebx, %edx
+; X86-NEXT: movl %ebx, %eax
+; X86-NEXT: cmoval %edx, %eax
+; X86-NEXT: cmpl %esi, %ecx
+; X86-NEXT: movl %ebx, %ebp
+; X86-NEXT: cmoval %edx, %ebp
+; X86-NEXT: cmovel %eax, %ebp
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: cmoval %ecx, %eax
+; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %edx, %ecx
+; X86-NEXT: sbbl %edi, %ecx
+; X86-NEXT: cmovbl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cmovbl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl %edi, %ecx
+; X86-NEXT: xorl %edx, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: xorl %eax, %edi
+; X86-NEXT: orl %ecx, %edi
+; X86-NEXT: cmovel %ebp, %ebx
+; X86-NEXT: cmovel (%esp), %esi # 4-byte Folded Reload
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: cmpl %eax, %edi
+; X86-NEXT: movl %eax, %ecx
+; X86-NEXT: cmoval %edi, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: cmpl %edx, %ebp
+; X86-NEXT: cmoval %edi, %eax
+; X86-NEXT: cmovel %ecx, %eax
+; X86-NEXT: cmoval %ebp, %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %edx, 12(%ecx)
+; X86-NEXT: movl %eax, 8(%ecx)
+; X86-NEXT: movl %esi, 4(%ecx)
+; X86-NEXT: movl %ebx, (%ecx)
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: addl $4, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call i128 @llvm.umax.i128(i128 %a, i128 %b)
+ ret i128 %r
+}
+
+define <1 x i32> @test_v1i32(<1 x i32> %a, <1 x i32> %b) nounwind {
+; X64-LABEL: test_v1i32:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpl %esi, %edi
+; X64-NEXT: cmoval %edi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_v1i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpl %eax, %ecx
+; X86-NEXT: cmoval %ecx, %eax
+; X86-NEXT: retl
+ %r = call <1 x i32> @llvm.umax.v1i32(<1 x i32> %a, <1 x i32> %b)
+ ret <1 x i32> %r
+}
+
+define <2 x i32> @test_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
+; SSE-LABEL: test_v2i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; SSE-NEXT: movdqa %xmm1, %xmm3
+; SSE-NEXT: pxor %xmm2, %xmm3
+; SSE-NEXT: pxor %xmm0, %xmm2
+; SSE-NEXT: pcmpgtd %xmm3, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v2i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v2i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cmpl %eax, %esi
+; X86-NEXT: cmoval %esi, %eax
+; X86-NEXT: cmpl %edx, %ecx
+; X86-NEXT: cmoval %ecx, %edx
+; X86-NEXT: popl %esi
+; X86-NEXT: retl
+ %r = call <2 x i32> @llvm.umax.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %r
+}
+
+define <3 x i32> @test_v3i32(<3 x i32> %a, <3 x i32> %b) nounwind {
+; SSE-LABEL: test_v3i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; SSE-NEXT: movdqa %xmm1, %xmm3
+; SSE-NEXT: pxor %xmm2, %xmm3
+; SSE-NEXT: pxor %xmm0, %xmm2
+; SSE-NEXT: pcmpgtd %xmm3, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v3i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v3i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: cmpl %eax, %ebx
+; X86-NEXT: cmoval %ebx, %eax
+; X86-NEXT: cmpl %edx, %edi
+; X86-NEXT: cmoval %edi, %edx
+; X86-NEXT: cmpl %ecx, %esi
+; X86-NEXT: cmoval %esi, %ecx
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: retl
+ %r = call <3 x i32> @llvm.umax.v3i32(<3 x i32> %a, <3 x i32> %b)
+ ret <3 x i32> %r
+}
+
+define <4 x i32> @test_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
+; SSE-LABEL: test_v4i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; SSE-NEXT: movdqa %xmm1, %xmm3
+; SSE-NEXT: pxor %xmm2, %xmm3
+; SSE-NEXT: pxor %xmm0, %xmm2
+; SSE-NEXT: pcmpgtd %xmm3, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v4i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edi, %eax
+; X86-NEXT: cmoval %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %esi, %eax
+; X86-NEXT: cmoval %eax, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edx, %eax
+; X86-NEXT: cmoval %eax, %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl %ecx, 12(%eax)
+; X86-NEXT: movl %edx, 8(%eax)
+; X86-NEXT: movl %esi, 4(%eax)
+; X86-NEXT: movl %edi, (%eax)
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: retl $4
+ %r = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> %b)
+ ret <4 x i32> %r
+}
+
+define <8 x i32> @test_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
+; SSE-LABEL: test_v8i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648]
+; SSE-NEXT: movdqa %xmm2, %xmm6
+; SSE-NEXT: pxor %xmm5, %xmm6
+; SSE-NEXT: movdqa %xmm0, %xmm4
+; SSE-NEXT: pxor %xmm5, %xmm4
+; SSE-NEXT: pcmpgtd %xmm6, %xmm4
+; SSE-NEXT: pand %xmm4, %xmm0
+; SSE-NEXT: pandn %xmm2, %xmm4
+; SSE-NEXT: por %xmm0, %xmm4
+; SSE-NEXT: movdqa %xmm3, %xmm0
+; SSE-NEXT: pxor %xmm5, %xmm0
+; SSE-NEXT: pxor %xmm1, %xmm5
+; SSE-NEXT: pcmpgtd %xmm0, %xmm5
+; SSE-NEXT: pand %xmm5, %xmm1
+; SSE-NEXT: pandn %xmm3, %xmm5
+; SSE-NEXT: por %xmm5, %xmm1
+; SSE-NEXT: movdqa %xmm4, %xmm0
+; SSE-NEXT: retq
+;
+; AVX1-LABEL: test_v8i32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT: vpmaxud %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v8i32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpmaxud %ymm1, %ymm0, %ymm0
+; AVX2-NEXT: retq
+;
+; X86-LABEL: test_v8i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $8, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ebp, %eax
+; X86-NEXT: cmoval %eax, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ebx, %eax
+; X86-NEXT: cmoval %eax, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edi, %eax
+; X86-NEXT: cmoval %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %esi, %eax
+; X86-NEXT: cmoval %eax, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edx, %eax
+; X86-NEXT: cmoval %eax, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: cmpl %eax, %edx
+; X86-NEXT: cmoval %edx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %eax, 28(%edx)
+; X86-NEXT: movl %ecx, 24(%edx)
+; X86-NEXT: movl (%esp), %eax # 4-byte Reload
+; X86-NEXT: movl %eax, 20(%edx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl %eax, 16(%edx)
+; X86-NEXT: movl %esi, 12(%edx)
+; X86-NEXT: movl %edi, 8(%edx)
+; X86-NEXT: movl %ebx, 4(%edx)
+; X86-NEXT: movl %ebp, (%edx)
+; X86-NEXT: movl %edx, %eax
+; X86-NEXT: addl $8, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call <8 x i32> @llvm.umax.v8i32(<8 x i32> %a, <8 x i32> %b)
+ ret <8 x i32> %r
+}
+
+define <8 x i16> @test_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
+; SSE-LABEL: test_v8i16:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768]
+; SSE-NEXT: pxor %xmm2, %xmm1
+; SSE-NEXT: pxor %xmm2, %xmm0
+; SSE-NEXT: pmaxsw %xmm1, %xmm0
+; SSE-NEXT: pxor %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v8i16:
+; AVX: # %bb.0:
+; AVX-NEXT: vpmaxuw %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v8i16:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $8, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %bp, %ax
+; X86-NEXT: cmoval %eax, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %bx, %ax
+; X86-NEXT: cmoval %eax, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %di, %ax
+; X86-NEXT: cmoval %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %si, %ax
+; X86-NEXT: cmoval %eax, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %dx, %ax
+; X86-NEXT: cmoval %eax, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %cx, %ax
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %dx, %ax
+; X86-NEXT: cmoval %eax, %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpw %ax, %cx
+; X86-NEXT: cmoval %ecx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movw %ax, 14(%ecx)
+; X86-NEXT: movw %dx, 12(%ecx)
+; X86-NEXT: movl (%esp), %eax # 4-byte Reload
+; X86-NEXT: movw %ax, 10(%ecx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movw %ax, 8(%ecx)
+; X86-NEXT: movw %si, 6(%ecx)
+; X86-NEXT: movw %di, 4(%ecx)
+; X86-NEXT: movw %bx, 2(%ecx)
+; X86-NEXT: movw %bp, (%ecx)
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: addl $8, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call <8 x i16> @llvm.umax.v8i16(<8 x i16> %a, <8 x i16> %b)
+ ret <8 x i16> %r
+}
+
+define <16 x i8> @test_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
+; SSE-LABEL: test_v16i8:
+; SSE: # %bb.0:
+; SSE-NEXT: pmaxub %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v16i8:
+; AVX: # %bb.0:
+; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v16i8:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $40, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %bl, %al
+; X86-NEXT: cmoval %eax, %ebx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %dl, %al
+; X86-NEXT: cmoval %eax, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl %ecx, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl %ecx, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %bl, %al
+; X86-NEXT: cmoval %eax, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %dl, %al
+; X86-NEXT: cmoval %eax, %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmoval %eax, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movb %cl, 15(%eax)
+; X86-NEXT: movb %dl, 14(%eax)
+; X86-NEXT: movb %bl, 13(%eax)
+; X86-NEXT: movl %esi, %ecx
+; X86-NEXT: movb %cl, 12(%eax)
+; X86-NEXT: movl %edi, %ecx
+; X86-NEXT: movb %cl, 11(%eax)
+; X86-NEXT: movl %ebp, %ecx
+; X86-NEXT: movb %cl, 10(%eax)
+; X86-NEXT: movl (%esp), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 9(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 8(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 7(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 6(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 5(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 4(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 3(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 2(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 1(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, (%eax)
+; X86-NEXT: addl $40, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %r
+}
diff --git a/llvm/test/CodeGen/X86/umin.ll b/llvm/test/CodeGen/X86/umin.ll
new file mode 100644
index 000000000000..234c4faf6cd2
--- /dev/null
+++ b/llvm/test/CodeGen/X86/umin.ll
@@ -0,0 +1,667 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefixes=X64,SSE
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=avx | FileCheck %s --check-prefixes=X64,AVX,AVX1
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=avx2 | FileCheck %s --check-prefixes=X64,AVX,AVX2
+; RUN: llc < %s -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefix=X86
+
+declare i8 @llvm.umin.i8(i8, i8)
+declare i16 @llvm.umin.i16(i16, i16)
+declare i24 @llvm.umin.i24(i24, i24)
+declare i32 @llvm.umin.i32(i32, i32)
+declare i64 @llvm.umin.i64(i64, i64)
+declare i128 @llvm.umin.i128(i128, i128)
+
+declare <1 x i32> @llvm.umin.v1i32(<1 x i32>, <1 x i32>)
+declare <2 x i32> @llvm.umin.v2i32(<2 x i32>, <2 x i32>)
+declare <3 x i32> @llvm.umin.v3i32(<3 x i32>, <3 x i32>)
+declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)
+declare <8 x i32> @llvm.umin.v8i32(<8 x i32>, <8 x i32>)
+
+declare <8 x i16> @llvm.umin.v8i16(<8 x i16>, <8 x i16>)
+declare <16 x i8> @llvm.umin.v16i8(<16 x i8>, <16 x i8>)
+
+define i8 @test_i8(i8 %a, i8 %b) nounwind {
+; X64-LABEL: test_i8:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpb %al, %dil
+; X64-NEXT: cmovbl %edi, %eax
+; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i8:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpb %al, %cl
+; X86-NEXT: cmovbl %ecx, %eax
+; X86-NEXT: # kill: def $al killed $al killed $eax
+; X86-NEXT: retl
+ %r = call i8 @llvm.umin.i8(i8 %a, i8 %b)
+ ret i8 %r
+}
+
+define i16 @test_i16(i16 %a, i16 %b) nounwind {
+; X64-LABEL: test_i16:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpw %ax, %di
+; X64-NEXT: cmovbl %edi, %eax
+; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i16:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpw %ax, %cx
+; X86-NEXT: cmovbl %ecx, %eax
+; X86-NEXT: # kill: def $ax killed $ax killed $eax
+; X86-NEXT: retl
+ %r = call i16 @llvm.umin.i16(i16 %a, i16 %b)
+ ret i16 %r
+}
+
+define i24 @test_i24(i24 %a, i24 %b) nounwind {
+; X64-LABEL: test_i24:
+; X64: # %bb.0:
+; X64-NEXT: movl %edi, %eax
+; X64-NEXT: andl $16777215, %esi # imm = 0xFFFFFF
+; X64-NEXT: andl $16777215, %eax # imm = 0xFFFFFF
+; X64-NEXT: cmpl %esi, %eax
+; X64-NEXT: cmovael %esi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i24:
+; X86: # %bb.0:
+; X86-NEXT: movl $16777215, %eax # imm = 0xFFFFFF
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: andl %eax, %ecx
+; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmovael %ecx, %eax
+; X86-NEXT: retl
+ %r = call i24 @llvm.umin.i24(i24 %a, i24 %b)
+ ret i24 %r
+}
+
+define i32 @test_i32(i32 %a, i32 %b) nounwind {
+; X64-LABEL: test_i32:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpl %esi, %edi
+; X64-NEXT: cmovbl %edi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpl %eax, %ecx
+; X86-NEXT: cmovbl %ecx, %eax
+; X86-NEXT: retl
+ %r = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+ ret i32 %r
+}
+
+define i64 @test_i64(i64 %a, i64 %b) nounwind {
+; X64-LABEL: test_i64:
+; X64: # %bb.0:
+; X64-NEXT: movq %rsi, %rax
+; X64-NEXT: cmpq %rsi, %rdi
+; X64-NEXT: cmovbq %rdi, %rax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i64:
+; X86: # %bb.0:
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cmpl %eax, %ecx
+; X86-NEXT: movl %eax, %edi
+; X86-NEXT: cmovbl %ecx, %edi
+; X86-NEXT: cmpl %edx, %esi
+; X86-NEXT: cmovbl %ecx, %eax
+; X86-NEXT: cmovel %edi, %eax
+; X86-NEXT: cmovbl %esi, %edx
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: retl
+ %r = call i64 @llvm.umin.i64(i64 %a, i64 %b)
+ ret i64 %r
+}
+
+define i128 @test_i128(i128 %a, i128 %b) nounwind {
+; X64-LABEL: test_i128:
+; X64: # %bb.0:
+; X64-NEXT: movq %rdx, %rax
+; X64-NEXT: cmpq %rdx, %rdi
+; X64-NEXT: cmovbq %rdi, %rdx
+; X64-NEXT: cmpq %rcx, %rsi
+; X64-NEXT: cmovbq %rdi, %rax
+; X64-NEXT: cmoveq %rdx, %rax
+; X64-NEXT: cmovbq %rsi, %rcx
+; X64-NEXT: movq %rcx, %rdx
+; X64-NEXT: retq
+;
+; X86-LABEL: test_i128:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $8, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: movl %ecx, %ebx
+; X86-NEXT: cmovbl %eax, %ebx
+; X86-NEXT: cmpl %esi, %edi
+; X86-NEXT: movl %ecx, %ebp
+; X86-NEXT: cmovbl %eax, %ebp
+; X86-NEXT: cmovel %ebx, %ebp
+; X86-NEXT: movl %esi, %eax
+; X86-NEXT: cmovbl %edi, %eax
+; X86-NEXT: movl %eax, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: cmpl %edx, %edi
+; X86-NEXT: movl %edx, %eax
+; X86-NEXT: cmovbl %edi, %eax
+; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl %ebx, %edi
+; X86-NEXT: sbbl %eax, %edi
+; X86-NEXT: cmovbl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cmovbl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl %ebx, %edi
+; X86-NEXT: xorl %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: xorl %edx, %ebx
+; X86-NEXT: orl %edi, %ebx
+; X86-NEXT: cmovel %ebp, %ecx
+; X86-NEXT: cmovel (%esp), %esi # 4-byte Folded Reload
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: cmpl %eax, %edi
+; X86-NEXT: cmovbl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: cmovel {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload
+; X86-NEXT: cmovbl %edi, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl %eax, 12(%edi)
+; X86-NEXT: movl %edx, 8(%edi)
+; X86-NEXT: movl %esi, 4(%edi)
+; X86-NEXT: movl %ecx, (%edi)
+; X86-NEXT: movl %edi, %eax
+; X86-NEXT: addl $8, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call i128 @llvm.umin.i128(i128 %a, i128 %b)
+ ret i128 %r
+}
+
+define <1 x i32> @test_v1i32(<1 x i32> %a, <1 x i32> %b) nounwind {
+; X64-LABEL: test_v1i32:
+; X64: # %bb.0:
+; X64-NEXT: movl %esi, %eax
+; X64-NEXT: cmpl %esi, %edi
+; X64-NEXT: cmovbl %edi, %eax
+; X64-NEXT: retq
+;
+; X86-LABEL: test_v1i32:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpl %eax, %ecx
+; X86-NEXT: cmovbl %ecx, %eax
+; X86-NEXT: retl
+ %r = call <1 x i32> @llvm.umin.v1i32(<1 x i32> %a, <1 x i32> %b)
+ ret <1 x i32> %r
+}
+
+define <2 x i32> @test_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
+; SSE-LABEL: test_v2i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; SSE-NEXT: movdqa %xmm0, %xmm3
+; SSE-NEXT: pxor %xmm2, %xmm3
+; SSE-NEXT: pxor %xmm1, %xmm2
+; SSE-NEXT: pcmpgtd %xmm3, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v2i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v2i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: cmpl %eax, %esi
+; X86-NEXT: cmovbl %esi, %eax
+; X86-NEXT: cmpl %edx, %ecx
+; X86-NEXT: cmovbl %ecx, %edx
+; X86-NEXT: popl %esi
+; X86-NEXT: retl
+ %r = call <2 x i32> @llvm.umin.v2i32(<2 x i32> %a, <2 x i32> %b)
+ ret <2 x i32> %r
+}
+
+define <3 x i32> @test_v3i32(<3 x i32> %a, <3 x i32> %b) nounwind {
+; SSE-LABEL: test_v3i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; SSE-NEXT: movdqa %xmm0, %xmm3
+; SSE-NEXT: pxor %xmm2, %xmm3
+; SSE-NEXT: pxor %xmm1, %xmm2
+; SSE-NEXT: pcmpgtd %xmm3, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v3i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v3i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: cmpl %eax, %ebx
+; X86-NEXT: cmovbl %ebx, %eax
+; X86-NEXT: cmpl %edx, %edi
+; X86-NEXT: cmovbl %edi, %edx
+; X86-NEXT: cmpl %ecx, %esi
+; X86-NEXT: cmovbl %esi, %ecx
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: retl
+ %r = call <3 x i32> @llvm.umin.v3i32(<3 x i32> %a, <3 x i32> %b)
+ ret <3 x i32> %r
+}
+
+define <4 x i32> @test_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
+; SSE-LABEL: test_v4i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; SSE-NEXT: movdqa %xmm0, %xmm3
+; SSE-NEXT: pxor %xmm2, %xmm3
+; SSE-NEXT: pxor %xmm1, %xmm2
+; SSE-NEXT: pcmpgtd %xmm3, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm0
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v4i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vpminud %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v4i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edi, %eax
+; X86-NEXT: cmovbl %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %esi, %eax
+; X86-NEXT: cmovbl %eax, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edx, %eax
+; X86-NEXT: cmovbl %eax, %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl %ecx, 12(%eax)
+; X86-NEXT: movl %edx, 8(%eax)
+; X86-NEXT: movl %esi, 4(%eax)
+; X86-NEXT: movl %edi, (%eax)
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: retl $4
+ %r = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> %b)
+ ret <4 x i32> %r
+}
+
+define <8 x i32> @test_v8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
+; SSE-LABEL: test_v8i32:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
+; SSE-NEXT: movdqa %xmm0, %xmm5
+; SSE-NEXT: pxor %xmm4, %xmm5
+; SSE-NEXT: movdqa %xmm2, %xmm6
+; SSE-NEXT: pxor %xmm4, %xmm6
+; SSE-NEXT: pcmpgtd %xmm5, %xmm6
+; SSE-NEXT: pand %xmm6, %xmm0
+; SSE-NEXT: pandn %xmm2, %xmm6
+; SSE-NEXT: por %xmm6, %xmm0
+; SSE-NEXT: movdqa %xmm1, %xmm2
+; SSE-NEXT: pxor %xmm4, %xmm2
+; SSE-NEXT: pxor %xmm3, %xmm4
+; SSE-NEXT: pcmpgtd %xmm2, %xmm4
+; SSE-NEXT: pand %xmm4, %xmm1
+; SSE-NEXT: pandn %xmm3, %xmm4
+; SSE-NEXT: por %xmm4, %xmm1
+; SSE-NEXT: retq
+;
+; AVX1-LABEL: test_v8i32:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
+; AVX1-NEXT: vpminud %xmm2, %xmm3, %xmm2
+; AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: test_v8i32:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpminud %ymm1, %ymm0, %ymm0
+; AVX2-NEXT: retq
+;
+; X86-LABEL: test_v8i32:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $8, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ebp, %eax
+; X86-NEXT: cmovbl %eax, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ebx, %eax
+; X86-NEXT: cmovbl %eax, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edi, %eax
+; X86-NEXT: cmovbl %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %esi, %eax
+; X86-NEXT: cmovbl %eax, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %edx, %eax
+; X86-NEXT: cmovbl %eax, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl %ecx, %eax
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: cmpl %eax, %edx
+; X86-NEXT: cmovbl %edx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl %eax, 28(%edx)
+; X86-NEXT: movl %ecx, 24(%edx)
+; X86-NEXT: movl (%esp), %eax # 4-byte Reload
+; X86-NEXT: movl %eax, 20(%edx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movl %eax, 16(%edx)
+; X86-NEXT: movl %esi, 12(%edx)
+; X86-NEXT: movl %edi, 8(%edx)
+; X86-NEXT: movl %ebx, 4(%edx)
+; X86-NEXT: movl %ebp, (%edx)
+; X86-NEXT: movl %edx, %eax
+; X86-NEXT: addl $8, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %a, <8 x i32> %b)
+ ret <8 x i32> %r
+}
+
+define <8 x i16> @test_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
+; SSE-LABEL: test_v8i16:
+; SSE: # %bb.0:
+; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768]
+; SSE-NEXT: pxor %xmm2, %xmm1
+; SSE-NEXT: pxor %xmm2, %xmm0
+; SSE-NEXT: pminsw %xmm1, %xmm0
+; SSE-NEXT: pxor %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v8i16:
+; AVX: # %bb.0:
+; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v8i16:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $8, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %bp, %ax
+; X86-NEXT: cmovbl %eax, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %bx, %ax
+; X86-NEXT: cmovbl %eax, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %di, %ax
+; X86-NEXT: cmovbl %eax, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %si, %ax
+; X86-NEXT: cmovbl %eax, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %dx, %ax
+; X86-NEXT: cmovbl %eax, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %cx, %ax
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpw %dx, %ax
+; X86-NEXT: cmovbl %eax, %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: cmpw %ax, %cx
+; X86-NEXT: cmovbl %ecx, %eax
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movw %ax, 14(%ecx)
+; X86-NEXT: movw %dx, 12(%ecx)
+; X86-NEXT: movl (%esp), %eax # 4-byte Reload
+; X86-NEXT: movw %ax, 10(%ecx)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
+; X86-NEXT: movw %ax, 8(%ecx)
+; X86-NEXT: movw %si, 6(%ecx)
+; X86-NEXT: movw %di, 4(%ecx)
+; X86-NEXT: movw %bx, 2(%ecx)
+; X86-NEXT: movw %bp, (%ecx)
+; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: addl $8, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call <8 x i16> @llvm.umin.v8i16(<8 x i16> %a, <8 x i16> %b)
+ ret <8 x i16> %r
+}
+
+define <16 x i8> @test_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
+; SSE-LABEL: test_v16i8:
+; SSE: # %bb.0:
+; SSE-NEXT: pminub %xmm1, %xmm0
+; SSE-NEXT: retq
+;
+; AVX-LABEL: test_v16i8:
+; AVX: # %bb.0:
+; AVX-NEXT: vpminub %xmm1, %xmm0, %xmm0
+; AVX-NEXT: retq
+;
+; X86-LABEL: test_v16i8:
+; X86: # %bb.0:
+; X86-NEXT: pushl %ebp
+; X86-NEXT: pushl %ebx
+; X86-NEXT: pushl %edi
+; X86-NEXT: pushl %esi
+; X86-NEXT: subl $40, %esp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %bl, %al
+; X86-NEXT: cmovbl %eax, %ebx
+; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %dl, %al
+; X86-NEXT: cmovbl %eax, %edx
+; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl %ecx, (%esp) # 4-byte Spill
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl %ecx, %ebp
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl %ecx, %edi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl %ecx, %esi
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %bl, %al
+; X86-NEXT: cmovbl %eax, %ebx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %dl, %al
+; X86-NEXT: cmovbl %eax, %edx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpb %cl, %al
+; X86-NEXT: cmovbl %eax, %ecx
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movb %cl, 15(%eax)
+; X86-NEXT: movb %dl, 14(%eax)
+; X86-NEXT: movb %bl, 13(%eax)
+; X86-NEXT: movl %esi, %ecx
+; X86-NEXT: movb %cl, 12(%eax)
+; X86-NEXT: movl %edi, %ecx
+; X86-NEXT: movb %cl, 11(%eax)
+; X86-NEXT: movl %ebp, %ecx
+; X86-NEXT: movb %cl, 10(%eax)
+; X86-NEXT: movl (%esp), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 9(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 8(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 7(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 6(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 5(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 4(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 3(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 2(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, 1(%eax)
+; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
+; X86-NEXT: movb %cl, (%eax)
+; X86-NEXT: addl $40, %esp
+; X86-NEXT: popl %esi
+; X86-NEXT: popl %edi
+; X86-NEXT: popl %ebx
+; X86-NEXT: popl %ebp
+; X86-NEXT: retl $4
+ %r = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %a, <16 x i8> %b)
+ ret <16 x i8> %r
+}
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