[PATCH] D84314: AMDGPU/GlobalISel: Fix assert on copy to vcc

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: nhaehnle, foad, kerbowa, mbrkusanin, Petar.Avramovic.
Herald added subscribers: hiraditya, t-tye, tpr, dstuttard, rovka, yaxunl, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

This was trying to constrain a physical register. By the verifier's
understanding, it's impossible to have a 1-bit copy to vcc/vcc_lo so
don't try to handle physregs.


https://reviews.llvm.org/D84314

Files:
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir


Index: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
@@ -239,3 +239,53 @@
     S_ENDPGM 0, implicit %2
 
 ...
+
+---
+
+name:            copy_s64_to_vcc
+legalized:       true
+regBankSelected: true
+
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; WAVE64-LABEL: name: copy_s64_to_vcc
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+    ; WAVE64: $vcc = COPY [[COPY]]
+    ; WAVE64: S_ENDPGM 0, implicit $vcc
+    ; WAVE32-LABEL: name: copy_s64_to_vcc
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+    ; WAVE32: $vcc = COPY [[COPY]]
+    ; WAVE32: S_ENDPGM 0, implicit $vcc_lo
+    %0:sgpr(s64) = COPY $sgpr0_sgpr1
+    $vcc = COPY %0
+    S_ENDPGM 0, implicit $vcc
+
+...
+
+---
+
+name:            copy_s32_to_vcc_lo
+legalized:       true
+regBankSelected: true
+
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; WAVE64-LABEL: name: copy_s32_to_vcc_lo
+    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE64: $vcc_lo = COPY [[COPY]]
+    ; WAVE64: S_ENDPGM 0, implicit $vcc
+    ; WAVE32-LABEL: name: copy_s32_to_vcc_lo
+    ; WAVE32: $vcc_hi = IMPLICIT_DEF
+    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; WAVE32: $vcc_lo = COPY [[COPY]]
+    ; WAVE32: S_ENDPGM 0, implicit $vcc_lo
+    %0:sgpr(s32) = COPY $sgpr0
+    $vcc_lo = COPY %0
+    S_ENDPGM 0, implicit $vcc
+
+...
Index: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -77,8 +77,9 @@
 
 bool AMDGPUInstructionSelector::isVCC(Register Reg,
                                       const MachineRegisterInfo &MRI) const {
-  if (Register::isPhysicalRegister(Reg))
-    return Reg == TRI.getVCC();
+  // The verifier is oblivious to s1 being a valid value for wavesize registers.
+  if (Reg.isPhysical())
+    return false;
 
   auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
   const TargetRegisterClass *RC =


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