[llvm] 1eb279d - [PowerPC][Power10] Add Vector Multiply/Mod/Divide Instruction Definitions and MC Tests
Amy Kwan via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 21 16:11:19 PDT 2020
Author: Amy Kwan
Date: 2020-07-21T18:05:35-05:00
New Revision: 1eb279d2a8c8325714bf517bff72d46f2d78cb05
URL: https://github.com/llvm/llvm-project/commit/1eb279d2a8c8325714bf517bff72d46f2d78cb05
DIFF: https://github.com/llvm/llvm-project/commit/1eb279d2a8c8325714bf517bff72d46f2d78cb05.diff
LOG: [PowerPC][Power10] Add Vector Multiply/Mod/Divide Instruction Definitions and MC Tests
This patch adds the td definitions and asm/disasm tests for the following instructions:
- Vector Multiply Low Doubleword: vmulld
- Vector Modulus Word/Doubleword: vmodsw, vmoduw, vmodsd, vmodud
- Vector Divide Word/Doubleword: vdivsw, vdivuw, vdivsd, vdivud
- Vector Multiply High Word/Doubleword: vmulhsw, vmulhsd, vmulhuw, vmulhud
- Vector Divide Extended Word/Doubleword: vdivesw, vdiveuw, vdivesd, vdiveud
Differential Revision: https://reviews.llvm.org/D82929
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 742693083432..6bf8475a7947 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -972,7 +972,40 @@ let Predicates = [IsISA3_1] in {
"vclrrb $vD, $vA, $rB", IIC_VecGeneral,
[(set v16i8:$vD,
(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
-
+ def VMULLD : VXForm_1<457, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmulld $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VMULHSW : VXForm_1<905, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmulhsw $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VMULHUW : VXForm_1<649, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmulhuw $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VMULHSD : VXForm_1<969, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmulhsd $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VMULHUD : VXForm_1<713, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmulhud $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VMODSW : VXForm_1<1931, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmodsw $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VMODUW : VXForm_1<1675, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmoduw $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VMODSD : VXForm_1<1995, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmodsd $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VMODUD : VXForm_1<1739, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmodud $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VDIVSW : VXForm_1<395, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vdivsw $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VDIVUW : VXForm_1<139, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vdivuw $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VDIVSD : VXForm_1<459, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vdivsd $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VDIVUD : VXForm_1<203, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vdivud $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VDIVESW : VXForm_1<907, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vdivesw $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vdiveuw $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VDIVESD : VXForm_1<971, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vdivesd $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VDIVEUD : VXForm_1<715, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vdiveud $vD, $vA, $vB", IIC_VecGeneral, []>;
def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
"xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
index 15ea5e9f1138..038a7f1a84fe 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
@@ -231,6 +231,57 @@
# CHECK: vsrdbi 2, 3, 4, 5
0x10 0x43 0x23 0x56
+# CHECK: vmulld 1, 2, 3
+0x10 0x22 0x19 0xc9
+
+# CHECK: vmodsw 21, 11, 10
+0x12 0xab 0x57 0x8b
+
+# CHECK: vmoduw 21, 11, 10
+0x12 0xab 0x56 0x8b
+
+# CHECK: vmodsd 21, 11, 10
+0x12 0xab 0x57 0xcb
+
+# CHECK: vmodud 21, 11, 10
+0x12 0xab 0x56 0xcb
+
+# CHECK: vdivsw 21, 11, 10
+0x12 0xab 0x51 0x8b
+
+# CHECK: vdivuw 21, 11, 10
+0x12 0xab 0x50 0x8b
+
+# CHECK: vdivsd 21, 11, 10
+0x12 0xab 0x51 0xcb
+
+# CHECK: vdivud 21, 11, 10
+0x12 0xab 0x50 0xcb
+
+# CHECK: vmulhsw 1, 2, 3
+0x10 0x22 0x1b 0x89
+
+# CHECK: vmulhuw 1, 2, 3
+0x10 0x22 0x1a 0x89
+
+# CHECK: vmulhsd 1, 2, 3
+0x10 0x22 0x1b 0xc9
+
+# CHECK: vmulhud 1, 2, 3
+0x10 0x22 0x1a 0xc9
+
+# CHECK: vdivesw 21, 11, 10
+0x12 0xab 0x53 0x8b
+
+# CHECK: vdiveuw 21, 11, 10
+0x12 0xab 0x52 0x8b
+
+# CHECK: vdivesd 21, 11, 10
+0x12 0xab 0x53 0xcb
+
+# CHECK: vdiveud 21, 11, 10
+0x12 0xab 0x52 0xcb
+
# CHECK: vinsw 2, 3, 12
0x10 0x4c 0x18 0xcf
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
index b144493eb2a9..c9f5547dd4c8 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -357,6 +357,57 @@
# CHECK-BE: vsrdbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x23,0x56]
# CHECK-LE: vsrdbi 2, 3, 4, 5 # encoding: [0x56,0x23,0x43,0x10]
vsrdbi 2, 3, 4, 5
+# CHECK-BE: vmulld 1, 2, 3 # encoding: [0x10,0x22,0x19,0xc9]
+# CHECK-LE: vmulld 1, 2, 3 # encoding: [0xc9,0x19,0x22,0x10]
+ vmulld 1, 2, 3
+# CHECK-BE: vmulhsw 1, 2, 3 # encoding: [0x10,0x22,0x1b,0x89]
+# CHECK-LE: vmulhsw 1, 2, 3 # encoding: [0x89,0x1b,0x22,0x10]
+ vmulhsw 1, 2, 3
+# CHECK-BE: vmulhuw 1, 2, 3 # encoding: [0x10,0x22,0x1a,0x89]
+# CHECK-LE: vmulhuw 1, 2, 3 # encoding: [0x89,0x1a,0x22,0x10]
+ vmulhuw 1, 2, 3
+# CHECK-BE: vmulhsd 1, 2, 3 # encoding: [0x10,0x22,0x1b,0xc9]
+# CHECK-LE: vmulhsd 1, 2, 3 # encoding: [0xc9,0x1b,0x22,0x10]
+ vmulhsd 1, 2, 3
+# CHECK-BE: vmulhud 1, 2, 3 # encoding: [0x10,0x22,0x1a,0xc9]
+# CHECK-LE: vmulhud 1, 2, 3 # encoding: [0xc9,0x1a,0x22,0x10]
+ vmulhud 1, 2, 3
+# CHECK-BE: vmodsw 21, 11, 10 # encoding: [0x12,0xab,0x57,0x8b]
+# CHECK-LE: vmodsw 21, 11, 10 # encoding: [0x8b,0x57,0xab,0x12]
+ vmodsw 21, 11, 10
+# CHECK-BE: vmoduw 21, 11, 10 # encoding: [0x12,0xab,0x56,0x8b]
+# CHECK-LE: vmoduw 21, 11, 10 # encoding: [0x8b,0x56,0xab,0x12]
+ vmoduw 21, 11, 10
+# CHECK-BE: vmodsd 21, 11, 10 # encoding: [0x12,0xab,0x57,0xcb]
+# CHECK-LE: vmodsd 21, 11, 10 # encoding: [0xcb,0x57,0xab,0x12]
+ vmodsd 21, 11, 10
+# CHECK-BE: vmodud 21, 11, 10 # encoding: [0x12,0xab,0x56,0xcb]
+# CHECK-LE: vmodud 21, 11, 10 # encoding: [0xcb,0x56,0xab,0x12]
+ vmodud 21, 11, 10
+# CHECK-BE: vdivsw 21, 11, 10 # encoding: [0x12,0xab,0x51,0x8b]
+# CHECK-LE: vdivsw 21, 11, 10 # encoding: [0x8b,0x51,0xab,0x12]
+ vdivsw 21, 11, 10
+# CHECK-BE: vdivuw 21, 11, 10 # encoding: [0x12,0xab,0x50,0x8b]
+# CHECK-LE: vdivuw 21, 11, 10 # encoding: [0x8b,0x50,0xab,0x12]
+ vdivuw 21, 11, 10
+# CHECK-BE: vdivsd 21, 11, 10 # encoding: [0x12,0xab,0x51,0xcb]
+# CHECK-LE: vdivsd 21, 11, 10 # encoding: [0xcb,0x51,0xab,0x12]
+ vdivsd 21, 11, 10
+# CHECK-BE: vdivud 21, 11, 10 # encoding: [0x12,0xab,0x50,0xcb]
+# CHECK-LE: vdivud 21, 11, 10 # encoding: [0xcb,0x50,0xab,0x12]
+ vdivud 21, 11, 10
+# CHECK-BE: vdivesw 21, 11, 10 # encoding: [0x12,0xab,0x53,0x8b]
+# CHECK-LE: vdivesw 21, 11, 10 # encoding: [0x8b,0x53,0xab,0x12]
+ vdivesw 21, 11, 10
+# CHECK-BE: vdiveuw 21, 11, 10 # encoding: [0x12,0xab,0x52,0x8b]
+# CHECK-LE: vdiveuw 21, 11, 10 # encoding: [0x8b,0x52,0xab,0x12]
+ vdiveuw 21, 11, 10
+# CHECK-BE: vdivesd 21, 11, 10 # encoding: [0x12,0xab,0x53,0xcb]
+# CHECK-LE: vdivesd 21, 11, 10 # encoding: [0xcb,0x53,0xab,0x12]
+ vdivesd 21, 11, 10
+# CHECK-BE: vdiveud 21, 11, 10 # encoding: [0x12,0xab,0x52,0xcb]
+# CHECK-LE: vdiveud 21, 11, 10 # encoding: [0xcb,0x52,0xab,0x12]
+ vdiveud 21, 11, 10
# CHECK-BE: vinsw 2, 3, 12 # encoding: [0x10,0x4c,0x18,0xcf]
# CHECK-LE: vinsw 2, 3, 12 # encoding: [0xcf,0x18,0x4c,0x10]
vinsw 2, 3, 12
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