[PATCH] D83357: [llvm][sve] Reg + Imm addressing mode for ld1ro.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:12229
   EVT VT = N->getValueType(0);
+  if (VT == MVT::nxv8bf16 &&
+      !static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasBF16())
----------------
This change doesn't seem to be tested. Does this belong in a separate patch?


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:7725
+  // Reg + Imm addressing mode
+    def : Pat<(Ty (Ld1ro PPR3bAny:$gp, (add GPR64:$base, (i64 simm4s32:$imm)))),
+              (!cast<Instruction>(NAME) $gp, $base, simm4s32:$imm)>;
----------------
A few questions:
- Should this pattern also use `(PredTy PPR3bAny:$gp)`?
- Why `2` in `AddedComplexity = 2` ?
- Is AddedComplexity needed at all? (it already looks more 'complex' than the other pattern)

nit: i don't know why `gp` is used here instead of `Pg`, which is used in the rest of file.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83357/new/

https://reviews.llvm.org/D83357