[PATCH] D84056: [FPEnv] Don't transform FSUB(-0, X) -> FNEG(X) in SelectionDAGBuilder.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:9274-9275
+  case ISD::FSUB: {
+    // FSUB(-0.0,X) can be lowered or combined as a bit operation.
+    // Need to check its input recursively to handle.
+    ConstantFPSDNode *N0C = isConstOrConstSplatFP(Op.getOperand(0), true);
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I thought the point was this cannot be lowered this way?


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Comment at: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmed3.ll:39
   %med3 = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)
   %neg.med3 = fsub float -0.0, %med3
   %med3.user = fmul float %med3, 4.0
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This is a code size regression. We probably need 

This should just change to use fneg. We could probably consider the fsub case in performFNegCombine though


Repository:
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  https://reviews.llvm.org/D84056/new/

https://reviews.llvm.org/D84056