[PATCH] D83765: [SVE] Add lowering for scalable vector fadd, fdiv, fmul and fsub operations.

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added a comment.

> then convert it back to an unpredicated operation

Ehh, sort of. The all-1 predicate isn't *really* all-1s. It's all-1s for the fixed-width. E.g.:

  ; CHECK-NEXT:    ptrue p0.d
  ; CHECK-NEXT:    fmla z2.s, p0/m, z0.s, z1.s


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83765/new/

https://reviews.llvm.org/D83765