[llvm] a5405a2 - [NFC][ARM] Add SimplifyCFG tests
Sam Parker via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 14 03:11:16 PDT 2020
Author: Sam Parker
Date: 2020-07-14T11:10:11+01:00
New Revision: a5405a2f0503c02b1cd5c89b8f7bc2bcb733a58c
URL: https://github.com/llvm/llvm-project/commit/a5405a2f0503c02b1cd5c89b8f7bc2bcb733a58c
DIFF: https://github.com/llvm/llvm-project/commit/a5405a2f0503c02b1cd5c89b8f7bc2bcb733a58c.diff
LOG: [NFC][ARM] Add SimplifyCFG tests
Added:
llvm/test/Transforms/SimplifyCFG/ARM/speculate-math.ll
llvm/test/Transforms/SimplifyCFG/ARM/speculate-vector-ops.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/Transforms/SimplifyCFG/ARM/speculate-math.ll b/llvm/test/Transforms/SimplifyCFG/ARM/speculate-math.ll
new file mode 100644
index 000000000000..229d453d00e0
--- /dev/null
+++ b/llvm/test/Transforms/SimplifyCFG/ARM/speculate-math.ll
@@ -0,0 +1,360 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -simplifycfg -mtriple=thumbv8.1m.main -mattr=+mve < %s | FileCheck %s --check-prefix=CHECK-MVE
+; RUN: opt -S -simplifycfg -mtriple=thumbv8m.main < %s | FileCheck %s --check-prefix=CHECK-V8M-MAIN
+; RUN: opt -S -simplifycfg -mtriple=thumbv8m.base < %s | FileCheck %s --check-prefix=CHECK-V8M-BASE
+
+declare float @llvm.sqrt.f32(float) nounwind readonly
+declare float @llvm.fma.f32(float, float, float) nounwind readonly
+declare float @llvm.fmuladd.f32(float, float, float) nounwind readonly
+declare float @llvm.fabs.f32(float) nounwind readonly
+declare float @llvm.minnum.f32(float, float) nounwind readonly
+declare float @llvm.maxnum.f32(float, float) nounwind readonly
+declare float @llvm.minimum.f32(float, float) nounwind readonly
+declare float @llvm.maximum.f32(float, float) nounwind readonly
+
+define double @fdiv_test(double %a, double %b) {
+; CHECK-MVE-LABEL: @fdiv_test(
+; CHECK-MVE-NEXT: entry:
+; CHECK-MVE-NEXT: [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00
+; CHECK-MVE-NEXT: [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]]
+; CHECK-MVE-NEXT: [[COND:%.*]] = select nsz i1 [[CMP]], double [[DIV]], double 0.000000e+00
+; CHECK-MVE-NEXT: ret double [[COND]]
+;
+; CHECK-V8M-MAIN-LABEL: @fdiv_test(
+; CHECK-V8M-MAIN-NEXT: entry:
+; CHECK-V8M-MAIN-NEXT: [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00
+; CHECK-V8M-MAIN-NEXT: [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]]
+; CHECK-V8M-MAIN-NEXT: [[COND:%.*]] = select nsz i1 [[CMP]], double [[DIV]], double 0.000000e+00
+; CHECK-V8M-MAIN-NEXT: ret double [[COND]]
+;
+; CHECK-V8M-BASE-LABEL: @fdiv_test(
+; CHECK-V8M-BASE-NEXT: entry:
+; CHECK-V8M-BASE-NEXT: [[CMP:%.*]] = fcmp ogt double [[A:%.*]], 0.000000e+00
+; CHECK-V8M-BASE-NEXT: [[DIV:%.*]] = fdiv double [[B:%.*]], [[A]]
+; CHECK-V8M-BASE-NEXT: [[COND:%.*]] = select nsz i1 [[CMP]], double [[DIV]], double 0.000000e+00
+; CHECK-V8M-BASE-NEXT: ret double [[COND]]
+;
+entry:
+ %cmp = fcmp ogt double %a, 0.0
+ br i1 %cmp, label %cond.true, label %cond.end
+
+cond.true:
+ %div = fdiv double %b, %a
+ br label %cond.end
+
+cond.end:
+ %cond = phi nsz double [ %div, %cond.true ], [ 0.0, %entry ]
+ ret double %cond
+}
+
+define void @sqrt_test(float addrspace(1)* noalias nocapture %out, float %a) nounwind {
+; CHECK-MVE-LABEL: @sqrt_test(
+; CHECK-MVE-NEXT: entry:
+; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #3
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-MVE-NEXT: ret void
+;
+; CHECK-V8M-MAIN-LABEL: @sqrt_test(
+; CHECK-V8M-MAIN-NEXT: entry:
+; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #2
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-MAIN-NEXT: ret void
+;
+; CHECK-V8M-BASE-LABEL: @sqrt_test(
+; CHECK-V8M-BASE-NEXT: entry:
+; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.sqrt.f32(float [[A]]) #2
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select afn i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-BASE-NEXT: ret void
+;
+entry:
+ %cmp.i = fcmp olt float %a, 0.000000e+00
+ br i1 %cmp.i, label %test_sqrt.exit, label %cond.else.i
+
+cond.else.i: ; preds = %entry
+ %0 = tail call float @llvm.sqrt.f32(float %a) nounwind readnone
+ br label %test_sqrt.exit
+
+test_sqrt.exit: ; preds = %cond.else.i, %entry
+ %cond.i = phi afn float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
+ store float %cond.i, float addrspace(1)* %out, align 4
+ ret void
+}
+
+define void @fabs_test(float addrspace(1)* noalias nocapture %out, float %a) nounwind {
+; CHECK-MVE-LABEL: @fabs_test(
+; CHECK-MVE-NEXT: entry:
+; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #3
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-MVE-NEXT: ret void
+;
+; CHECK-V8M-MAIN-LABEL: @fabs_test(
+; CHECK-V8M-MAIN-NEXT: entry:
+; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #2
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-MAIN-NEXT: ret void
+;
+; CHECK-V8M-BASE-LABEL: @fabs_test(
+; CHECK-V8M-BASE-NEXT: entry:
+; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fabs.f32(float [[A]]) #2
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-BASE-NEXT: ret void
+;
+entry:
+ %cmp.i = fcmp olt float %a, 0.000000e+00
+ br i1 %cmp.i, label %test_fabs.exit, label %cond.else.i
+
+cond.else.i: ; preds = %entry
+ %0 = tail call float @llvm.fabs.f32(float %a) nounwind readnone
+ br label %test_fabs.exit
+
+test_fabs.exit: ; preds = %cond.else.i, %entry
+ %cond.i = phi reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
+ store float %cond.i, float addrspace(1)* %out, align 4
+ ret void
+}
+
+define void @fma_test(float addrspace(1)* noalias nocapture %out, float %a, float %b, float %c) nounwind {
+; CHECK-MVE-LABEL: @fma_test(
+; CHECK-MVE-NEXT: entry:
+; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #3
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-MVE-NEXT: ret void
+;
+; CHECK-V8M-MAIN-LABEL: @fma_test(
+; CHECK-V8M-MAIN-NEXT: entry:
+; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-MAIN-NEXT: ret void
+;
+; CHECK-V8M-BASE-LABEL: @fma_test(
+; CHECK-V8M-BASE-NEXT: entry:
+; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fma.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-BASE-NEXT: ret void
+;
+entry:
+ %cmp.i = fcmp olt float %a, 0.000000e+00
+ br i1 %cmp.i, label %test_fma.exit, label %cond.else.i
+
+cond.else.i: ; preds = %entry
+ %0 = tail call float @llvm.fma.f32(float %a, float %b, float %c) nounwind readnone
+ br label %test_fma.exit
+
+test_fma.exit: ; preds = %cond.else.i, %entry
+ %cond.i = phi nsz reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
+ store float %cond.i, float addrspace(1)* %out, align 4
+ ret void
+}
+
+define void @fmuladd_test(float addrspace(1)* noalias nocapture %out, float %a, float %b, float %c) nounwind {
+; CHECK-MVE-LABEL: @fmuladd_test(
+; CHECK-MVE-NEXT: entry:
+; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #3
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-MVE-NEXT: ret void
+;
+; CHECK-V8M-MAIN-LABEL: @fmuladd_test(
+; CHECK-V8M-MAIN-NEXT: entry:
+; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-MAIN-NEXT: ret void
+;
+; CHECK-V8M-BASE-LABEL: @fmuladd_test(
+; CHECK-V8M-BASE-NEXT: entry:
+; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.fmuladd.f32(float [[A]], float [[B:%.*]], float [[C:%.*]]) #2
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select ninf i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-BASE-NEXT: ret void
+;
+entry:
+ %cmp.i = fcmp olt float %a, 0.000000e+00
+ br i1 %cmp.i, label %test_fmuladd.exit, label %cond.else.i
+
+cond.else.i: ; preds = %entry
+ %0 = tail call float @llvm.fmuladd.f32(float %a, float %b, float %c) nounwind readnone
+ br label %test_fmuladd.exit
+
+test_fmuladd.exit: ; preds = %cond.else.i, %entry
+ %cond.i = phi ninf float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
+ store float %cond.i, float addrspace(1)* %out, align 4
+ ret void
+}
+
+define void @minnum_test(float addrspace(1)* noalias nocapture %out, float %a, float %b) nounwind {
+; CHECK-MVE-LABEL: @minnum_test(
+; CHECK-MVE-NEXT: entry:
+; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #3
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-MVE-NEXT: ret void
+;
+; CHECK-V8M-MAIN-LABEL: @minnum_test(
+; CHECK-V8M-MAIN-NEXT: entry:
+; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-MAIN-NEXT: ret void
+;
+; CHECK-V8M-BASE-LABEL: @minnum_test(
+; CHECK-V8M-BASE-NEXT: entry:
+; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minnum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-BASE-NEXT: ret void
+;
+entry:
+ %cmp.i = fcmp olt float %a, 0.000000e+00
+ br i1 %cmp.i, label %test_minnum.exit, label %cond.else.i
+
+cond.else.i: ; preds = %entry
+ %0 = tail call float @llvm.minnum.f32(float %a, float %b) nounwind readnone
+ br label %test_minnum.exit
+
+test_minnum.exit: ; preds = %cond.else.i, %entry
+ %cond.i = phi float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
+ store float %cond.i, float addrspace(1)* %out, align 4
+ ret void
+}
+
+define void @maxnum_test(float addrspace(1)* noalias nocapture %out, float %a, float %b) nounwind {
+; CHECK-MVE-LABEL: @maxnum_test(
+; CHECK-MVE-NEXT: entry:
+; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #3
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-MVE-NEXT: ret void
+;
+; CHECK-V8M-MAIN-LABEL: @maxnum_test(
+; CHECK-V8M-MAIN-NEXT: entry:
+; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-MAIN-NEXT: ret void
+;
+; CHECK-V8M-BASE-LABEL: @maxnum_test(
+; CHECK-V8M-BASE-NEXT: entry:
+; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maxnum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select ninf nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-BASE-NEXT: ret void
+;
+entry:
+ %cmp.i = fcmp olt float %a, 0.000000e+00
+ br i1 %cmp.i, label %test_maxnum.exit, label %cond.else.i
+
+cond.else.i: ; preds = %entry
+ %0 = tail call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone
+ br label %test_maxnum.exit
+
+test_maxnum.exit: ; preds = %cond.else.i, %entry
+ %cond.i = phi ninf nsz float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
+ store float %cond.i, float addrspace(1)* %out, align 4
+ ret void
+}
+
+define void @minimum_test(float addrspace(1)* noalias nocapture %out, float %a, float %b) nounwind {
+; CHECK-MVE-LABEL: @minimum_test(
+; CHECK-MVE-NEXT: entry:
+; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #3
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-MVE-NEXT: ret void
+;
+; CHECK-V8M-MAIN-LABEL: @minimum_test(
+; CHECK-V8M-MAIN-NEXT: entry:
+; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-MAIN-NEXT: ret void
+;
+; CHECK-V8M-BASE-LABEL: @minimum_test(
+; CHECK-V8M-BASE-NEXT: entry:
+; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.minimum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select reassoc i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-BASE-NEXT: ret void
+;
+entry:
+ %cmp.i = fcmp olt float %a, 0.000000e+00
+ br i1 %cmp.i, label %test_minimum.exit, label %cond.else.i
+
+cond.else.i: ; preds = %entry
+ %0 = tail call float @llvm.minimum.f32(float %a, float %b) nounwind readnone
+ br label %test_minimum.exit
+
+test_minimum.exit: ; preds = %cond.else.i, %entry
+ %cond.i = phi reassoc float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
+ store float %cond.i, float addrspace(1)* %out, align 4
+ ret void
+}
+
+define void @maximum_test(float addrspace(1)* noalias nocapture %out, float %a, float %b) nounwind {
+; CHECK-MVE-LABEL: @maximum_test(
+; CHECK-MVE-NEXT: entry:
+; CHECK-MVE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-MVE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #3
+; CHECK-MVE-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-MVE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-MVE-NEXT: ret void
+;
+; CHECK-V8M-MAIN-LABEL: @maximum_test(
+; CHECK-V8M-MAIN-NEXT: entry:
+; CHECK-V8M-MAIN-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-MAIN-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-MAIN-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-MAIN-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-MAIN-NEXT: ret void
+;
+; CHECK-V8M-BASE-LABEL: @maximum_test(
+; CHECK-V8M-BASE-NEXT: entry:
+; CHECK-V8M-BASE-NEXT: [[CMP_I:%.*]] = fcmp olt float [[A:%.*]], 0.000000e+00
+; CHECK-V8M-BASE-NEXT: [[TMP0:%.*]] = tail call float @llvm.maximum.f32(float [[A]], float [[B:%.*]]) #2
+; CHECK-V8M-BASE-NEXT: [[COND_I:%.*]] = select nsz i1 [[CMP_I]], float 0x7FF8000000000000, float [[TMP0]]
+; CHECK-V8M-BASE-NEXT: store float [[COND_I]], float addrspace(1)* [[OUT:%.*]], align 4
+; CHECK-V8M-BASE-NEXT: ret void
+;
+entry:
+ %cmp.i = fcmp olt float %a, 0.000000e+00
+ br i1 %cmp.i, label %test_maximum.exit, label %cond.else.i
+
+cond.else.i: ; preds = %entry
+ %0 = tail call float @llvm.maximum.f32(float %a, float %b) nounwind readnone
+ br label %test_maximum.exit
+
+test_maximum.exit: ; preds = %cond.else.i, %entry
+ %cond.i = phi nsz float [ %0, %cond.else.i ], [ 0x7FF8000000000000, %entry ]
+ store float %cond.i, float addrspace(1)* %out, align 4
+ ret void
+}
diff --git a/llvm/test/Transforms/SimplifyCFG/ARM/speculate-vector-ops.ll b/llvm/test/Transforms/SimplifyCFG/ARM/speculate-vector-ops.ll
new file mode 100644
index 000000000000..1f74644eb091
--- /dev/null
+++ b/llvm/test/Transforms/SimplifyCFG/ARM/speculate-vector-ops.ll
@@ -0,0 +1,112 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -simplifycfg -mtriple=thumbv8.1m.main -mattr=+mve -S %s -o - | FileCheck %s --check-prefix=CHECK-MVE
+; RUN: opt -simplifycfg -mtriple=thumbv8.1m.main -S %s -o - | FileCheck %s --check-prefix=CHECK-NOMVE
+
+define i32 @speculate_vector_extract(i32 %d, <4 x i32> %v) {
+; CHECK-MVE-LABEL: @speculate_vector_extract(
+; CHECK-MVE-NEXT: entry:
+; CHECK-MVE-NEXT: [[CONV:%.*]] = insertelement <4 x i32> undef, i32 [[D:%.*]], i32 0
+; CHECK-MVE-NEXT: [[CONV2:%.*]] = insertelement <4 x i32> [[CONV]], i32 [[D]], i32 1
+; CHECK-MVE-NEXT: [[CONV3:%.*]] = insertelement <4 x i32> [[CONV2]], i32 [[D]], i32 2
+; CHECK-MVE-NEXT: [[CONV4:%.*]] = insertelement <4 x i32> [[CONV3]], i32 [[D]], i32 3
+; CHECK-MVE-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[CONV4]], <i32 0, i32 -1, i32 -2, i32 -3>
+; CHECK-MVE-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[TMP6]], zeroinitializer
+; CHECK-MVE-NEXT: [[CMP_EXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
+; CHECK-MVE-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[CMP_EXT]], i32 0
+; CHECK-MVE-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[TMP8]], 0
+; CHECK-MVE-NEXT: br i1 [[TOBOOL]], label [[COND_ELSE:%.*]], label [[COND_THEN:%.*]]
+; CHECK-MVE: cond.then:
+; CHECK-MVE-NEXT: [[TMP10:%.*]] = extractelement <4 x i32> [[V:%.*]], i32 0
+; CHECK-MVE-NEXT: br label [[COND_END:%.*]]
+; CHECK-MVE: cond.else:
+; CHECK-MVE-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[V]], i32 3
+; CHECK-MVE-NEXT: br label [[COND_END]]
+; CHECK-MVE: cond.end:
+; CHECK-MVE-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_THEN]] ], [ [[TMP12]], [[COND_ELSE]] ]
+; CHECK-MVE-NEXT: [[TMP14:%.*]] = extractelement <4 x i32> [[CMP_EXT]], i32 1
+; CHECK-MVE-NEXT: [[TOBOOL15:%.*]] = icmp eq i32 [[TMP14]], 0
+; CHECK-MVE-NEXT: [[TMP20:%.*]] = extractelement <4 x i32> [[V]], i32 1
+; CHECK-MVE-NEXT: [[COND22:%.*]] = select i1 [[TOBOOL15]], i32 [[COND]], i32 [[TMP20]]
+; CHECK-MVE-NEXT: [[TMP24:%.*]] = extractelement <4 x i32> [[CMP_EXT]], i32 2
+; CHECK-MVE-NEXT: [[TOBOOL25:%.*]] = icmp eq i32 [[TMP24]], 0
+; CHECK-MVE-NEXT: [[TMP30:%.*]] = extractelement <4 x i32> [[V]], i32 2
+; CHECK-MVE-NEXT: [[COND32:%.*]] = select i1 [[TOBOOL25]], i32 [[COND22]], i32 [[TMP30]]
+; CHECK-MVE-NEXT: ret i32 [[COND32]]
+;
+; CHECK-NOMVE-LABEL: @speculate_vector_extract(
+; CHECK-NOMVE-NEXT: entry:
+; CHECK-NOMVE-NEXT: [[CONV:%.*]] = insertelement <4 x i32> undef, i32 [[D:%.*]], i32 0
+; CHECK-NOMVE-NEXT: [[CONV2:%.*]] = insertelement <4 x i32> [[CONV]], i32 [[D]], i32 1
+; CHECK-NOMVE-NEXT: [[CONV3:%.*]] = insertelement <4 x i32> [[CONV2]], i32 [[D]], i32 2
+; CHECK-NOMVE-NEXT: [[CONV4:%.*]] = insertelement <4 x i32> [[CONV3]], i32 [[D]], i32 3
+; CHECK-NOMVE-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[CONV4]], <i32 0, i32 -1, i32 -2, i32 -3>
+; CHECK-NOMVE-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[TMP6]], zeroinitializer
+; CHECK-NOMVE-NEXT: [[CMP_EXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
+; CHECK-NOMVE-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[CMP_EXT]], i32 0
+; CHECK-NOMVE-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[TMP8]], 0
+; CHECK-NOMVE-NEXT: [[TMP10:%.*]] = extractelement <4 x i32> [[V:%.*]], i32 0
+; CHECK-NOMVE-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[V]], i32 3
+; CHECK-NOMVE-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 [[TMP12]], i32 [[TMP10]]
+; CHECK-NOMVE-NEXT: [[TMP14:%.*]] = extractelement <4 x i32> [[CMP_EXT]], i32 1
+; CHECK-NOMVE-NEXT: [[TOBOOL15:%.*]] = icmp eq i32 [[TMP14]], 0
+; CHECK-NOMVE-NEXT: [[TMP20:%.*]] = extractelement <4 x i32> [[V]], i32 1
+; CHECK-NOMVE-NEXT: [[COND22:%.*]] = select i1 [[TOBOOL15]], i32 [[COND]], i32 [[TMP20]]
+; CHECK-NOMVE-NEXT: [[TMP24:%.*]] = extractelement <4 x i32> [[CMP_EXT]], i32 2
+; CHECK-NOMVE-NEXT: [[TOBOOL25:%.*]] = icmp eq i32 [[TMP24]], 0
+; CHECK-NOMVE-NEXT: [[TMP30:%.*]] = extractelement <4 x i32> [[V]], i32 2
+; CHECK-NOMVE-NEXT: [[COND32:%.*]] = select i1 [[TOBOOL25]], i32 [[COND22]], i32 [[TMP30]]
+; CHECK-NOMVE-NEXT: ret i32 [[COND32]]
+;
+entry:
+ %conv = insertelement <4 x i32> undef, i32 %d, i32 0
+ %conv2 = insertelement <4 x i32> %conv, i32 %d, i32 1
+ %conv3 = insertelement <4 x i32> %conv2, i32 %d, i32 2
+ %conv4 = insertelement <4 x i32> %conv3, i32 %d, i32 3
+ %tmp6 = add nsw <4 x i32> %conv4, <i32 0, i32 -1, i32 -2, i32 -3>
+ %cmp = icmp eq <4 x i32> %tmp6, zeroinitializer
+ %cmp.ext = sext <4 x i1> %cmp to <4 x i32>
+ %tmp8 = extractelement <4 x i32> %cmp.ext, i32 0
+ %tobool = icmp eq i32 %tmp8, 0
+ br i1 %tobool, label %cond.else, label %cond.then
+
+return: ; preds = %cond.end28
+ ret i32 %cond32
+
+cond.then: ; preds = %entry
+ %tmp10 = extractelement <4 x i32> %v, i32 0
+ br label %cond.end
+
+cond.else: ; preds = %entry
+ %tmp12 = extractelement <4 x i32> %v, i32 3
+ br label %cond.end
+
+cond.end: ; preds = %cond.else, %cond.then
+ %cond = phi i32 [ %tmp10, %cond.then ], [ %tmp12, %cond.else ]
+ %tmp14 = extractelement <4 x i32> %cmp.ext, i32 1
+ %tobool15 = icmp eq i32 %tmp14, 0
+ br i1 %tobool15, label %cond.else17, label %cond.then16
+
+cond.then16: ; preds = %cond.end
+ %tmp20 = extractelement <4 x i32> %v, i32 1
+ br label %cond.end18
+
+cond.else17: ; preds = %cond.end
+ br label %cond.end18
+
+cond.end18: ; preds = %cond.else17, %cond.then16
+ %cond22 = phi i32 [ %tmp20, %cond.then16 ], [ %cond, %cond.else17 ]
+ %tmp24 = extractelement <4 x i32> %cmp.ext, i32 2
+ %tobool25 = icmp eq i32 %tmp24, 0
+ br i1 %tobool25, label %cond.else27, label %cond.then26
+
+cond.then26: ; preds = %cond.end18
+ %tmp30 = extractelement <4 x i32> %v, i32 2
+ br label %cond.end28
+
+cond.else27: ; preds = %cond.end18
+ br label %cond.end28
+
+cond.end28: ; preds = %cond.else27, %cond.then26
+ %cond32 = phi i32 [ %tmp30, %cond.then26 ], [ %cond22, %cond.else27 ]
+ br label %return
+}
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