[PATCH] D81993: [AArch64][GlobalISel] Add post-legalize combine for sext(trunc(sextload)) -> trunc/copy

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp:447
+    Register Dst = MI.getOperand(0).getReg();
+    unsigned DstSize = MRI.getType(Dst).getSizeInBits();
+    if (MI.hasOneMemOperand())
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I think this needs to be careful about a vector sextload


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81993/new/

https://reviews.llvm.org/D81993