[PATCH] D83137: [SVE][CodeGen] Legalisation of masked loads and stores

Fri Jul 10 14:23:10 PDT 2020

efriedma accepted this revision.
efriedma added a comment.

LGTM

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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1096

+  // Extract lo/hi halves of legal predicate types.
+  def : Pat<(nxv2i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 0))),
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kmclaughlin wrote:
> efriedma wrote:
> > Do we need to support extracting, for example, an nxv2i1 from an nxv16i1?
> We may need to support extracting a nxv2i1 from an nxv16i1, etc at some point, though I don't believe there are any code paths which would require this just now? At least, for the purposes of this patch I think we just need those patterns where the index is either 0 or half the number of elements.
We do have a DAGCombine for EXTRACT_SUBVECTOR of an EXTRACT_SUBVECTOR; it isn't triggering here for some reason?  I guess that's okay.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83137/new/

https://reviews.llvm.org/D83137