[llvm] 90b1a71 - [PowerPC] Enable default support of quad precision operations
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 10 11:27:55 PDT 2020
Author: Lei Huang
Date: 2020-07-10T13:27:48-05:00
New Revision: 90b1a710aede2b276cda47538142fef6f5253361
URL: https://github.com/llvm/llvm-project/commit/90b1a710aede2b276cda47538142fef6f5253361
DIFF: https://github.com/llvm/llvm-project/commit/90b1a710aede2b276cda47538142fef6f5253361.diff
LOG: [PowerPC] Enable default support of quad precision operations
Summary: Remove option guarding support of quad precision operations.
Reviewers: nemanjai, #powerpc, steven.zhang
Reviewed By: nemanjai, #powerpc, steven.zhang
Subscribers: qiucf, wuzish, nemanjai, hiraditya, kbarton, shchenz, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D83437
Added:
Modified:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
llvm/test/CodeGen/PowerPC/constant-pool.ll
llvm/test/CodeGen/PowerPC/f128-aggregates.ll
llvm/test/CodeGen/PowerPC/f128-arith.ll
llvm/test/CodeGen/PowerPC/f128-bitcast.ll
llvm/test/CodeGen/PowerPC/f128-compare.ll
llvm/test/CodeGen/PowerPC/f128-conv.ll
llvm/test/CodeGen/PowerPC/f128-fma.ll
llvm/test/CodeGen/PowerPC/f128-passByValue.ll
llvm/test/CodeGen/PowerPC/f128-rounding.ll
llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll
llvm/test/CodeGen/PowerPC/float-load-store-pair.ll
llvm/test/CodeGen/PowerPC/fp-strict-f128.ll
llvm/test/CodeGen/PowerPC/global-address-non-got-indirect-access.ll
llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll
llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
llvm/test/CodeGen/PowerPC/recipest.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 229c5a76010c..49140bab5134 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -117,9 +117,6 @@ cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
-static cl::opt<bool> EnableQuadPrecision("enable-ppc-quad-precision",
-cl::desc("enable quad precision float support on ppc"), cl::Hidden);
-
static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
cl::desc("use absolute jump tables on ppc"), cl::Hidden);
@@ -1004,61 +1001,59 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::SRL, MVT::v1i128, Legal);
setOperationAction(ISD::SRA, MVT::v1i128, Expand);
- if (EnableQuadPrecision) {
- addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
- setOperationAction(ISD::FADD, MVT::f128, Legal);
- setOperationAction(ISD::FSUB, MVT::f128, Legal);
- setOperationAction(ISD::FDIV, MVT::f128, Legal);
- setOperationAction(ISD::FMUL, MVT::f128, Legal);
- setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
- // No extending loads to f128 on PPC.
- for (MVT FPT : MVT::fp_valuetypes())
- setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
- setOperationAction(ISD::FMA, MVT::f128, Legal);
- setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
- setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
- setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
- setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
- setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
- setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
-
- setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
- setOperationAction(ISD::FRINT, MVT::f128, Legal);
- setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
- setOperationAction(ISD::FCEIL, MVT::f128, Legal);
- setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
- setOperationAction(ISD::FROUND, MVT::f128, Legal);
-
- setOperationAction(ISD::SELECT, MVT::f128, Expand);
- setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
- setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
- setTruncStoreAction(MVT::f128, MVT::f64, Expand);
- setTruncStoreAction(MVT::f128, MVT::f32, Expand);
- setOperationAction(ISD::BITCAST, MVT::i128, Custom);
- // No implementation for these ops for PowerPC.
- setOperationAction(ISD::FSIN , MVT::f128, Expand);
- setOperationAction(ISD::FCOS , MVT::f128, Expand);
- setOperationAction(ISD::FPOW, MVT::f128, Expand);
- setOperationAction(ISD::FPOWI, MVT::f128, Expand);
- setOperationAction(ISD::FREM, MVT::f128, Expand);
-
- // Handle constrained floating-point operations of fp128
- setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal);
- setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal);
- setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal);
- setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal);
- setOperationAction(ISD::STRICT_FMA, MVT::f128, Legal);
- setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal);
- setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal);
- setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
- setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
- setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal);
- setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal);
- setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal);
- setOperationAction(ISD::STRICT_FCEIL, MVT::f128, Legal);
- setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal);
- setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal);
- }
+ addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
+ setOperationAction(ISD::FADD, MVT::f128, Legal);
+ setOperationAction(ISD::FSUB, MVT::f128, Legal);
+ setOperationAction(ISD::FDIV, MVT::f128, Legal);
+ setOperationAction(ISD::FMUL, MVT::f128, Legal);
+ setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
+ // No extending loads to f128 on PPC.
+ for (MVT FPT : MVT::fp_valuetypes())
+ setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
+ setOperationAction(ISD::FMA, MVT::f128, Legal);
+ setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
+ setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
+ setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
+ setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
+ setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
+ setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
+
+ setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
+ setOperationAction(ISD::FRINT, MVT::f128, Legal);
+ setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
+ setOperationAction(ISD::FCEIL, MVT::f128, Legal);
+ setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
+ setOperationAction(ISD::FROUND, MVT::f128, Legal);
+
+ setOperationAction(ISD::SELECT, MVT::f128, Expand);
+ setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
+ setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
+ setTruncStoreAction(MVT::f128, MVT::f64, Expand);
+ setTruncStoreAction(MVT::f128, MVT::f32, Expand);
+ setOperationAction(ISD::BITCAST, MVT::i128, Custom);
+ // No implementation for these ops for PowerPC.
+ setOperationAction(ISD::FSIN, MVT::f128, Expand);
+ setOperationAction(ISD::FCOS, MVT::f128, Expand);
+ setOperationAction(ISD::FPOW, MVT::f128, Expand);
+ setOperationAction(ISD::FPOWI, MVT::f128, Expand);
+ setOperationAction(ISD::FREM, MVT::f128, Expand);
+
+ // Handle constrained floating-point operations of fp128
+ setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal);
+ setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal);
+ setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal);
+ setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal);
+ setOperationAction(ISD::STRICT_FMA, MVT::f128, Legal);
+ setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal);
+ setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal);
+ setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
+ setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
+ setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal);
+ setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal);
+ setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal);
+ setOperationAction(ISD::STRICT_FCEIL, MVT::f128, Legal);
+ setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal);
+ setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal);
setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
@@ -1307,20 +1302,18 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setTargetDAGCombine(ISD::VSELECT);
}
- if (EnableQuadPrecision) {
- setLibcallName(RTLIB::LOG_F128, "logf128");
- setLibcallName(RTLIB::LOG2_F128, "log2f128");
- setLibcallName(RTLIB::LOG10_F128, "log10f128");
- setLibcallName(RTLIB::EXP_F128, "expf128");
- setLibcallName(RTLIB::EXP2_F128, "exp2f128");
- setLibcallName(RTLIB::SIN_F128, "sinf128");
- setLibcallName(RTLIB::COS_F128, "cosf128");
- setLibcallName(RTLIB::POW_F128, "powf128");
- setLibcallName(RTLIB::FMIN_F128, "fminf128");
- setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
- setLibcallName(RTLIB::POWI_F128, "__powikf2");
- setLibcallName(RTLIB::REM_F128, "fmodf128");
- }
+ setLibcallName(RTLIB::LOG_F128, "logf128");
+ setLibcallName(RTLIB::LOG2_F128, "log2f128");
+ setLibcallName(RTLIB::LOG10_F128, "log10f128");
+ setLibcallName(RTLIB::EXP_F128, "expf128");
+ setLibcallName(RTLIB::EXP2_F128, "exp2f128");
+ setLibcallName(RTLIB::SIN_F128, "sinf128");
+ setLibcallName(RTLIB::COS_F128, "cosf128");
+ setLibcallName(RTLIB::POW_F128, "powf128");
+ setLibcallName(RTLIB::FMIN_F128, "fminf128");
+ setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
+ setLibcallName(RTLIB::POWI_F128, "__powikf2");
+ setLibcallName(RTLIB::REM_F128, "fmodf128");
// With 32 condition bits, we don't need to sink (and duplicate) compares
// aggressively in CodeGenPrep.
@@ -8308,7 +8301,7 @@ SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
const SDLoc &dl) const {
// FP to INT conversions are legal for f128.
- if (EnableQuadPrecision && (Op->getOperand(0).getValueType() == MVT::f128))
+ if (Op->getOperand(0).getValueType() == MVT::f128)
return Op;
// Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
@@ -8576,7 +8569,7 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
return LowerINT_TO_FPVector(Op, DAG, dl);
// Conversions to f128 are legal.
- if (EnableQuadPrecision && (Op.getValueType() == MVT::f128))
+ if (Op.getValueType() == MVT::f128)
return Op;
if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
@@ -9104,10 +9097,9 @@ SDValue PPCTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
SDLoc dl(Op);
SDValue Op0 = Op->getOperand(0);
- if (!EnableQuadPrecision ||
- (Op.getValueType() != MVT::f128 ) ||
+ if ((Op.getValueType() != MVT::f128) ||
(Op0.getOpcode() != ISD::BUILD_PAIR) ||
- (Op0.getOperand(0).getValueType() != MVT::i64) ||
+ (Op0.getOperand(0).getValueType() != MVT::i64) ||
(Op0.getOperand(1).getValueType() != MVT::i64))
return SDValue();
@@ -16373,7 +16365,7 @@ bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(const Function &F,
case Type::DoubleTyID:
return true;
case Type::FP128TyID:
- return EnableQuadPrecision && Subtarget.hasP9Vector();
+ return Subtarget.hasP9Vector();
default:
return false;
}
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
index 366493ae76b2..bd8d6099c40f 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll
@@ -1,6 +1,5 @@
-; RUN: llc -verify-machineinstrs -mcpu=pwr9 -enable-ppc-quad-precision \
-; RUN: -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
-; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
@A = common global fp128 0xL00000000000000000000000000000000, align 16
@B = common global fp128 0xL00000000000000000000000000000000, align 16
diff --git a/llvm/test/CodeGen/PowerPC/constant-pool.ll b/llvm/test/CodeGen/PowerPC/constant-pool.ll
index 797fc74672a2..4355cfa6ba21 100644
--- a/llvm/test/CodeGen/PowerPC/constant-pool.ll
+++ b/llvm/test/CodeGen/PowerPC/constant-pool.ll
@@ -1,6 +1,5 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -mcpu=future -enable-ppc-quad-precision -ppc-asm-full-reg-names \
-; RUN: < %s | FileCheck %s
+; RUN: -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s
define float @FloatConstantPool() {
; CHECK-LABEL: FloatConstantPool:
diff --git a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
index 006ad745f607..094d29e2f258 100644
--- a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
@@ -1,9 +1,8 @@
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
-; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN: -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
+; RUN: | FileCheck %s
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
-; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
+; RUN: -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
; RUN: | FileCheck -check-prefix=CHECK-BE %s
; Testing homogeneous aggregates.
diff --git a/llvm/test/CodeGen/PowerPC/f128-arith.ll b/llvm/test/CodeGen/PowerPC/f128-arith.ll
index a957e0e6bdaa..40b123bb9276 100644
--- a/llvm/test/CodeGen/PowerPC/f128-arith.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-arith.ll
@@ -1,5 +1,4 @@
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
; Function Attrs: norecurse nounwind
diff --git a/llvm/test/CodeGen/PowerPC/f128-bitcast.ll b/llvm/test/CodeGen/PowerPC/f128-bitcast.ll
index 68069e542ffd..fca24f5fd541 100644
--- a/llvm/test/CodeGen/PowerPC/f128-bitcast.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-bitcast.ll
@@ -1,10 +1,8 @@
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
-; RUN: -ppc-asm-full-reg-names \
-; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -verify-machineinstrs \
+; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN: FileCheck %s --check-prefix=CHECK-BE
; Function Attrs: norecurse nounwind readnone
define i64 @getPart1(fp128 %in) local_unnamed_addr {
diff --git a/llvm/test/CodeGen/PowerPC/f128-compare.ll b/llvm/test/CodeGen/PowerPC/f128-compare.ll
index c876878f05fa..5376b3b3f1c5 100644
--- a/llvm/test/CodeGen/PowerPC/f128-compare.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-compare.ll
@@ -1,5 +1,4 @@
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
@a_qp = common global fp128 0xL00000000000000000000000000000000, align 16
diff --git a/llvm/test/CodeGen/PowerPC/f128-conv.ll b/llvm/test/CodeGen/PowerPC/f128-conv.ll
index 4c64341d6349..2cb317492545 100644
--- a/llvm/test/CodeGen/PowerPC/f128-conv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-conv.ll
@@ -1,6 +1,6 @@
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
-; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN: -ppc-vsr-nums-as-vr -verify-machineinstrs -ppc-asm-full-reg-names < %s \
+; RUN: | FileCheck %s
@mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8
@umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
diff --git a/llvm/test/CodeGen/PowerPC/f128-fma.ll b/llvm/test/CodeGen/PowerPC/f128-fma.ll
index 8f76520d32bd..f63ae04699f4 100644
--- a/llvm/test/CodeGen/PowerPC/f128-fma.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-fma.ll
@@ -1,6 +1,5 @@
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
-; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
define void @qpFmadd(fp128* nocapture readonly %a, fp128* nocapture %b,
fp128* nocapture readonly %c, fp128* nocapture %res) {
diff --git a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll
index cbccaea3bce1..8b2db6b03510 100644
--- a/llvm/test/CodeGen/PowerPC/f128-passByValue.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-passByValue.ll
@@ -1,5 +1,4 @@
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
; Function Attrs: norecurse nounwind readnone
diff --git a/llvm/test/CodeGen/PowerPC/f128-rounding.ll b/llvm/test/CodeGen/PowerPC/f128-rounding.ll
index 063eb1456fd8..56f63be5734e 100644
--- a/llvm/test/CodeGen/PowerPC/f128-rounding.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-rounding.ll
@@ -1,5 +1,4 @@
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
diff --git a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
index ebded9dcccbe..10d56fb2c47a 100644
--- a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
@@ -1,6 +1,6 @@
; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -verify-machineinstrs -enable-ppc-quad-precision \
-; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN: -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
+; RUN: | FileCheck %s
@f128Array = global [4 x fp128] [fp128 0xL00000000000000004004C00000000000,
fp128 0xLF000000000000000400808AB851EB851,
diff --git a/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll b/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll
index bae676cd09cd..8542b1072233 100644
--- a/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
; RUN: -relocation-model=pic -ppc-asm-full-reg-names -verify-machineinstrs \
-; RUN: -enable-ppc-quad-precision < %s | FileCheck %s
+; RUN: < %s | FileCheck %s
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -ppc-vsr-nums-as-vr \
; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \
-; RUN: -enable-ppc-quad-precision < %s | FileCheck %s -check-prefix=CHECK-BE
+; RUN: < %s | FileCheck %s -check-prefix=CHECK-BE
; Vector extract DWord and convert to quad precision.
diff --git a/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll b/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll
index a8ed39ee9ce0..caeff7155334 100644
--- a/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll
+++ b/llvm/test/CodeGen/PowerPC/float-load-store-pair.ll
@@ -52,24 +52,22 @@ define signext i32 @test() nounwind {
; CHECK-NEXT: addis 3, 2, a10 at toc@ha
; CHECK-NEXT: lfd 10, a10 at toc@l(3)
; CHECK-NEXT: addis 3, 2, a11 at toc@ha
-; CHECK-NEXT: addis 6, 2, a17 at toc@ha
+; CHECK-NEXT: lfd 11, a11 at toc@l(3)
+; CHECK-NEXT: addis 3, 2, a12 at toc@ha
; CHECK-NEXT: addis 5, 2, a16 at toc@ha
+; CHECK-NEXT: addis 6, 2, a17 at toc@ha
; CHECK-NEXT: addi 6, 6, a17 at toc@l
-; CHECK-NEXT: addi 5, 5, a16 at toc@l
; CHECK-NEXT: lxvx 34, 0, 6
+; CHECK-NEXT: lfd 12, a12 at toc@l(3)
+; CHECK-NEXT: addis 3, 2, a13 at toc@ha
+; CHECK-NEXT: addi 5, 5, a16 at toc@l
; CHECK-NEXT: addis 4, 2, a15 at toc@ha
; CHECK-NEXT: lxvx 0, 0, 5
; CHECK-NEXT: ld 4, a15 at toc@l(4)
-; CHECK-NEXT: li 5, 168
-; CHECK-NEXT: lfd 11, a11 at toc@l(3)
-; CHECK-NEXT: addis 3, 2, a12 at toc@ha
-; CHECK-NEXT: lfd 12, a12 at toc@l(3)
-; CHECK-NEXT: addis 3, 2, a13 at toc@ha
+; CHECK-NEXT: li 5, 152
; CHECK-NEXT: lfd 13, a13 at toc@l(3)
; CHECK-NEXT: addis 3, 2, a14 at toc@ha
; CHECK-NEXT: ld 3, a14 at toc@l(3)
-; CHECK-NEXT: stxvx 34, 1, 5
-; CHECK-NEXT: li 5, 152
; CHECK-NEXT: stxvx 0, 1, 5
; CHECK-NEXT: std 4, 144(1)
; CHECK-NEXT: std 3, 136(1)
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-f128.ll b/llvm/test/CodeGen/PowerPC/fp-strict-f128.ll
index 21ddb799141d..cab949a6ebd2 100644
--- a/llvm/test/CodeGen/PowerPC/fp-strict-f128.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-f128.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 -enable-ppc-quad-precision=true | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s
declare fp128 @llvm.experimental.constrained.fadd.f128(fp128, fp128, metadata, metadata)
declare fp128 @llvm.experimental.constrained.fsub.f128(fp128, fp128, metadata, metadata)
diff --git a/llvm/test/CodeGen/PowerPC/global-address-non-got-indirect-access.ll b/llvm/test/CodeGen/PowerPC/global-address-non-got-indirect-access.ll
index f29d9bd251ca..5c49760a9f45 100644
--- a/llvm/test/CodeGen/PowerPC/global-address-non-got-indirect-access.ll
+++ b/llvm/test/CodeGen/PowerPC/global-address-non-got-indirect-access.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -mcpu=future -enable-ppc-quad-precision -ppc-asm-full-reg-names \
-; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
+; RUN: -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s \
+; RUN: | FileCheck %s
@_ZL13StaticBoolVar = internal unnamed_addr global i8 0, align 1
@_ZL19StaticSignedCharVar = internal unnamed_addr global i8 0, align 1
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll b/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll
index 7f7659b356ee..c838308f3aa6 100644
--- a/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -mcpu=future -enable-ppc-quad-precision -ppc-asm-full-reg-names \
-; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
+; RUN: -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s \
+; RUN: | FileCheck %s
%struct.Struct = type { i8, i16, i32 }
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
index feb20465c510..4762b10af7dd 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
@@ -1,5 +1,5 @@
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN: -enable-ppc-quad-precision -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s -check-prefix=CHECK-PWR8 \
; RUN: -implicit-check-not "\<setb\>"
diff --git a/llvm/test/CodeGen/PowerPC/recipest.ll b/llvm/test/CodeGen/PowerPC/recipest.ll
index 4276d944af8f..7ceddd95e573 100644
--- a/llvm/test/CodeGen/PowerPC/recipest.ll
+++ b/llvm/test/CodeGen/PowerPC/recipest.ll
@@ -1176,14 +1176,7 @@ define fp128 @hoo5_fmf(fp128 %a) #1 {
;
; CHECK-P9-LABEL: hoo5_fmf:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: mflr 0
-; CHECK-P9-NEXT: std 0, 16(1)
-; CHECK-P9-NEXT: stdu 1, -32(1)
-; CHECK-P9-NEXT: bl sqrtl
-; CHECK-P9-NEXT: nop
-; CHECK-P9-NEXT: addi 1, 1, 32
-; CHECK-P9-NEXT: ld 0, 16(1)
-; CHECK-P9-NEXT: mtlr 0
+; CHECK-P9-NEXT: xssqrtqp 2, 2
; CHECK-P9-NEXT: blr
%r = call reassoc ninf afn fp128 @llvm.sqrt.f128(fp128 %a)
ret fp128 %r
@@ -1216,14 +1209,7 @@ define fp128 @hoo5_safe(fp128 %a) #1 {
;
; CHECK-P9-LABEL: hoo5_safe:
; CHECK-P9: # %bb.0:
-; CHECK-P9-NEXT: mflr 0
-; CHECK-P9-NEXT: std 0, 16(1)
-; CHECK-P9-NEXT: stdu 1, -32(1)
-; CHECK-P9-NEXT: bl sqrtl
-; CHECK-P9-NEXT: nop
-; CHECK-P9-NEXT: addi 1, 1, 32
-; CHECK-P9-NEXT: ld 0, 16(1)
-; CHECK-P9-NEXT: mtlr 0
+; CHECK-P9-NEXT: xssqrtqp 2, 2
; CHECK-P9-NEXT: blr
%r = call fp128 @llvm.sqrt.f128(fp128 %a)
ret fp128 %r
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